1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/mux/ti-serdes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-am642.dtsi" 14 15/ { 16 compatible = "ti,am642-evm", "ti,am642"; 17 model = "Texas Instruments AM642 EVM"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 2G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 28 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 38 alignment = <0x1000>; 39 no-map; 40 }; 41 42 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa0000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa0100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa1000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa1100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa2000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa2100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa3000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa3100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 rtos_ipc_memory_region: ipc-memories@a5000000 { 91 reg = <0x00 0xa5000000 0x00 0x00800000>; 92 alignment = <0x1000>; 93 no-map; 94 }; 95 }; 96 97 evm_12v0: fixedregulator-evm12v0 { 98 /* main DC jack */ 99 compatible = "regulator-fixed"; 100 regulator-name = "evm_12v0"; 101 regulator-min-microvolt = <12000000>; 102 regulator-max-microvolt = <12000000>; 103 regulator-always-on; 104 regulator-boot-on; 105 }; 106 107 vsys_5v0: fixedregulator-vsys5v0 { 108 /* output of LM5140 */ 109 compatible = "regulator-fixed"; 110 regulator-name = "vsys_5v0"; 111 regulator-min-microvolt = <5000000>; 112 regulator-max-microvolt = <5000000>; 113 vin-supply = <&evm_12v0>; 114 regulator-always-on; 115 regulator-boot-on; 116 }; 117 118 vsys_3v3: fixedregulator-vsys3v3 { 119 /* output of LM5140 */ 120 compatible = "regulator-fixed"; 121 regulator-name = "vsys_3v3"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 vin-supply = <&evm_12v0>; 125 regulator-always-on; 126 regulator-boot-on; 127 }; 128 129 vdd_mmc1: fixed-regulator-sd { 130 /* TPS2051BD */ 131 compatible = "regulator-fixed"; 132 regulator-name = "vdd_mmc1"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 regulator-boot-on; 136 enable-active-high; 137 vin-supply = <&vsys_3v3>; 138 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; 139 }; 140 141 vddb: fixedregulator-vddb { 142 compatible = "regulator-fixed"; 143 regulator-name = "vddb_3v3_display"; 144 regulator-min-microvolt = <3300000>; 145 regulator-max-microvolt = <3300000>; 146 vin-supply = <&vsys_3v3>; 147 regulator-always-on; 148 regulator-boot-on; 149 }; 150 151 leds { 152 compatible = "gpio-leds"; 153 154 led-0 { 155 label = "am64-evm:red:heartbeat"; 156 gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; 157 linux,default-trigger = "heartbeat"; 158 function = LED_FUNCTION_HEARTBEAT; 159 default-state = "off"; 160 }; 161 }; 162 163 mdio_mux: mux-controller { 164 compatible = "gpio-mux"; 165 #mux-control-cells = <0>; 166 167 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; 168 }; 169 170 mdio-mux-1 { 171 compatible = "mdio-mux-multiplexer"; 172 mux-controls = <&mdio_mux>; 173 mdio-parent-bus = <&cpsw3g_mdio>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 mdio@1 { 178 reg = <0x1>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 cpsw3g_phy3: ethernet-phy@3 { 183 reg = <3>; 184 }; 185 }; 186 }; 187 188 transceiver1: can-phy0 { 189 compatible = "ti,tcan1042"; 190 #phy-cells = <0>; 191 max-bitrate = <5000000>; 192 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; 193 }; 194 195 transceiver2: can-phy1 { 196 compatible = "ti,tcan1042"; 197 #phy-cells = <0>; 198 max-bitrate = <5000000>; 199 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; 200 }; 201}; 202 203&main_pmx0 { 204 main_mmc1_pins_default: main-mmc1-pins-default { 205 pinctrl-single,pins = < 206 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 207 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 208 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 209 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 210 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 211 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 212 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 213 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ 214 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ 215 >; 216 }; 217 218 main_uart1_pins_default: main-uart1-pins-default { 219 pinctrl-single,pins = < 220 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ 221 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ 222 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ 223 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ 224 >; 225 }; 226 227 main_uart0_pins_default: main-uart0-pins-default { 228 pinctrl-single,pins = < 229 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 230 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 231 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 232 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 233 >; 234 }; 235 236 main_spi0_pins_default: main-spi0-pins-default { 237 pinctrl-single,pins = < 238 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ 239 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ 240 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ 241 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ 242 >; 243 }; 244 245 main_i2c0_pins_default: main-i2c0-pins-default { 246 pinctrl-single,pins = < 247 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ 248 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ 249 >; 250 }; 251 252 main_i2c1_pins_default: main-i2c1-pins-default { 253 pinctrl-single,pins = < 254 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 255 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 256 >; 257 }; 258 259 mdio1_pins_default: mdio1-pins-default { 260 pinctrl-single,pins = < 261 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 262 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 263 >; 264 }; 265 266 rgmii1_pins_default: rgmii1-pins-default { 267 pinctrl-single,pins = < 268 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 269 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 270 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 271 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 272 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 273 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 274 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 275 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 276 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 277 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 278 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 279 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 280 >; 281 }; 282 283 rgmii2_pins_default: rgmii2-pins-default { 284 pinctrl-single,pins = < 285 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 286 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 287 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 288 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 289 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 290 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 291 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 292 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 293 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 294 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 295 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 296 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 297 >; 298 }; 299 300 main_usb0_pins_default: main-usb0-pins-default { 301 pinctrl-single,pins = < 302 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 303 >; 304 }; 305 306 ospi0_pins_default: ospi0-pins-default { 307 pinctrl-single,pins = < 308 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 309 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 310 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 311 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 312 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 313 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 314 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 315 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 316 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 317 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 318 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 319 >; 320 }; 321 322 main_ecap0_pins_default: main-ecap0-pins-default { 323 pinctrl-single,pins = < 324 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 325 >; 326 }; 327 328 main_mcan0_pins_default: main-mcan0-pins-default { 329 pinctrl-single,pins = < 330 AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ 331 AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ 332 >; 333 }; 334 335 main_mcan1_pins_default: main-mcan1-pins-default { 336 pinctrl-single,pins = < 337 AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ 338 AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ 339 >; 340 }; 341}; 342 343&main_uart0 { 344 status = "okay"; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&main_uart0_pins_default>; 347}; 348 349/* main_uart1 is reserved for firmware usage */ 350&main_uart1 { 351 status = "reserved"; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&main_uart1_pins_default>; 354}; 355 356&main_i2c0 { 357 status = "okay"; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&main_i2c0_pins_default>; 360 clock-frequency = <400000>; 361 362 eeprom@50 { 363 /* AT24CM01 */ 364 compatible = "atmel,24c1024"; 365 reg = <0x50>; 366 }; 367}; 368 369&main_i2c1 { 370 status = "okay"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&main_i2c1_pins_default>; 373 clock-frequency = <400000>; 374 375 exp1: gpio@22 { 376 compatible = "ti,tca6424"; 377 reg = <0x22>; 378 gpio-controller; 379 #gpio-cells = <2>; 380 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", 381 "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", 382 "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", 383 "MMC1_SD_EN", "FSI_FET_SEL", 384 "MCAN0_STB_3V3", "MCAN1_STB_3V3", 385 "CPSW_FET_SEL", "CPSW_FET2_SEL", 386 "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", 387 "GPIO_OLED_RESETn", "VPP_LDO_EN", 388 "TEST_LED1", "TP92", "TP90", "TP88", 389 "TP87", "TP86", "TP89", "TP91"; 390 }; 391 392 /* osd9616p0899-10 */ 393 display@3c { 394 compatible = "solomon,ssd1306fb-i2c"; 395 reg = <0x3c>; 396 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; 397 vbat-supply = <&vddb>; 398 solomon,height = <16>; 399 solomon,width = <96>; 400 solomon,com-seq; 401 solomon,com-invdir; 402 solomon,page-offset = <0>; 403 solomon,prechargep1 = <2>; 404 solomon,prechargep2 = <13>; 405 }; 406}; 407 408/* mcu_gpio0 is reserved for mcu firmware usage */ 409&mcu_gpio0 { 410 status = "reserved"; 411}; 412 413&main_spi0 { 414 status = "okay"; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&main_spi0_pins_default>; 417 ti,pindir-d0-out-d1-in; 418 eeprom@0 { 419 compatible = "microchip,93lc46b"; 420 reg = <0>; 421 spi-max-frequency = <1000000>; 422 spi-cs-high; 423 data-size = <16>; 424 }; 425}; 426 427&sdhci0 { 428 /* emmc */ 429 bus-width = <8>; 430 non-removable; 431 ti,driver-strength-ohm = <50>; 432 disable-wp; 433}; 434 435&sdhci1 { 436 /* SD/MMC */ 437 vmmc-supply = <&vdd_mmc1>; 438 pinctrl-names = "default"; 439 bus-width = <4>; 440 pinctrl-0 = <&main_mmc1_pins_default>; 441 ti,driver-strength-ohm = <50>; 442 disable-wp; 443}; 444 445&usbss0 { 446 ti,vbus-divider; 447 ti,usb2-only; 448}; 449 450&usb0 { 451 dr_mode = "otg"; 452 maximum-speed = "high-speed"; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&main_usb0_pins_default>; 455}; 456 457&cpsw3g { 458 pinctrl-names = "default"; 459 pinctrl-0 = <&rgmii1_pins_default 460 &rgmii2_pins_default>; 461}; 462 463&cpsw_port1 { 464 phy-mode = "rgmii-rxid"; 465 phy-handle = <&cpsw3g_phy0>; 466}; 467 468&cpsw_port2 { 469 phy-mode = "rgmii-rxid"; 470 phy-handle = <&cpsw3g_phy3>; 471}; 472 473&cpsw3g_mdio { 474 status = "okay"; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&mdio1_pins_default>; 477 478 cpsw3g_phy0: ethernet-phy@0 { 479 reg = <0>; 480 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 481 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 482 }; 483}; 484 485&tscadc0 { 486 /* ADC is reserved for R5 usage */ 487 status = "reserved"; 488}; 489 490&ospi0 { 491 pinctrl-names = "default"; 492 pinctrl-0 = <&ospi0_pins_default>; 493 494 flash@0 { 495 compatible = "jedec,spi-nor"; 496 reg = <0x0>; 497 spi-tx-bus-width = <8>; 498 spi-rx-bus-width = <8>; 499 spi-max-frequency = <25000000>; 500 cdns,tshsl-ns = <60>; 501 cdns,tsd2d-ns = <60>; 502 cdns,tchsh-ns = <60>; 503 cdns,tslch-ns = <60>; 504 cdns,read-delay = <4>; 505 }; 506}; 507 508&mailbox0_cluster2 { 509 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 510 ti,mbox-rx = <0 0 2>; 511 ti,mbox-tx = <1 0 2>; 512 }; 513 514 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 515 ti,mbox-rx = <2 0 2>; 516 ti,mbox-tx = <3 0 2>; 517 }; 518}; 519 520&mailbox0_cluster3 { 521 status = "disabled"; 522}; 523 524&mailbox0_cluster4 { 525 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 526 ti,mbox-rx = <0 0 2>; 527 ti,mbox-tx = <1 0 2>; 528 }; 529 530 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 531 ti,mbox-rx = <2 0 2>; 532 ti,mbox-tx = <3 0 2>; 533 }; 534}; 535 536&mailbox0_cluster5 { 537 status = "disabled"; 538}; 539 540&mailbox0_cluster6 { 541 mbox_m4_0: mbox-m4-0 { 542 ti,mbox-rx = <0 0 2>; 543 ti,mbox-tx = <1 0 2>; 544 }; 545}; 546 547&mailbox0_cluster7 { 548 status = "disabled"; 549}; 550 551&main_r5fss0_core0 { 552 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 553 memory-region = <&main_r5fss0_core0_dma_memory_region>, 554 <&main_r5fss0_core0_memory_region>; 555}; 556 557&main_r5fss0_core1 { 558 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 559 memory-region = <&main_r5fss0_core1_dma_memory_region>, 560 <&main_r5fss0_core1_memory_region>; 561}; 562 563&main_r5fss1_core0 { 564 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 565 memory-region = <&main_r5fss1_core0_dma_memory_region>, 566 <&main_r5fss1_core0_memory_region>; 567}; 568 569&main_r5fss1_core1 { 570 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 571 memory-region = <&main_r5fss1_core1_dma_memory_region>, 572 <&main_r5fss1_core1_memory_region>; 573}; 574 575&serdes_ln_ctrl { 576 idle-states = <AM64_SERDES0_LANE0_PCIE0>; 577}; 578 579&serdes0 { 580 serdes0_pcie_link: phy@0 { 581 reg = <0>; 582 cdns,num-lanes = <1>; 583 #phy-cells = <0>; 584 cdns,phy-type = <PHY_TYPE_PCIE>; 585 resets = <&serdes_wiz0 1>; 586 }; 587}; 588 589&pcie0_rc { 590 status = "okay"; 591 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 592 phys = <&serdes0_pcie_link>; 593 phy-names = "pcie-phy"; 594 num-lanes = <1>; 595}; 596 597&pcie0_ep { 598 phys = <&serdes0_pcie_link>; 599 phy-names = "pcie-phy"; 600 num-lanes = <1>; 601}; 602 603&ecap0 { 604 status = "okay"; 605 /* PWM is available on Pin 1 of header J12 */ 606 pinctrl-names = "default"; 607 pinctrl-0 = <&main_ecap0_pins_default>; 608}; 609 610&main_mcan0 { 611 status = "okay"; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&main_mcan0_pins_default>; 614 phys = <&transceiver1>; 615}; 616 617&main_mcan1 { 618 status = "okay"; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&main_mcan1_pins_default>; 621 phys = <&transceiver2>; 622}; 623