1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/mux/ti-serdes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-am642.dtsi" 14 15/ { 16 compatible = "ti,am642-evm", "ti,am642"; 17 model = "Texas Instruments AM642 EVM"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 }; 22 23 aliases { 24 serial0 = &mcu_uart0; 25 serial1 = &main_uart1; 26 serial2 = &main_uart0; 27 serial3 = &main_uart3; 28 i2c0 = &main_i2c0; 29 i2c1 = &main_i2c1; 30 mmc0 = &sdhci0; 31 mmc1 = &sdhci1; 32 ethernet0 = &cpsw_port1; 33 ethernet1 = &cpsw_port2; 34 }; 35 36 memory@80000000 { 37 device_type = "memory"; 38 /* 2G RAM */ 39 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 40 }; 41 42 reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 secure_ddr: optee@9e800000 { 48 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 49 alignment = <0x1000>; 50 no-map; 51 }; 52 53 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 54 compatible = "shared-dma-pool"; 55 reg = <0x00 0xa0000000 0x00 0x100000>; 56 no-map; 57 }; 58 59 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0xa0100000 0x00 0xf00000>; 62 no-map; 63 }; 64 65 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0x00 0xa1000000 0x00 0x100000>; 68 no-map; 69 }; 70 71 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 72 compatible = "shared-dma-pool"; 73 reg = <0x00 0xa1100000 0x00 0xf00000>; 74 no-map; 75 }; 76 77 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 78 compatible = "shared-dma-pool"; 79 reg = <0x00 0xa2000000 0x00 0x100000>; 80 no-map; 81 }; 82 83 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 84 compatible = "shared-dma-pool"; 85 reg = <0x00 0xa2100000 0x00 0xf00000>; 86 no-map; 87 }; 88 89 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 90 compatible = "shared-dma-pool"; 91 reg = <0x00 0xa3000000 0x00 0x100000>; 92 no-map; 93 }; 94 95 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 96 compatible = "shared-dma-pool"; 97 reg = <0x00 0xa3100000 0x00 0xf00000>; 98 no-map; 99 }; 100 101 rtos_ipc_memory_region: ipc-memories@a5000000 { 102 reg = <0x00 0xa5000000 0x00 0x00800000>; 103 alignment = <0x1000>; 104 no-map; 105 }; 106 }; 107 108 evm_12v0: regulator-0 { 109 /* main DC jack */ 110 compatible = "regulator-fixed"; 111 regulator-name = "evm_12v0"; 112 regulator-min-microvolt = <12000000>; 113 regulator-max-microvolt = <12000000>; 114 regulator-always-on; 115 regulator-boot-on; 116 }; 117 118 vsys_5v0: regulator-1 { 119 /* output of LM5140 */ 120 compatible = "regulator-fixed"; 121 regulator-name = "vsys_5v0"; 122 regulator-min-microvolt = <5000000>; 123 regulator-max-microvolt = <5000000>; 124 vin-supply = <&evm_12v0>; 125 regulator-always-on; 126 regulator-boot-on; 127 }; 128 129 vsys_3v3: regulator-2 { 130 /* output of LM5140 */ 131 compatible = "regulator-fixed"; 132 regulator-name = "vsys_3v3"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 vin-supply = <&evm_12v0>; 136 regulator-always-on; 137 regulator-boot-on; 138 }; 139 140 vdd_mmc1: regulator-3 { 141 /* TPS2051BD */ 142 compatible = "regulator-fixed"; 143 regulator-name = "vdd_mmc1"; 144 regulator-min-microvolt = <3300000>; 145 regulator-max-microvolt = <3300000>; 146 regulator-boot-on; 147 enable-active-high; 148 vin-supply = <&vsys_3v3>; 149 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; 150 }; 151 152 vddb: regulator-4 { 153 compatible = "regulator-fixed"; 154 regulator-name = "vddb_3v3_display"; 155 regulator-min-microvolt = <3300000>; 156 regulator-max-microvolt = <3300000>; 157 vin-supply = <&vsys_3v3>; 158 regulator-always-on; 159 regulator-boot-on; 160 }; 161 162 vtt_supply: regulator-5 { 163 compatible = "regulator-fixed"; 164 regulator-name = "vtt"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&ddr_vtt_pins_default>; 167 regulator-min-microvolt = <3300000>; 168 regulator-max-microvolt = <3300000>; 169 gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; 170 vin-supply = <&vsys_3v3>; 171 enable-active-high; 172 regulator-always-on; 173 regulator-boot-on; 174 }; 175 176 leds { 177 compatible = "gpio-leds"; 178 179 led-0 { 180 label = "am64-evm:red:heartbeat"; 181 gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; 182 linux,default-trigger = "heartbeat"; 183 function = LED_FUNCTION_HEARTBEAT; 184 default-state = "off"; 185 }; 186 }; 187 188 mdio_mux: mux-controller { 189 compatible = "gpio-mux"; 190 #mux-control-cells = <0>; 191 192 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; 193 }; 194 195 mdio-mux-1 { 196 compatible = "mdio-mux-multiplexer"; 197 mux-controls = <&mdio_mux>; 198 mdio-parent-bus = <&cpsw3g_mdio>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 202 mdio@1 { 203 reg = <0x1>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 207 cpsw3g_phy3: ethernet-phy@3 { 208 reg = <3>; 209 }; 210 }; 211 }; 212 213 transceiver1: can-phy0 { 214 compatible = "ti,tcan1042"; 215 #phy-cells = <0>; 216 max-bitrate = <5000000>; 217 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; 218 }; 219 220 transceiver2: can-phy1 { 221 compatible = "ti,tcan1042"; 222 #phy-cells = <0>; 223 max-bitrate = <5000000>; 224 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; 225 }; 226}; 227 228&main_pmx0 { 229 main_mmc1_pins_default: main-mmc1-pins-default { 230 pinctrl-single,pins = < 231 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 232 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 233 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 234 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 235 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 236 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 237 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 238 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ 239 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ 240 >; 241 }; 242 243 main_uart1_pins_default: main-uart1-pins-default { 244 pinctrl-single,pins = < 245 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ 246 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ 247 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ 248 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ 249 >; 250 }; 251 252 main_uart0_pins_default: main-uart0-pins-default { 253 pinctrl-single,pins = < 254 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 255 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 256 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 257 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 258 >; 259 }; 260 261 main_spi0_pins_default: main-spi0-pins-default { 262 pinctrl-single,pins = < 263 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ 264 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ 265 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ 266 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ 267 >; 268 }; 269 270 main_i2c0_pins_default: main-i2c0-pins-default { 271 pinctrl-single,pins = < 272 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ 273 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ 274 >; 275 }; 276 277 main_i2c1_pins_default: main-i2c1-pins-default { 278 pinctrl-single,pins = < 279 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 280 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 281 >; 282 }; 283 284 mdio1_pins_default: mdio1-pins-default { 285 pinctrl-single,pins = < 286 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 287 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 288 >; 289 }; 290 291 rgmii1_pins_default: rgmii1-pins-default { 292 pinctrl-single,pins = < 293 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 294 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 295 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 296 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 297 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 298 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 299 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 300 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 301 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 302 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 303 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 304 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 305 >; 306 }; 307 308 rgmii2_pins_default: rgmii2-pins-default { 309 pinctrl-single,pins = < 310 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 311 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 312 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 313 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 314 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 315 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 316 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 317 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 318 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 319 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 320 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 321 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 322 >; 323 }; 324 325 main_usb0_pins_default: main-usb0-pins-default { 326 pinctrl-single,pins = < 327 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 328 >; 329 }; 330 331 ospi0_pins_default: ospi0-pins-default { 332 pinctrl-single,pins = < 333 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 334 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 335 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 336 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 337 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 338 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 339 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 340 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 341 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 342 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 343 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 344 >; 345 }; 346 347 main_ecap0_pins_default: main-ecap0-pins-default { 348 pinctrl-single,pins = < 349 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 350 >; 351 }; 352 353 main_mcan0_pins_default: main-mcan0-pins-default { 354 pinctrl-single,pins = < 355 AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ 356 AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ 357 >; 358 }; 359 360 main_mcan1_pins_default: main-mcan1-pins-default { 361 pinctrl-single,pins = < 362 AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ 363 AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ 364 >; 365 }; 366 367 ddr_vtt_pins_default: ddr-vtt-pins-default { 368 pinctrl-single,pins = < 369 AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ 370 >; 371 }; 372}; 373 374&main_uart0 { 375 status = "okay"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&main_uart0_pins_default>; 378}; 379 380/* main_uart1 is reserved for firmware usage */ 381&main_uart1 { 382 status = "reserved"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&main_uart1_pins_default>; 385}; 386 387&main_i2c0 { 388 status = "okay"; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&main_i2c0_pins_default>; 391 clock-frequency = <400000>; 392 393 eeprom@50 { 394 /* AT24CM01 */ 395 compatible = "atmel,24c1024"; 396 reg = <0x50>; 397 }; 398}; 399 400&main_i2c1 { 401 status = "okay"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&main_i2c1_pins_default>; 404 clock-frequency = <400000>; 405 406 exp1: gpio@22 { 407 compatible = "ti,tca6424"; 408 reg = <0x22>; 409 gpio-controller; 410 #gpio-cells = <2>; 411 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", 412 "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", 413 "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", 414 "MMC1_SD_EN", "FSI_FET_SEL", 415 "MCAN0_STB_3V3", "MCAN1_STB_3V3", 416 "CPSW_FET_SEL", "CPSW_FET2_SEL", 417 "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", 418 "GPIO_OLED_RESETn", "VPP_LDO_EN", 419 "TEST_LED1", "TP92", "TP90", "TP88", 420 "TP87", "TP86", "TP89", "TP91"; 421 }; 422 423 /* osd9616p0899-10 */ 424 display@3c { 425 compatible = "solomon,ssd1306fb-i2c"; 426 reg = <0x3c>; 427 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; 428 vbat-supply = <&vddb>; 429 solomon,height = <16>; 430 solomon,width = <96>; 431 solomon,com-seq; 432 solomon,com-invdir; 433 solomon,page-offset = <0>; 434 solomon,prechargep1 = <2>; 435 solomon,prechargep2 = <13>; 436 }; 437}; 438 439/* mcu_gpio0 is reserved for mcu firmware usage */ 440&mcu_gpio0 { 441 status = "reserved"; 442}; 443 444&main_spi0 { 445 status = "okay"; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&main_spi0_pins_default>; 448 ti,pindir-d0-out-d1-in; 449 eeprom@0 { 450 compatible = "microchip,93lc46b"; 451 reg = <0>; 452 spi-max-frequency = <1000000>; 453 spi-cs-high; 454 data-size = <16>; 455 }; 456}; 457 458&sdhci0 { 459 /* emmc */ 460 bus-width = <8>; 461 non-removable; 462 ti,driver-strength-ohm = <50>; 463 disable-wp; 464}; 465 466&sdhci1 { 467 /* SD/MMC */ 468 vmmc-supply = <&vdd_mmc1>; 469 pinctrl-names = "default"; 470 bus-width = <4>; 471 pinctrl-0 = <&main_mmc1_pins_default>; 472 ti,driver-strength-ohm = <50>; 473 disable-wp; 474}; 475 476&usbss0 { 477 ti,vbus-divider; 478 ti,usb2-only; 479}; 480 481&usb0 { 482 dr_mode = "otg"; 483 maximum-speed = "high-speed"; 484 pinctrl-names = "default"; 485 pinctrl-0 = <&main_usb0_pins_default>; 486}; 487 488&cpsw3g { 489 pinctrl-names = "default"; 490 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; 491}; 492 493&cpsw_port1 { 494 phy-mode = "rgmii-rxid"; 495 phy-handle = <&cpsw3g_phy0>; 496}; 497 498&cpsw_port2 { 499 phy-mode = "rgmii-rxid"; 500 phy-handle = <&cpsw3g_phy3>; 501}; 502 503&cpsw3g_mdio { 504 status = "okay"; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&mdio1_pins_default>; 507 508 cpsw3g_phy0: ethernet-phy@0 { 509 reg = <0>; 510 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 511 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 512 }; 513}; 514 515&tscadc0 { 516 /* ADC is reserved for R5 usage */ 517 status = "reserved"; 518}; 519 520&ospi0 { 521 pinctrl-names = "default"; 522 pinctrl-0 = <&ospi0_pins_default>; 523 524 flash@0 { 525 compatible = "jedec,spi-nor"; 526 reg = <0x0>; 527 spi-tx-bus-width = <8>; 528 spi-rx-bus-width = <8>; 529 spi-max-frequency = <25000000>; 530 cdns,tshsl-ns = <60>; 531 cdns,tsd2d-ns = <60>; 532 cdns,tchsh-ns = <60>; 533 cdns,tslch-ns = <60>; 534 cdns,read-delay = <4>; 535 536 partitions { 537 compatible = "fixed-partitions"; 538 #address-cells = <1>; 539 #size-cells = <1>; 540 541 partition@0 { 542 label = "ospi.tiboot3"; 543 reg = <0x0 0x100000>; 544 }; 545 546 partition@100000 { 547 label = "ospi.tispl"; 548 reg = <0x100000 0x200000>; 549 }; 550 551 partition@300000 { 552 label = "ospi.u-boot"; 553 reg = <0x300000 0x400000>; 554 }; 555 556 partition@700000 { 557 label = "ospi.env"; 558 reg = <0x700000 0x40000>; 559 }; 560 561 partition@740000 { 562 label = "ospi.env.backup"; 563 reg = <0x740000 0x40000>; 564 }; 565 566 partition@800000 { 567 label = "ospi.rootfs"; 568 reg = <0x800000 0x37c0000>; 569 }; 570 571 partition@3fc0000 { 572 label = "ospi.phypattern"; 573 reg = <0x3fc0000 0x40000>; 574 }; 575 }; 576 }; 577}; 578 579&mailbox0_cluster2 { 580 status = "okay"; 581 582 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 583 ti,mbox-rx = <0 0 2>; 584 ti,mbox-tx = <1 0 2>; 585 }; 586 587 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 588 ti,mbox-rx = <2 0 2>; 589 ti,mbox-tx = <3 0 2>; 590 }; 591}; 592 593&mailbox0_cluster4 { 594 status = "okay"; 595 596 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 597 ti,mbox-rx = <0 0 2>; 598 ti,mbox-tx = <1 0 2>; 599 }; 600 601 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 602 ti,mbox-rx = <2 0 2>; 603 ti,mbox-tx = <3 0 2>; 604 }; 605}; 606 607&mailbox0_cluster6 { 608 status = "okay"; 609 610 mbox_m4_0: mbox-m4-0 { 611 ti,mbox-rx = <0 0 2>; 612 ti,mbox-tx = <1 0 2>; 613 }; 614}; 615 616&main_r5fss0_core0 { 617 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; 618 memory-region = <&main_r5fss0_core0_dma_memory_region>, 619 <&main_r5fss0_core0_memory_region>; 620}; 621 622&main_r5fss0_core1 { 623 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; 624 memory-region = <&main_r5fss0_core1_dma_memory_region>, 625 <&main_r5fss0_core1_memory_region>; 626}; 627 628&main_r5fss1_core0 { 629 mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; 630 memory-region = <&main_r5fss1_core0_dma_memory_region>, 631 <&main_r5fss1_core0_memory_region>; 632}; 633 634&main_r5fss1_core1 { 635 mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; 636 memory-region = <&main_r5fss1_core1_dma_memory_region>, 637 <&main_r5fss1_core1_memory_region>; 638}; 639 640&serdes_ln_ctrl { 641 idle-states = <AM64_SERDES0_LANE0_PCIE0>; 642}; 643 644&serdes0 { 645 serdes0_pcie_link: phy@0 { 646 reg = <0>; 647 cdns,num-lanes = <1>; 648 #phy-cells = <0>; 649 cdns,phy-type = <PHY_TYPE_PCIE>; 650 resets = <&serdes_wiz0 1>; 651 }; 652}; 653 654&pcie0_rc { 655 status = "okay"; 656 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 657 phys = <&serdes0_pcie_link>; 658 phy-names = "pcie-phy"; 659 num-lanes = <1>; 660}; 661 662&pcie0_ep { 663 phys = <&serdes0_pcie_link>; 664 phy-names = "pcie-phy"; 665 num-lanes = <1>; 666}; 667 668&ecap0 { 669 status = "okay"; 670 /* PWM is available on Pin 1 of header J12 */ 671 pinctrl-names = "default"; 672 pinctrl-0 = <&main_ecap0_pins_default>; 673}; 674 675&main_mcan0 { 676 status = "okay"; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&main_mcan0_pins_default>; 679 phys = <&transceiver1>; 680}; 681 682&main_mcan1 { 683 status = "okay"; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&main_mcan1_pins_default>; 686 phys = <&transceiver2>; 687}; 688