1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu-map { 22 cluster0 { 23 core0 { 24 cpu = <&a55_0>; 25 }; 26 core1 { 27 cpu = <&a55_1>; 28 }; 29 }; 30 31 cluster1 { 32 core0 { 33 cpu = <&a55_2>; 34 }; 35 core1 { 36 cpu = <&a55_3>; 37 }; 38 }; 39 40 cluster2 { 41 core0 { 42 cpu = <&a55_4>; 43 }; 44 core1 { 45 cpu = <&a55_5>; 46 }; 47 }; 48 49 cluster3 { 50 core0 { 51 cpu = <&a55_6>; 52 }; 53 core1 { 54 cpu = <&a55_7>; 55 }; 56 }; 57 }; 58 59 a55_0: cpu@0 { 60 compatible = "arm,cortex-a55"; 61 reg = <0>; 62 device_type = "cpu"; 63 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 64 next-level-cache = <&L3_CA55_0>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 68 }; 69 70 a55_1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; 75 next-level-cache = <&L3_CA55_0>; 76 enable-method = "psci"; 77 cpu-idle-states = <&CPU_SLEEP_0>; 78 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 79 }; 80 81 a55_2: cpu@10000 { 82 compatible = "arm,cortex-a55"; 83 reg = <0x10000>; 84 device_type = "cpu"; 85 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; 86 next-level-cache = <&L3_CA55_1>; 87 enable-method = "psci"; 88 cpu-idle-states = <&CPU_SLEEP_0>; 89 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 90 }; 91 92 a55_3: cpu@10100 { 93 compatible = "arm,cortex-a55"; 94 reg = <0x10100>; 95 device_type = "cpu"; 96 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; 97 next-level-cache = <&L3_CA55_1>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 101 }; 102 103 a55_4: cpu@20000 { 104 compatible = "arm,cortex-a55"; 105 reg = <0x20000>; 106 device_type = "cpu"; 107 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; 108 next-level-cache = <&L3_CA55_2>; 109 enable-method = "psci"; 110 cpu-idle-states = <&CPU_SLEEP_0>; 111 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 112 }; 113 114 a55_5: cpu@20100 { 115 compatible = "arm,cortex-a55"; 116 reg = <0x20100>; 117 device_type = "cpu"; 118 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; 119 next-level-cache = <&L3_CA55_2>; 120 enable-method = "psci"; 121 cpu-idle-states = <&CPU_SLEEP_0>; 122 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 123 }; 124 125 a55_6: cpu@30000 { 126 compatible = "arm,cortex-a55"; 127 reg = <0x30000>; 128 device_type = "cpu"; 129 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; 130 next-level-cache = <&L3_CA55_3>; 131 enable-method = "psci"; 132 cpu-idle-states = <&CPU_SLEEP_0>; 133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 134 }; 135 136 a55_7: cpu@30100 { 137 compatible = "arm,cortex-a55"; 138 reg = <0x30100>; 139 device_type = "cpu"; 140 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; 141 next-level-cache = <&L3_CA55_3>; 142 enable-method = "psci"; 143 cpu-idle-states = <&CPU_SLEEP_0>; 144 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 145 }; 146 147 L3_CA55_0: cache-controller-0 { 148 compatible = "cache"; 149 power-domains = <&sysc R8A779F0_PD_A2E0D0>; 150 cache-unified; 151 cache-level = <3>; 152 }; 153 154 L3_CA55_1: cache-controller-1 { 155 compatible = "cache"; 156 power-domains = <&sysc R8A779F0_PD_A2E0D1>; 157 cache-unified; 158 cache-level = <3>; 159 }; 160 161 L3_CA55_2: cache-controller-2 { 162 compatible = "cache"; 163 power-domains = <&sysc R8A779F0_PD_A2E1D0>; 164 cache-unified; 165 cache-level = <3>; 166 }; 167 168 L3_CA55_3: cache-controller-3 { 169 compatible = "cache"; 170 power-domains = <&sysc R8A779F0_PD_A2E1D1>; 171 cache-unified; 172 cache-level = <3>; 173 }; 174 175 idle-states { 176 entry-method = "psci"; 177 178 CPU_SLEEP_0: cpu-sleep-0 { 179 compatible = "arm,idle-state"; 180 arm,psci-suspend-param = <0x0010000>; 181 local-timer-stop; 182 entry-latency-us = <400>; 183 exit-latency-us = <500>; 184 min-residency-us = <4000>; 185 }; 186 }; 187 }; 188 189 extal_clk: extal { 190 compatible = "fixed-clock"; 191 #clock-cells = <0>; 192 /* This value must be overridden by the board */ 193 clock-frequency = <0>; 194 }; 195 196 extalr_clk: extalr { 197 compatible = "fixed-clock"; 198 #clock-cells = <0>; 199 /* This value must be overridden by the board */ 200 clock-frequency = <0>; 201 }; 202 203 pmu_a55 { 204 compatible = "arm,cortex-a55-pmu"; 205 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 206 }; 207 208 psci { 209 compatible = "arm,psci-1.0", "arm,psci-0.2"; 210 method = "smc"; 211 }; 212 213 /* External SCIF clock - to be overridden by boards that provide it */ 214 scif_clk: scif { 215 compatible = "fixed-clock"; 216 #clock-cells = <0>; 217 clock-frequency = <0>; 218 }; 219 220 soc: soc { 221 compatible = "simple-bus"; 222 interrupt-parent = <&gic>; 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges; 226 227 rwdt: watchdog@e6020000 { 228 compatible = "renesas,r8a779f0-wdt", 229 "renesas,rcar-gen4-wdt"; 230 reg = <0 0xe6020000 0 0x0c>; 231 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cpg CPG_MOD 907>; 233 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 234 resets = <&cpg 907>; 235 status = "disabled"; 236 }; 237 238 pfc: pinctrl@e6050000 { 239 compatible = "renesas,pfc-r8a779f0"; 240 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 241 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 242 }; 243 244 gpio0: gpio@e6050180 { 245 compatible = "renesas,gpio-r8a779f0", 246 "renesas,rcar-gen4-gpio"; 247 reg = <0 0xe6050180 0 0x54>; 248 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cpg CPG_MOD 915>; 250 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 251 resets = <&cpg 915>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 gpio-ranges = <&pfc 0 0 21>; 255 interrupt-controller; 256 #interrupt-cells = <2>; 257 }; 258 259 gpio1: gpio@e6050980 { 260 compatible = "renesas,gpio-r8a779f0", 261 "renesas,rcar-gen4-gpio"; 262 reg = <0 0xe6050980 0 0x54>; 263 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&cpg CPG_MOD 915>; 265 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 266 resets = <&cpg 915>; 267 gpio-controller; 268 #gpio-cells = <2>; 269 gpio-ranges = <&pfc 0 32 25>; 270 interrupt-controller; 271 #interrupt-cells = <2>; 272 }; 273 274 gpio2: gpio@e6051180 { 275 compatible = "renesas,gpio-r8a779f0", 276 "renesas,rcar-gen4-gpio"; 277 reg = <0 0xe6051180 0 0x54>; 278 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cpg CPG_MOD 915>; 280 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 281 resets = <&cpg 915>; 282 gpio-controller; 283 #gpio-cells = <2>; 284 gpio-ranges = <&pfc 0 64 17>; 285 interrupt-controller; 286 #interrupt-cells = <2>; 287 }; 288 289 gpio3: gpio@e6051980 { 290 compatible = "renesas,gpio-r8a779f0", 291 "renesas,rcar-gen4-gpio"; 292 reg = <0 0xe6051980 0 0x54>; 293 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&cpg CPG_MOD 915>; 295 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 296 resets = <&cpg 915>; 297 gpio-controller; 298 #gpio-cells = <2>; 299 gpio-ranges = <&pfc 0 96 19>; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 }; 303 304 cpg: clock-controller@e6150000 { 305 compatible = "renesas,r8a779f0-cpg-mssr"; 306 reg = <0 0xe6150000 0 0x4000>; 307 clocks = <&extal_clk>, <&extalr_clk>; 308 clock-names = "extal", "extalr"; 309 #clock-cells = <2>; 310 #power-domain-cells = <0>; 311 #reset-cells = <1>; 312 }; 313 314 rst: reset-controller@e6160000 { 315 compatible = "renesas,r8a779f0-rst"; 316 reg = <0 0xe6160000 0 0x4000>; 317 }; 318 319 sysc: system-controller@e6180000 { 320 compatible = "renesas,r8a779f0-sysc"; 321 reg = <0 0xe6180000 0 0x4000>; 322 #power-domain-cells = <1>; 323 }; 324 325 tsc: thermal@e6198000 { 326 compatible = "renesas,r8a779f0-thermal"; 327 /* The 4th sensor is in control domain and not for Linux */ 328 reg = <0 0xe6198000 0 0x200>, 329 <0 0xe61a0000 0 0x200>, 330 <0 0xe61a8000 0 0x200>; 331 clocks = <&cpg CPG_MOD 919>; 332 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 333 resets = <&cpg 919>; 334 #thermal-sensor-cells = <1>; 335 }; 336 337 i2c0: i2c@e6500000 { 338 compatible = "renesas,i2c-r8a779f0", 339 "renesas,rcar-gen4-i2c"; 340 reg = <0 0xe6500000 0 0x40>; 341 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&cpg CPG_MOD 518>; 343 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 344 resets = <&cpg 518>; 345 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 346 <&dmac1 0x91>, <&dmac1 0x90>; 347 dma-names = "tx", "rx", "tx", "rx"; 348 i2c-scl-internal-delay-ns = <110>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 status = "disabled"; 352 }; 353 354 i2c1: i2c@e6508000 { 355 compatible = "renesas,i2c-r8a779f0", 356 "renesas,rcar-gen4-i2c"; 357 reg = <0 0xe6508000 0 0x40>; 358 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&cpg CPG_MOD 519>; 360 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 361 resets = <&cpg 519>; 362 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 363 <&dmac1 0x93>, <&dmac1 0x92>; 364 dma-names = "tx", "rx", "tx", "rx"; 365 i2c-scl-internal-delay-ns = <110>; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 status = "disabled"; 369 }; 370 371 i2c2: i2c@e6510000 { 372 compatible = "renesas,i2c-r8a779f0", 373 "renesas,rcar-gen4-i2c"; 374 reg = <0 0xe6510000 0 0x40>; 375 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&cpg CPG_MOD 520>; 377 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 378 resets = <&cpg 520>; 379 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 380 <&dmac1 0x95>, <&dmac1 0x94>; 381 dma-names = "tx", "rx", "tx", "rx"; 382 i2c-scl-internal-delay-ns = <110>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 status = "disabled"; 386 }; 387 388 i2c3: i2c@e66d0000 { 389 compatible = "renesas,i2c-r8a779f0", 390 "renesas,rcar-gen4-i2c"; 391 reg = <0 0xe66d0000 0 0x40>; 392 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cpg CPG_MOD 521>; 394 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 395 resets = <&cpg 521>; 396 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 397 <&dmac1 0x97>, <&dmac1 0x96>; 398 dma-names = "tx", "rx", "tx", "rx"; 399 i2c-scl-internal-delay-ns = <110>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 i2c4: i2c@e66d8000 { 406 compatible = "renesas,i2c-r8a779f0", 407 "renesas,rcar-gen4-i2c"; 408 reg = <0 0xe66d8000 0 0x40>; 409 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&cpg CPG_MOD 522>; 411 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 412 resets = <&cpg 522>; 413 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 414 <&dmac1 0x99>, <&dmac1 0x98>; 415 dma-names = "tx", "rx", "tx", "rx"; 416 i2c-scl-internal-delay-ns = <110>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 status = "disabled"; 420 }; 421 422 i2c5: i2c@e66e0000 { 423 compatible = "renesas,i2c-r8a779f0", 424 "renesas,rcar-gen4-i2c"; 425 reg = <0 0xe66e0000 0 0x40>; 426 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&cpg CPG_MOD 523>; 428 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 429 resets = <&cpg 523>; 430 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 431 <&dmac1 0x9b>, <&dmac1 0x9a>; 432 dma-names = "tx", "rx", "tx", "rx"; 433 i2c-scl-internal-delay-ns = <110>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 status = "disabled"; 437 }; 438 439 ufs: ufs@e6860000 { 440 compatible = "renesas,r8a779f0-ufs"; 441 reg = <0 0xe6860000 0 0x100>; 442 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; 444 clock-names = "fck", "ref_clk"; 445 freq-table-hz = <200000000 200000000>, <38400000 38400000>; 446 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 447 resets = <&cpg 1514>; 448 status = "disabled"; 449 }; 450 451 scif3: serial@e6c50000 { 452 compatible = "renesas,scif-r8a779f0", 453 "renesas,rcar-gen4-scif", "renesas,scif"; 454 reg = <0 0xe6c50000 0 64>; 455 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cpg CPG_MOD 704>, 457 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 458 <&scif_clk>; 459 clock-names = "fck", "brg_int", "scif_clk"; 460 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 461 resets = <&cpg 704>; 462 status = "disabled"; 463 }; 464 465 dmac0: dma-controller@e7350000 { 466 compatible = "renesas,dmac-r8a779f0", 467 "renesas,rcar-gen4-dmac"; 468 reg = <0 0xe7350000 0 0x1000>, 469 <0 0xe7300000 0 0x10000>; 470 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "error", 488 "ch0", "ch1", "ch2", "ch3", "ch4", 489 "ch5", "ch6", "ch7", "ch8", "ch9", 490 "ch10", "ch11", "ch12", "ch13", 491 "ch14", "ch15"; 492 clocks = <&cpg CPG_MOD 709>; 493 clock-names = "fck"; 494 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 495 resets = <&cpg 709>; 496 #dma-cells = <1>; 497 dma-channels = <16>; 498 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 499 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 500 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 501 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 502 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 503 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 504 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 505 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 506 }; 507 508 dmac1: dma-controller@e7351000 { 509 compatible = "renesas,dmac-r8a779f0", 510 "renesas,rcar-gen4-dmac"; 511 reg = <0 0xe7351000 0 0x1000>, 512 <0 0xe7310000 0 0x10000>; 513 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 530 interrupt-names = "error", 531 "ch0", "ch1", "ch2", "ch3", "ch4", 532 "ch5", "ch6", "ch7", "ch8", "ch9", 533 "ch10", "ch11", "ch12", "ch13", 534 "ch14", "ch15"; 535 clocks = <&cpg CPG_MOD 710>; 536 clock-names = "fck"; 537 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 538 resets = <&cpg 710>; 539 #dma-cells = <1>; 540 dma-channels = <16>; 541 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, 542 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, 543 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, 544 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, 545 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, 546 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, 547 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, 548 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; 549 }; 550 551 ipmmu_rt0: iommu@ee480000 { 552 compatible = "renesas,ipmmu-r8a779f0", 553 "renesas,rcar-gen4-ipmmu-vmsa"; 554 reg = <0 0xee480000 0 0x20000>; 555 renesas,ipmmu-main = <&ipmmu_mm 10>; 556 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 557 #iommu-cells = <1>; 558 }; 559 560 ipmmu_rt1: iommu@ee4c0000 { 561 compatible = "renesas,ipmmu-r8a779f0", 562 "renesas,rcar-gen4-ipmmu-vmsa"; 563 reg = <0 0xee4c0000 0 0x20000>; 564 renesas,ipmmu-main = <&ipmmu_mm 19>; 565 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 566 #iommu-cells = <1>; 567 }; 568 569 ipmmu_ds0: iommu@eed00000 { 570 compatible = "renesas,ipmmu-r8a779f0", 571 "renesas,rcar-gen4-ipmmu-vmsa"; 572 reg = <0 0xeed00000 0 0x20000>; 573 renesas,ipmmu-main = <&ipmmu_mm 0>; 574 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 575 #iommu-cells = <1>; 576 }; 577 578 ipmmu_hc: iommu@eed40000 { 579 compatible = "renesas,ipmmu-r8a779f0", 580 "renesas,rcar-gen4-ipmmu-vmsa"; 581 reg = <0 0xeed40000 0 0x20000>; 582 renesas,ipmmu-main = <&ipmmu_mm 2>; 583 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 584 #iommu-cells = <1>; 585 }; 586 587 ipmmu_mm: iommu@eefc0000 { 588 compatible = "renesas,ipmmu-r8a779f0", 589 "renesas,rcar-gen4-ipmmu-vmsa"; 590 reg = <0 0xeefc0000 0 0x20000>; 591 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 593 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 594 #iommu-cells = <1>; 595 }; 596 597 gic: interrupt-controller@f1000000 { 598 compatible = "arm,gic-v3"; 599 #interrupt-cells = <3>; 600 #address-cells = <0>; 601 interrupt-controller; 602 reg = <0x0 0xf1000000 0 0x20000>, 603 <0x0 0xf1060000 0 0x110000>; 604 interrupts = <GIC_PPI 9 605 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 606 }; 607 608 prr: chipid@fff00044 { 609 compatible = "renesas,prr"; 610 reg = <0 0xfff00044 0 4>; 611 }; 612 }; 613 614 thermal-zones { 615 sensor_thermal1: sensor1-thermal { 616 polling-delay-passive = <250>; 617 polling-delay = <1000>; 618 thermal-sensors = <&tsc 0>; 619 620 trips { 621 sensor1_crit: sensor1-crit { 622 temperature = <120000>; 623 hysteresis = <1000>; 624 type = "critical"; 625 }; 626 }; 627 }; 628 629 sensor_thermal2: sensor2-thermal { 630 polling-delay-passive = <250>; 631 polling-delay = <1000>; 632 thermal-sensors = <&tsc 1>; 633 634 trips { 635 sensor2_crit: sensor2-crit { 636 temperature = <120000>; 637 hysteresis = <1000>; 638 type = "critical"; 639 }; 640 }; 641 }; 642 643 sensor_thermal3: sensor3-thermal { 644 polling-delay-passive = <250>; 645 polling-delay = <1000>; 646 thermal-sensors = <&tsc 2>; 647 648 trips { 649 sensor3_crit: sensor3-crit { 650 temperature = <120000>; 651 hysteresis = <1000>; 652 type = "critical"; 653 }; 654 }; 655 }; 656 }; 657 658 timer { 659 compatible = "arm,armv8-timer"; 660 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 661 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 662 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 663 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 664 }; 665 666 ufs30_clk: ufs30-clk { 667 compatible = "fixed-clock"; 668 #clock-cells = <0>; 669 /* This value must be overridden by the board */ 670 clock-frequency = <0>; 671 }; 672}; 673