1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 a55_0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 26 }; 27 }; 28 29 extal_clk: extal { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 /* This value must be overridden by the board */ 33 clock-frequency = <0>; 34 }; 35 36 extalr_clk: extalr { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 /* This value must be overridden by the board */ 40 clock-frequency = <0>; 41 }; 42 43 pmu_a55 { 44 compatible = "arm,cortex-a55-pmu"; 45 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 46 }; 47 48 /* External SCIF clock - to be overridden by boards that provide it */ 49 scif_clk: scif { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <0>; 53 }; 54 55 soc: soc { 56 compatible = "simple-bus"; 57 interrupt-parent = <&gic>; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 62 rwdt: watchdog@e6020000 { 63 compatible = "renesas,r8a779f0-wdt", 64 "renesas,rcar-gen4-wdt"; 65 reg = <0 0xe6020000 0 0x0c>; 66 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&cpg CPG_MOD 907>; 68 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 69 resets = <&cpg 907>; 70 status = "disabled"; 71 }; 72 73 pfc: pinctrl@e6050000 { 74 compatible = "renesas,pfc-r8a779f0"; 75 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 76 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 77 }; 78 79 gpio0: gpio@e6050180 { 80 compatible = "renesas,gpio-r8a779f0", 81 "renesas,rcar-gen4-gpio"; 82 reg = <0 0xe6050180 0 0x54>; 83 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 84 clocks = <&cpg CPG_MOD 915>; 85 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 86 resets = <&cpg 915>; 87 gpio-controller; 88 #gpio-cells = <2>; 89 gpio-ranges = <&pfc 0 0 21>; 90 interrupt-controller; 91 #interrupt-cells = <2>; 92 }; 93 94 gpio1: gpio@e6050980 { 95 compatible = "renesas,gpio-r8a779f0", 96 "renesas,rcar-gen4-gpio"; 97 reg = <0 0xe6050980 0 0x54>; 98 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&cpg CPG_MOD 915>; 100 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 101 resets = <&cpg 915>; 102 gpio-controller; 103 #gpio-cells = <2>; 104 gpio-ranges = <&pfc 0 32 25>; 105 interrupt-controller; 106 #interrupt-cells = <2>; 107 }; 108 109 gpio2: gpio@e6051180 { 110 compatible = "renesas,gpio-r8a779f0", 111 "renesas,rcar-gen4-gpio"; 112 reg = <0 0xe6051180 0 0x54>; 113 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&cpg CPG_MOD 915>; 115 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 116 resets = <&cpg 915>; 117 gpio-controller; 118 #gpio-cells = <2>; 119 gpio-ranges = <&pfc 0 64 17>; 120 interrupt-controller; 121 #interrupt-cells = <2>; 122 }; 123 124 gpio3: gpio@e6051980 { 125 compatible = "renesas,gpio-r8a779f0", 126 "renesas,rcar-gen4-gpio"; 127 reg = <0 0xe6051980 0 0x54>; 128 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&cpg CPG_MOD 915>; 130 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 131 resets = <&cpg 915>; 132 gpio-controller; 133 #gpio-cells = <2>; 134 gpio-ranges = <&pfc 0 96 19>; 135 interrupt-controller; 136 #interrupt-cells = <2>; 137 }; 138 139 cpg: clock-controller@e6150000 { 140 compatible = "renesas,r8a779f0-cpg-mssr"; 141 reg = <0 0xe6150000 0 0x4000>; 142 clocks = <&extal_clk>, <&extalr_clk>; 143 clock-names = "extal", "extalr"; 144 #clock-cells = <2>; 145 #power-domain-cells = <0>; 146 #reset-cells = <1>; 147 }; 148 149 rst: reset-controller@e6160000 { 150 compatible = "renesas,r8a779f0-rst"; 151 reg = <0 0xe6160000 0 0x4000>; 152 }; 153 154 sysc: system-controller@e6180000 { 155 compatible = "renesas,r8a779f0-sysc"; 156 reg = <0 0xe6180000 0 0x4000>; 157 #power-domain-cells = <1>; 158 }; 159 160 tsc: thermal@e6198000 { 161 compatible = "renesas,r8a779f0-thermal"; 162 /* The 4th sensor is in control domain and not for Linux */ 163 reg = <0 0xe6198000 0 0x200>, 164 <0 0xe61a0000 0 0x200>, 165 <0 0xe61a8000 0 0x200>; 166 clocks = <&cpg CPG_MOD 919>; 167 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 168 resets = <&cpg 919>; 169 #thermal-sensor-cells = <1>; 170 }; 171 172 i2c0: i2c@e6500000 { 173 compatible = "renesas,i2c-r8a779f0", 174 "renesas,rcar-gen4-i2c"; 175 reg = <0 0xe6500000 0 0x40>; 176 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&cpg CPG_MOD 518>; 178 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 179 resets = <&cpg 518>; 180 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 181 <&dmac1 0x91>, <&dmac1 0x90>; 182 dma-names = "tx", "rx", "tx", "rx"; 183 i2c-scl-internal-delay-ns = <110>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 status = "disabled"; 187 }; 188 189 i2c1: i2c@e6508000 { 190 compatible = "renesas,i2c-r8a779f0", 191 "renesas,rcar-gen4-i2c"; 192 reg = <0 0xe6508000 0 0x40>; 193 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&cpg CPG_MOD 519>; 195 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 196 resets = <&cpg 519>; 197 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 198 <&dmac1 0x93>, <&dmac1 0x92>; 199 dma-names = "tx", "rx", "tx", "rx"; 200 i2c-scl-internal-delay-ns = <110>; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 status = "disabled"; 204 }; 205 206 i2c2: i2c@e6510000 { 207 compatible = "renesas,i2c-r8a779f0", 208 "renesas,rcar-gen4-i2c"; 209 reg = <0 0xe6510000 0 0x40>; 210 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&cpg CPG_MOD 520>; 212 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 213 resets = <&cpg 520>; 214 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 215 <&dmac1 0x95>, <&dmac1 0x94>; 216 dma-names = "tx", "rx", "tx", "rx"; 217 i2c-scl-internal-delay-ns = <110>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2c3: i2c@e66d0000 { 224 compatible = "renesas,i2c-r8a779f0", 225 "renesas,rcar-gen4-i2c"; 226 reg = <0 0xe66d0000 0 0x40>; 227 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cpg CPG_MOD 521>; 229 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 230 resets = <&cpg 521>; 231 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 232 <&dmac1 0x97>, <&dmac1 0x96>; 233 dma-names = "tx", "rx", "tx", "rx"; 234 i2c-scl-internal-delay-ns = <110>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 status = "disabled"; 238 }; 239 240 i2c4: i2c@e66d8000 { 241 compatible = "renesas,i2c-r8a779f0", 242 "renesas,rcar-gen4-i2c"; 243 reg = <0 0xe66d8000 0 0x40>; 244 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&cpg CPG_MOD 522>; 246 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 247 resets = <&cpg 522>; 248 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 249 <&dmac1 0x99>, <&dmac1 0x98>; 250 dma-names = "tx", "rx", "tx", "rx"; 251 i2c-scl-internal-delay-ns = <110>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 status = "disabled"; 255 }; 256 257 i2c5: i2c@e66e0000 { 258 compatible = "renesas,i2c-r8a779f0", 259 "renesas,rcar-gen4-i2c"; 260 reg = <0 0xe66e0000 0 0x40>; 261 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&cpg CPG_MOD 523>; 263 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 264 resets = <&cpg 523>; 265 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 266 <&dmac1 0x9b>, <&dmac1 0x9a>; 267 dma-names = "tx", "rx", "tx", "rx"; 268 i2c-scl-internal-delay-ns = <110>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 status = "disabled"; 272 }; 273 274 scif3: serial@e6c50000 { 275 compatible = "renesas,scif-r8a779f0", 276 "renesas,rcar-gen4-scif", "renesas,scif"; 277 reg = <0 0xe6c50000 0 64>; 278 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cpg CPG_MOD 704>, 280 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 281 <&scif_clk>; 282 clock-names = "fck", "brg_int", "scif_clk"; 283 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 284 resets = <&cpg 704>; 285 status = "disabled"; 286 }; 287 288 dmac0: dma-controller@e7350000 { 289 compatible = "renesas,dmac-r8a779f0", 290 "renesas,rcar-gen4-dmac"; 291 reg = <0 0xe7350000 0 0x1000>, 292 <0 0xe7300000 0 0x10000>; 293 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "error", 311 "ch0", "ch1", "ch2", "ch3", "ch4", 312 "ch5", "ch6", "ch7", "ch8", "ch9", 313 "ch10", "ch11", "ch12", "ch13", 314 "ch14", "ch15"; 315 clocks = <&cpg CPG_MOD 709>; 316 clock-names = "fck"; 317 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 318 resets = <&cpg 709>; 319 #dma-cells = <1>; 320 dma-channels = <16>; 321 }; 322 323 dmac1: dma-controller@e7351000 { 324 compatible = "renesas,dmac-r8a779f0", 325 "renesas,rcar-gen4-dmac"; 326 reg = <0 0xe7351000 0 0x1000>, 327 <0 0xe7310000 0 0x10000>; 328 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 345 interrupt-names = "error", 346 "ch0", "ch1", "ch2", "ch3", "ch4", 347 "ch5", "ch6", "ch7", "ch8", "ch9", 348 "ch10", "ch11", "ch12", "ch13", 349 "ch14", "ch15"; 350 clocks = <&cpg CPG_MOD 710>; 351 clock-names = "fck"; 352 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 353 resets = <&cpg 710>; 354 #dma-cells = <1>; 355 dma-channels = <16>; 356 }; 357 358 gic: interrupt-controller@f1000000 { 359 compatible = "arm,gic-v3"; 360 #interrupt-cells = <3>; 361 #address-cells = <0>; 362 interrupt-controller; 363 reg = <0x0 0xf1000000 0 0x20000>, 364 <0x0 0xf1060000 0 0x110000>; 365 interrupts = <GIC_PPI 9 366 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 367 }; 368 369 prr: chipid@fff00044 { 370 compatible = "renesas,prr"; 371 reg = <0 0xfff00044 0 4>; 372 }; 373 }; 374 375 thermal-zones { 376 sensor_thermal1: sensor1-thermal { 377 polling-delay-passive = <250>; 378 polling-delay = <1000>; 379 thermal-sensors = <&tsc 0>; 380 381 trips { 382 sensor1_crit: sensor1-crit { 383 temperature = <120000>; 384 hysteresis = <1000>; 385 type = "critical"; 386 }; 387 }; 388 }; 389 390 sensor_thermal2: sensor2-thermal { 391 polling-delay-passive = <250>; 392 polling-delay = <1000>; 393 thermal-sensors = <&tsc 1>; 394 395 trips { 396 sensor2_crit: sensor2-crit { 397 temperature = <120000>; 398 hysteresis = <1000>; 399 type = "critical"; 400 }; 401 }; 402 }; 403 404 sensor_thermal3: sensor3-thermal { 405 polling-delay-passive = <250>; 406 polling-delay = <1000>; 407 thermal-sensors = <&tsc 2>; 408 409 trips { 410 sensor3_crit: sensor3-crit { 411 temperature = <120000>; 412 hysteresis = <1000>; 413 type = "critical"; 414 }; 415 }; 416 }; 417 }; 418 419 timer { 420 compatible = "arm,armv8-timer"; 421 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 422 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 423 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 424 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 425 }; 426}; 427