1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/microchip,sparx5.h> 9 10/ { 11 compatible = "microchip,sparx5"; 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <1>; 15 16 aliases { 17 serial0 = &uart0; 18 serial1 = &uart1; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 cpus { 26 #address-cells = <2>; 27 #size-cells = <0>; 28 cpu-map { 29 cluster0 { 30 core0 { 31 cpu = <&cpu0>; 32 }; 33 core1 { 34 cpu = <&cpu1>; 35 }; 36 }; 37 }; 38 cpu0: cpu@0 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 next-level-cache = <&L2_0>; 44 }; 45 cpu1: cpu@1 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 reg = <0x0 0x1>; 49 enable-method = "psci"; 50 next-level-cache = <&L2_0>; 51 }; 52 L2_0: l2-cache0 { 53 compatible = "cache"; 54 }; 55 }; 56 57 arm-pmu { 58 compatible = "arm,cortex-a53-pmu"; 59 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>; 61 }; 62 63 psci { 64 compatible = "arm,psci-0.2"; 65 method = "smc"; 66 }; 67 68 timer { 69 compatible = "arm,armv8-timer"; 70 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 71 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 72 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 73 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 74 }; 75 76 lcpll_clk: lcpll-clk { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <2500000000>; 80 }; 81 82 clks: clock-controller@61110000c { 83 compatible = "microchip,sparx5-dpll"; 84 #clock-cells = <1>; 85 clocks = <&lcpll_clk>; 86 reg = <0x6 0x1110000c 0x24>; 87 }; 88 89 ahb_clk: ahb-clk { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <250000000>; 93 }; 94 95 sys_clk: sys-clk { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <625000000>; 99 }; 100 101 axi: axi@600000000 { 102 compatible = "simple-bus"; 103 #address-cells = <2>; 104 #size-cells = <1>; 105 ranges; 106 107 gic: interrupt-controller@600300000 { 108 compatible = "arm,gic-v3"; 109 #interrupt-cells = <3>; 110 #address-cells = <2>; 111 #size-cells = <2>; 112 interrupt-controller; 113 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ 114 <0x6 0x00340000 0xc0000>, /* GICR */ 115 <0x6 0x00200000 0x2000>, /* GICC */ 116 <0x6 0x00210000 0x2000>, /* GICV */ 117 <0x6 0x00220000 0x2000>; /* GICH */ 118 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 119 }; 120 121 uart0: serial@600100000 { 122 pinctrl-0 = <&uart_pins>; 123 pinctrl-names = "default"; 124 compatible = "ns16550a"; 125 reg = <0x6 0x00100000 0x20>; 126 clocks = <&ahb_clk>; 127 reg-io-width = <4>; 128 reg-shift = <2>; 129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 130 131 status = "disabled"; 132 }; 133 134 uart1: serial@600102000 { 135 pinctrl-0 = <&uart2_pins>; 136 pinctrl-names = "default"; 137 compatible = "ns16550a"; 138 reg = <0x6 0x00102000 0x20>; 139 clocks = <&ahb_clk>; 140 reg-io-width = <4>; 141 reg-shift = <2>; 142 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 143 144 status = "disabled"; 145 }; 146 147 timer1: timer@600105000 { 148 compatible = "snps,dw-apb-timer"; 149 reg = <0x6 0x00105000 0x1000>; 150 clocks = <&ahb_clk>; 151 clock-names = "timer"; 152 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 153 }; 154 155 sdhci0: mmc@600800000 { 156 compatible = "microchip,dw-sparx5-sdhci"; 157 status = "disabled"; 158 reg = <0x6 0x00800000 0x1000>; 159 pinctrl-0 = <&emmc_pins>; 160 pinctrl-names = "default"; 161 clocks = <&clks CLK_ID_AUX1>; 162 clock-names = "core"; 163 assigned-clocks = <&clks CLK_ID_AUX1>; 164 assigned-clock-rates = <800000000>; 165 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 166 bus-width = <8>; 167 }; 168 169 gpio: pinctrl@6110101e0 { 170 compatible = "microchip,sparx5-pinctrl"; 171 reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; 172 gpio-controller; 173 #gpio-cells = <2>; 174 gpio-ranges = <&gpio 0 0 64>; 175 interrupt-controller; 176 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 177 #interrupt-cells = <2>; 178 179 uart_pins: uart-pins { 180 pins = "GPIO_10", "GPIO_11"; 181 function = "uart"; 182 }; 183 184 uart2_pins: uart2-pins { 185 pins = "GPIO_26", "GPIO_27"; 186 function = "uart2"; 187 }; 188 189 i2c_pins: i2c-pins { 190 pins = "GPIO_14", "GPIO_15"; 191 function = "twi"; 192 }; 193 194 i2c2_pins: i2c2-pins { 195 pins = "GPIO_28", "GPIO_29"; 196 function = "twi2"; 197 }; 198 199 emmc_pins: emmc-pins { 200 pins = "GPIO_34", "GPIO_35", "GPIO_36", 201 "GPIO_37", "GPIO_38", "GPIO_39", 202 "GPIO_40", "GPIO_41", "GPIO_42", 203 "GPIO_43", "GPIO_44", "GPIO_45", 204 "GPIO_46", "GPIO_47"; 205 function = "emmc"; 206 }; 207 }; 208 209 i2c0: i2c@600101000 { 210 compatible = "snps,designware-i2c"; 211 status = "disabled"; 212 pinctrl-0 = <&i2c_pins>; 213 pinctrl-names = "default"; 214 reg = <0x6 0x00101000 0x100>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 218 i2c-sda-hold-time-ns = <300>; 219 clock-frequency = <100000>; 220 clocks = <&ahb_clk>; 221 }; 222 223 i2c1: i2c@600103000 { 224 compatible = "snps,designware-i2c"; 225 status = "disabled"; 226 pinctrl-0 = <&i2c2_pins>; 227 pinctrl-names = "default"; 228 reg = <0x6 0x00103000 0x100>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 232 i2c-sda-hold-time-ns = <300>; 233 clock-frequency = <100000>; 234 clocks = <&ahb_clk>; 235 }; 236 }; 237}; 238