1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	compatible = "microchip,sparx5";
11	interrupt-parent = <&gic>;
12	#address-cells = <2>;
13	#size-cells = <1>;
14
15	aliases {
16		serial0 = &uart0;
17		serial1 = &uart1;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	cpus {
25		#address-cells = <2>;
26		#size-cells = <0>;
27		cpu-map {
28			cluster0 {
29				core0 {
30					cpu = <&cpu0>;
31				};
32				core1 {
33					cpu = <&cpu1>;
34				};
35			};
36		};
37		cpu0: cpu@0 {
38			compatible = "arm,cortex-a53";
39			device_type = "cpu";
40			reg = <0x0 0x0>;
41			enable-method = "psci";
42			next-level-cache = <&L2_0>;
43		};
44		cpu1: cpu@1 {
45			compatible = "arm,cortex-a53";
46			device_type = "cpu";
47			reg = <0x0 0x1>;
48			enable-method = "psci";
49			next-level-cache = <&L2_0>;
50		};
51		L2_0: l2-cache0 {
52			compatible = "cache";
53		};
54	};
55
56	arm-pmu {
57		compatible = "arm,cortex-a53-pmu";
58		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
59		interrupt-affinity = <&cpu0>, <&cpu1>;
60	};
61
62	psci {
63		compatible = "arm,psci-0.2";
64		method = "smc";
65	};
66
67	timer {
68		compatible = "arm,armv8-timer";
69		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
70			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
71			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
72			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
73	};
74
75	lcpll_clk: lcpll-clk {
76		compatible = "fixed-clock";
77		#clock-cells = <0>;
78		clock-frequency = <2500000000>;
79	};
80
81	clks: clock-controller@61110000c {
82		compatible = "microchip,sparx5-dpll";
83		#clock-cells = <1>;
84		clocks = <&lcpll_clk>;
85		reg = <0x6 0x1110000c 0x24>;
86	};
87
88	ahb_clk: ahb-clk {
89		compatible = "fixed-clock";
90		#clock-cells = <0>;
91		clock-frequency = <250000000>;
92	};
93
94	sys_clk: sys-clk {
95		compatible = "fixed-clock";
96		#clock-cells = <0>;
97		clock-frequency = <625000000>;
98	};
99
100	axi: axi@600000000 {
101		compatible = "simple-bus";
102		#address-cells = <2>;
103		#size-cells = <1>;
104		ranges;
105
106		gic: interrupt-controller@600300000 {
107			compatible = "arm,gic-v3";
108			#interrupt-cells = <3>;
109			#address-cells = <2>;
110			#size-cells = <2>;
111			interrupt-controller;
112			reg = <0x6 0x00300000 0x10000>,	/* GIC Dist */
113			      <0x6 0x00340000 0xc0000>,	/* GICR */
114			      <0x6 0x00200000 0x2000>,	/* GICC */
115			      <0x6 0x00210000 0x2000>,  /* GICV */
116			      <0x6 0x00220000 0x2000>;  /* GICH */
117			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
118		};
119
120		uart0: serial@600100000 {
121			pinctrl-0 = <&uart_pins>;
122			pinctrl-names = "default";
123			compatible = "ns16550a";
124			reg = <0x6 0x00100000 0x20>;
125			clocks = <&ahb_clk>;
126			reg-io-width = <4>;
127			reg-shift = <2>;
128			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
129
130			status = "disabled";
131		};
132
133		uart1: serial@600102000 {
134			pinctrl-0 = <&uart2_pins>;
135			pinctrl-names = "default";
136			compatible = "ns16550a";
137			reg = <0x6 0x00102000 0x20>;
138			clocks = <&ahb_clk>;
139			reg-io-width = <4>;
140			reg-shift = <2>;
141			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
142
143			status = "disabled";
144		};
145
146		timer1: timer@600105000 {
147			compatible = "snps,dw-apb-timer";
148			reg = <0x6 0x00105000 0x1000>;
149			clocks = <&ahb_clk>;
150			clock-names = "timer";
151			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
152		};
153
154		gpio: pinctrl@6110101e0 {
155			compatible = "microchip,sparx5-pinctrl";
156			reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
157			gpio-controller;
158			#gpio-cells = <2>;
159			gpio-ranges = <&gpio 0 0 64>;
160			interrupt-controller;
161			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
162			#interrupt-cells = <2>;
163
164			uart_pins: uart-pins {
165				pins = "GPIO_10", "GPIO_11";
166				function = "uart";
167			};
168
169			uart2_pins: uart2-pins {
170				pins = "GPIO_26", "GPIO_27";
171				function = "uart2";
172			};
173		};
174	};
175};
176