1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 */ 5 6#include <dt-bindings/clock/imx8ulp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/power/imx8ulp-power.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8ulp-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec; 21 gpio0 = &gpiod; 22 gpio1 = &gpioe; 23 gpio2 = &gpiof; 24 mmc0 = &usdhc0; 25 mmc1 = &usdhc1; 26 mmc2 = &usdhc2; 27 serial0 = &lpuart4; 28 serial1 = &lpuart5; 29 serial2 = &lpuart6; 30 serial3 = &lpuart7; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 A35_0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a35"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 next-level-cache = <&A35_L2>; 43 cpu-idle-states = <&cpu_sleep>; 44 }; 45 46 A35_1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a35"; 49 reg = <0x0 0x1>; 50 enable-method = "psci"; 51 next-level-cache = <&A35_L2>; 52 cpu-idle-states = <&cpu_sleep>; 53 }; 54 55 A35_L2: l2-cache0 { 56 compatible = "cache"; 57 cache-level = <2>; 58 cache-unified; 59 }; 60 61 idle-states { 62 entry-method = "psci"; 63 64 cpu_sleep: cpu-sleep { 65 compatible = "arm,idle-state"; 66 arm,psci-suspend-param = <0x0>; 67 local-timer-stop; 68 entry-latency-us = <1000>; 69 exit-latency-us = <700>; 70 min-residency-us = <2700>; 71 }; 72 }; 73 }; 74 75 gic: interrupt-controller@2d400000 { 76 compatible = "arm,gic-v3"; 77 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ 78 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 79 #interrupt-cells = <3>; 80 interrupt-controller; 81 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 82 }; 83 84 pmu { 85 compatible = "arm,cortex-a35-pmu"; 86 interrupt-parent = <&gic>; 87 interrupts = <GIC_PPI 7 88 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 89 interrupt-affinity = <&A35_0>, <&A35_1>; 90 }; 91 92 psci { 93 compatible = "arm,psci-1.0"; 94 method = "smc"; 95 }; 96 97 thermal-zones { 98 cpu-thermal { 99 polling-delay-passive = <250>; 100 polling-delay = <2000>; 101 thermal-sensors = <&scmi_sensor 0>; 102 103 trips { 104 cpu_alert0: trip0 { 105 temperature = <85000>; 106 hysteresis = <2000>; 107 type = "passive"; 108 }; 109 110 cpu_crit0: trip1 { 111 temperature = <95000>; 112 hysteresis = <2000>; 113 type = "critical"; 114 }; 115 }; 116 }; 117 }; 118 119 timer { 120 compatible = "arm,armv8-timer"; 121 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 122 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 123 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 124 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 125 }; 126 127 frosc: clock-frosc { 128 compatible = "fixed-clock"; 129 clock-frequency = <192000000>; 130 clock-output-names = "frosc"; 131 #clock-cells = <0>; 132 }; 133 134 lposc: clock-lposc { 135 compatible = "fixed-clock"; 136 clock-frequency = <1000000>; 137 clock-output-names = "lposc"; 138 #clock-cells = <0>; 139 }; 140 141 rosc: clock-rosc { 142 compatible = "fixed-clock"; 143 clock-frequency = <32768>; 144 clock-output-names = "rosc"; 145 #clock-cells = <0>; 146 }; 147 148 sosc: clock-sosc { 149 compatible = "fixed-clock"; 150 clock-frequency = <24000000>; 151 clock-output-names = "sosc"; 152 #clock-cells = <0>; 153 }; 154 155 sram@2201f000 { 156 compatible = "mmio-sram"; 157 reg = <0x0 0x2201f000 0x0 0x1000>; 158 159 #address-cells = <1>; 160 #size-cells = <1>; 161 ranges = <0 0x0 0x2201f000 0x1000>; 162 163 scmi_buf: scmi-sram-section@0 { 164 compatible = "arm,scmi-shmem"; 165 reg = <0x0 0x400>; 166 }; 167 }; 168 169 firmware { 170 scmi { 171 compatible = "arm,scmi-smc"; 172 arm,smc-id = <0xc20000fe>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 shmem = <&scmi_buf>; 176 177 scmi_devpd: protocol@11 { 178 reg = <0x11>; 179 #power-domain-cells = <1>; 180 }; 181 182 scmi_sensor: protocol@15 { 183 reg = <0x15>; 184 #thermal-sensor-cells = <1>; 185 }; 186 }; 187 }; 188 189 cm33: remoteproc-cm33 { 190 compatible = "fsl,imx8ulp-cm33"; 191 status = "disabled"; 192 }; 193 194 soc: soc@0 { 195 compatible = "simple-bus"; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0x0 0x0 0x0 0x40000000>; 199 200 s4muap: mailbox@27020000 { 201 compatible = "fsl,imx8ulp-mu-s4"; 202 reg = <0x27020000 0x10000>; 203 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 204 #mbox-cells = <2>; 205 }; 206 207 per_bridge3: bus@29000000 { 208 compatible = "simple-bus"; 209 reg = <0x29000000 0x800000>; 210 #address-cells = <1>; 211 #size-cells = <1>; 212 ranges; 213 214 mu: mailbox@29220000 { 215 compatible = "fsl,imx8ulp-mu"; 216 reg = <0x29220000 0x10000>; 217 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 218 #mbox-cells = <2>; 219 status = "disabled"; 220 }; 221 222 mu3: mailbox@29230000 { 223 compatible = "fsl,imx8ulp-mu"; 224 reg = <0x29230000 0x10000>; 225 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&pcc3 IMX8ULP_CLK_MU3_A>; 227 #mbox-cells = <2>; 228 status = "disabled"; 229 }; 230 231 wdog3: watchdog@292a0000 { 232 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; 233 reg = <0x292a0000 0x10000>; 234 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 236 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; 237 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; 238 timeout-sec = <40>; 239 }; 240 241 cgc1: clock-controller@292c0000 { 242 compatible = "fsl,imx8ulp-cgc1"; 243 reg = <0x292c0000 0x10000>; 244 #clock-cells = <1>; 245 }; 246 247 pcc3: clock-controller@292d0000 { 248 compatible = "fsl,imx8ulp-pcc3"; 249 reg = <0x292d0000 0x10000>; 250 #clock-cells = <1>; 251 #reset-cells = <1>; 252 }; 253 254 tpm5: tpm@29340000 { 255 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; 256 reg = <0x29340000 0x1000>; 257 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&pcc3 IMX8ULP_CLK_TPM5>, 259 <&pcc3 IMX8ULP_CLK_TPM5>; 260 clock-names = "ipg", "per"; 261 status = "disabled"; 262 }; 263 264 lpi2c4: i2c@29370000 { 265 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 266 reg = <0x29370000 0x10000>; 267 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, 269 <&pcc3 IMX8ULP_CLK_LPI2C4>; 270 clock-names = "per", "ipg"; 271 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; 272 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 273 assigned-clock-rates = <48000000>; 274 status = "disabled"; 275 }; 276 277 lpi2c5: i2c@29380000 { 278 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 279 reg = <0x29380000 0x10000>; 280 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, 282 <&pcc3 IMX8ULP_CLK_LPI2C5>; 283 clock-names = "per", "ipg"; 284 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; 285 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 286 assigned-clock-rates = <48000000>; 287 status = "disabled"; 288 }; 289 290 lpuart4: serial@29390000 { 291 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 292 reg = <0x29390000 0x1000>; 293 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; 295 clock-names = "ipg"; 296 status = "disabled"; 297 }; 298 299 lpuart5: serial@293a0000 { 300 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 301 reg = <0x293a0000 0x1000>; 302 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; 304 clock-names = "ipg"; 305 status = "disabled"; 306 }; 307 308 lpspi4: spi@293b0000 { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 312 reg = <0x293b0000 0x10000>; 313 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, 315 <&pcc3 IMX8ULP_CLK_LPSPI4>; 316 clock-names = "per", "ipg"; 317 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; 318 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 319 assigned-clock-rates = <48000000>; 320 status = "disabled"; 321 }; 322 323 lpspi5: spi@293c0000 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; 327 reg = <0x293c0000 0x10000>; 328 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, 330 <&pcc3 IMX8ULP_CLK_LPSPI5>; 331 clock-names = "per", "ipg"; 332 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; 333 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 334 assigned-clock-rates = <48000000>; 335 status = "disabled"; 336 }; 337 }; 338 339 per_bridge4: bus@29800000 { 340 compatible = "simple-bus"; 341 reg = <0x29800000 0x800000>; 342 #address-cells = <1>; 343 #size-cells = <1>; 344 ranges; 345 346 pcc4: clock-controller@29800000 { 347 compatible = "fsl,imx8ulp-pcc4"; 348 reg = <0x29800000 0x10000>; 349 #clock-cells = <1>; 350 #reset-cells = <1>; 351 }; 352 353 lpi2c6: i2c@29840000 { 354 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 355 reg = <0x29840000 0x10000>; 356 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, 358 <&pcc4 IMX8ULP_CLK_LPI2C6>; 359 clock-names = "per", "ipg"; 360 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; 361 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 362 assigned-clock-rates = <48000000>; 363 status = "disabled"; 364 }; 365 366 lpi2c7: i2c@29850000 { 367 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; 368 reg = <0x29850000 0x10000>; 369 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, 371 <&pcc4 IMX8ULP_CLK_LPI2C7>; 372 clock-names = "per", "ipg"; 373 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; 374 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; 375 assigned-clock-rates = <48000000>; 376 status = "disabled"; 377 }; 378 379 lpuart6: serial@29860000 { 380 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 381 reg = <0x29860000 0x1000>; 382 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; 384 clock-names = "ipg"; 385 status = "disabled"; 386 }; 387 388 lpuart7: serial@29870000 { 389 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 390 reg = <0x29870000 0x1000>; 391 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; 393 clock-names = "ipg"; 394 status = "disabled"; 395 }; 396 397 iomuxc1: pinctrl@298c0000 { 398 compatible = "fsl,imx8ulp-iomuxc1"; 399 reg = <0x298c0000 0x10000>; 400 }; 401 402 usdhc0: mmc@298d0000 { 403 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 404 reg = <0x298d0000 0x10000>; 405 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 407 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, 408 <&pcc4 IMX8ULP_CLK_USDHC0>; 409 clock-names = "ipg", "ahb", "per"; 410 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; 411 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>, 412 <&pcc4 IMX8ULP_CLK_USDHC0>; 413 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>; 414 assigned-clock-rates = <389283840>, <389283840>; 415 fsl,tuning-start-tap = <20>; 416 fsl,tuning-step = <2>; 417 bus-width = <4>; 418 status = "disabled"; 419 }; 420 421 usdhc1: mmc@298e0000 { 422 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 423 reg = <0x298e0000 0x10000>; 424 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 426 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 427 <&pcc4 IMX8ULP_CLK_USDHC1>; 428 clock-names = "ipg", "ahb", "per"; 429 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; 430 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, 431 <&pcc4 IMX8ULP_CLK_USDHC1>; 432 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 433 assigned-clock-rates = <194641920>, <194641920>; 434 fsl,tuning-start-tap = <20>; 435 fsl,tuning-step = <2>; 436 bus-width = <4>; 437 status = "disabled"; 438 }; 439 440 usdhc2: mmc@298f0000 { 441 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; 442 reg = <0x298f0000 0x10000>; 443 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 445 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, 446 <&pcc4 IMX8ULP_CLK_USDHC2>; 447 clock-names = "ipg", "ahb", "per"; 448 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; 449 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, 450 <&pcc4 IMX8ULP_CLK_USDHC2>; 451 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; 452 assigned-clock-rates = <194641920>, <194641920>; 453 fsl,tuning-start-tap = <20>; 454 fsl,tuning-step = <2>; 455 bus-width = <4>; 456 status = "disabled"; 457 }; 458 459 fec: ethernet@29950000 { 460 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec"; 461 reg = <0x29950000 0x10000>; 462 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-names = "int0"; 464 fsl,num-tx-queues = <1>; 465 fsl,num-rx-queues = <1>; 466 status = "disabled"; 467 }; 468 }; 469 470 gpioe: gpio@2d000080 { 471 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 472 reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; 473 gpio-controller; 474 #gpio-cells = <2>; 475 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 476 interrupt-controller; 477 #interrupt-cells = <2>; 478 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, 479 <&pcc4 IMX8ULP_CLK_PCTLE>; 480 clock-names = "gpio", "port"; 481 gpio-ranges = <&iomuxc1 0 32 24>; 482 }; 483 484 gpiof: gpio@2d010080 { 485 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 486 reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; 487 gpio-controller; 488 #gpio-cells = <2>; 489 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, 493 <&pcc4 IMX8ULP_CLK_PCTLF>; 494 clock-names = "gpio", "port"; 495 gpio-ranges = <&iomuxc1 0 64 32>; 496 }; 497 498 per_bridge5: bus@2d800000 { 499 compatible = "simple-bus"; 500 reg = <0x2d800000 0x800000>; 501 #address-cells = <1>; 502 #size-cells = <1>; 503 ranges; 504 505 cgc2: clock-controller@2da60000 { 506 compatible = "fsl,imx8ulp-cgc2"; 507 reg = <0x2da60000 0x10000>; 508 #clock-cells = <1>; 509 }; 510 511 pcc5: clock-controller@2da70000 { 512 compatible = "fsl,imx8ulp-pcc5"; 513 reg = <0x2da70000 0x10000>; 514 #clock-cells = <1>; 515 #reset-cells = <1>; 516 }; 517 }; 518 519 gpiod: gpio@2e200080 { 520 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; 521 reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; 522 gpio-controller; 523 #gpio-cells = <2>; 524 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-controller; 526 #interrupt-cells = <2>; 527 clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, 528 <&pcc5 IMX8ULP_CLK_RGPIOD>; 529 clock-names = "gpio", "port"; 530 gpio-ranges = <&iomuxc1 0 0 24>; 531 }; 532 }; 533}; 534