1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 NXP
4 */
5
6#include <dt-bindings/clock/imx8ulp-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/power/imx8ulp-power.h>
10
11#include "imx8ulp-pinfunc.h"
12
13/ {
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	aliases {
19		ethernet0 = &fec;
20		gpio0 = &gpiod;
21		gpio1 = &gpioe;
22		gpio2 = &gpiof;
23		mmc0 = &usdhc0;
24		mmc1 = &usdhc1;
25		mmc2 = &usdhc2;
26		serial0 = &lpuart4;
27		serial1 = &lpuart5;
28		serial2 = &lpuart6;
29		serial3 = &lpuart7;
30	};
31
32	cpus {
33		#address-cells = <2>;
34		#size-cells = <0>;
35
36		A35_0: cpu@0 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a35";
39			reg = <0x0 0x0>;
40			enable-method = "psci";
41			next-level-cache = <&A35_L2>;
42		};
43
44		A35_1: cpu@1 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a35";
47			reg = <0x0 0x1>;
48			enable-method = "psci";
49			next-level-cache = <&A35_L2>;
50		};
51
52		A35_L2: l2-cache0 {
53			compatible = "cache";
54			cache-level = <2>;
55			cache-unified;
56		};
57	};
58
59	gic: interrupt-controller@2d400000 {
60		compatible = "arm,gic-v3";
61		reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
62		      <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
63		#interrupt-cells = <3>;
64		interrupt-controller;
65		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
66	};
67
68	pmu {
69		compatible = "arm,cortex-a35-pmu";
70		interrupt-parent = <&gic>;
71		interrupts = <GIC_PPI 7
72			     (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
73		interrupt-affinity = <&A35_0>, <&A35_1>;
74	};
75
76	psci {
77		compatible = "arm,psci-1.0";
78		method = "smc";
79	};
80
81	timer {
82		compatible = "arm,armv8-timer";
83		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
84			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
85			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
86			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
87	};
88
89	frosc: clock-frosc {
90		compatible = "fixed-clock";
91		clock-frequency = <192000000>;
92		clock-output-names = "frosc";
93		#clock-cells = <0>;
94	};
95
96	lposc: clock-lposc {
97		compatible = "fixed-clock";
98		clock-frequency = <1000000>;
99		clock-output-names = "lposc";
100		#clock-cells = <0>;
101	};
102
103	rosc: clock-rosc {
104		compatible = "fixed-clock";
105		clock-frequency = <32768>;
106		clock-output-names = "rosc";
107		#clock-cells = <0>;
108	};
109
110	sosc: clock-sosc {
111		compatible = "fixed-clock";
112		clock-frequency = <24000000>;
113		clock-output-names = "sosc";
114		#clock-cells = <0>;
115	};
116
117	sram@2201f000 {
118		compatible = "mmio-sram";
119		reg = <0x0 0x2201f000 0x0 0x1000>;
120
121		#address-cells = <1>;
122		#size-cells = <1>;
123		ranges = <0 0x0 0x2201f000 0x1000>;
124
125		scmi_buf: scmi-sram-section@0 {
126			compatible = "arm,scmi-shmem";
127			reg = <0x0 0x400>;
128		};
129	};
130
131	firmware {
132		scmi {
133			compatible = "arm,scmi-smc";
134			arm,smc-id = <0xc20000fe>;
135			#address-cells = <1>;
136			#size-cells = <0>;
137			shmem = <&scmi_buf>;
138
139			scmi_devpd: protocol@11 {
140				reg = <0x11>;
141				#power-domain-cells = <1>;
142			};
143
144			scmi_sensor: protocol@15 {
145				reg = <0x15>;
146				#thermal-sensor-cells = <1>;
147			};
148		};
149	};
150
151	soc: soc@0 {
152		compatible = "simple-bus";
153		#address-cells = <1>;
154		#size-cells = <1>;
155		ranges = <0x0 0x0 0x0 0x40000000>;
156
157		s4muap: mailbox@27020000 {
158			compatible = "fsl,imx8ulp-mu-s4";
159			reg = <0x27020000 0x10000>;
160			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
161			#mbox-cells = <2>;
162		};
163
164		per_bridge3: bus@29000000 {
165			compatible = "simple-bus";
166			reg = <0x29000000 0x800000>;
167			#address-cells = <1>;
168			#size-cells = <1>;
169			ranges;
170
171			mu: mailbox@29220000 {
172				compatible = "fsl,imx8ulp-mu";
173				reg = <0x29220000 0x10000>;
174				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
175				#mbox-cells = <2>;
176				status = "disabled";
177			};
178
179			mu3: mailbox@29230000 {
180				compatible = "fsl,imx8ulp-mu";
181				reg = <0x29230000 0x10000>;
182				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
183				clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
184				#mbox-cells = <2>;
185				status = "disabled";
186			};
187
188			wdog3: watchdog@292a0000 {
189				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
190				reg = <0x292a0000 0x10000>;
191				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
192				clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
193				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
194				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
195				timeout-sec = <40>;
196			};
197
198			cgc1: clock-controller@292c0000 {
199				compatible = "fsl,imx8ulp-cgc1";
200				reg = <0x292c0000 0x10000>;
201				#clock-cells = <1>;
202			};
203
204			pcc3: clock-controller@292d0000 {
205				compatible = "fsl,imx8ulp-pcc3";
206				reg = <0x292d0000 0x10000>;
207				#clock-cells = <1>;
208				#reset-cells = <1>;
209			};
210
211			tpm5: tpm@29340000 {
212				compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
213				reg = <0x29340000 0x1000>;
214				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
215				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
216					 <&pcc3 IMX8ULP_CLK_TPM5>;
217				clock-names = "ipg", "per";
218				status = "disabled";
219			};
220
221			lpi2c4: i2c@29370000 {
222				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
223				reg = <0x29370000 0x10000>;
224				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
225				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
226					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
227				clock-names = "per", "ipg";
228				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
229				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
230				assigned-clock-rates = <48000000>;
231				status = "disabled";
232			};
233
234			lpi2c5: i2c@29380000 {
235				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
236				reg = <0x29380000 0x10000>;
237				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
238				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
239					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
240				clock-names = "per", "ipg";
241				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
242				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
243				assigned-clock-rates = <48000000>;
244				status = "disabled";
245			};
246
247			lpuart4: serial@29390000 {
248				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
249				reg = <0x29390000 0x1000>;
250				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
251				clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
252				clock-names = "ipg";
253				status = "disabled";
254			};
255
256			lpuart5: serial@293a0000 {
257				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
258				reg = <0x293a0000 0x1000>;
259				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
260				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
261				clock-names = "ipg";
262				status = "disabled";
263			};
264
265			lpspi4: spi@293b0000 {
266				#address-cells = <1>;
267				#size-cells = <0>;
268				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
269				reg = <0x293b0000 0x10000>;
270				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
271				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
272					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
273				clock-names = "per", "ipg";
274				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
275				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
276				assigned-clock-rates = <48000000>;
277				status = "disabled";
278			};
279
280			lpspi5: spi@293c0000 {
281				#address-cells = <1>;
282				#size-cells = <0>;
283				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
284				reg = <0x293c0000 0x10000>;
285				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
286				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
287					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
288				clock-names = "per", "ipg";
289				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
290				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
291				assigned-clock-rates = <48000000>;
292				status = "disabled";
293			};
294		};
295
296		per_bridge4: bus@29800000 {
297			compatible = "simple-bus";
298			reg = <0x29800000 0x800000>;
299			#address-cells = <1>;
300			#size-cells = <1>;
301			ranges;
302
303			pcc4: clock-controller@29800000 {
304				compatible = "fsl,imx8ulp-pcc4";
305				reg = <0x29800000 0x10000>;
306				#clock-cells = <1>;
307				#reset-cells = <1>;
308			};
309
310			lpi2c6: i2c@29840000 {
311				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
312				reg = <0x29840000 0x10000>;
313				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
314				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
315					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
316				clock-names = "per", "ipg";
317				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
318				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
319				assigned-clock-rates = <48000000>;
320				status = "disabled";
321			};
322
323			lpi2c7: i2c@29850000 {
324				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
325				reg = <0x29850000 0x10000>;
326				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
327				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
328					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
329				clock-names = "per", "ipg";
330				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
331				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
332				assigned-clock-rates = <48000000>;
333				status = "disabled";
334			};
335
336			lpuart6: serial@29860000 {
337				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
338				reg = <0x29860000 0x1000>;
339				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
340				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
341				clock-names = "ipg";
342				status = "disabled";
343			};
344
345			lpuart7: serial@29870000 {
346				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
347				reg = <0x29870000 0x1000>;
348				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
349				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
350				clock-names = "ipg";
351				status = "disabled";
352			};
353
354			iomuxc1: pinctrl@298c0000 {
355				compatible = "fsl,imx8ulp-iomuxc1";
356				reg = <0x298c0000 0x10000>;
357			};
358
359			usdhc0: mmc@298d0000 {
360				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
361				reg = <0x298d0000 0x10000>;
362				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
363				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
364					 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
365					 <&pcc4 IMX8ULP_CLK_USDHC0>;
366				clock-names = "ipg", "ahb", "per";
367				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
368				fsl,tuning-start-tap = <20>;
369				fsl,tuning-step = <2>;
370				bus-width = <4>;
371				status = "disabled";
372			};
373
374			usdhc1: mmc@298e0000 {
375				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
376				reg = <0x298e0000 0x10000>;
377				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
378				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
379					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
380					 <&pcc4 IMX8ULP_CLK_USDHC1>;
381				clock-names = "ipg", "ahb", "per";
382				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
383				fsl,tuning-start-tap = <20>;
384				fsl,tuning-step = <2>;
385				bus-width = <4>;
386				status = "disabled";
387			};
388
389			usdhc2: mmc@298f0000 {
390				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
391				reg = <0x298f0000 0x10000>;
392				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
393				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
394					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
395					 <&pcc4 IMX8ULP_CLK_USDHC2>;
396				clock-names = "ipg", "ahb", "per";
397				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
398				fsl,tuning-start-tap = <20>;
399				fsl,tuning-step = <2>;
400				bus-width = <4>;
401				status = "disabled";
402			};
403
404			fec: ethernet@29950000 {
405				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
406				reg = <0x29950000 0x10000>;
407				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
408				interrupt-names = "int0";
409				fsl,num-tx-queues = <1>;
410				fsl,num-rx-queues = <1>;
411				status = "disabled";
412			};
413		};
414
415		gpioe: gpio@2d000080 {
416				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
417				reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
418				gpio-controller;
419				#gpio-cells = <2>;
420				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
421				interrupt-controller;
422				#interrupt-cells = <2>;
423				clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
424					 <&pcc4 IMX8ULP_CLK_PCTLE>;
425				clock-names = "gpio", "port";
426				gpio-ranges = <&iomuxc1 0 32 24>;
427		};
428
429		gpiof: gpio@2d010080 {
430				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
431				reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
432				gpio-controller;
433				#gpio-cells = <2>;
434				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
435				interrupt-controller;
436				#interrupt-cells = <2>;
437				clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
438					 <&pcc4 IMX8ULP_CLK_PCTLF>;
439				clock-names = "gpio", "port";
440				gpio-ranges = <&iomuxc1 0 64 32>;
441		};
442
443		per_bridge5: bus@2d800000 {
444			compatible = "simple-bus";
445			reg = <0x2d800000 0x800000>;
446			#address-cells = <1>;
447			#size-cells = <1>;
448			ranges;
449
450			cgc2: clock-controller@2da60000 {
451				compatible = "fsl,imx8ulp-cgc2";
452				reg = <0x2da60000 0x10000>;
453				#clock-cells = <1>;
454			};
455
456			pcc5: clock-controller@2da70000 {
457				compatible = "fsl,imx8ulp-pcc5";
458				reg = <0x2da70000 0x10000>;
459				#clock-cells = <1>;
460				#reset-cells = <1>;
461			};
462		};
463
464		gpiod: gpio@2e200080 {
465			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
466			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
467			gpio-controller;
468			#gpio-cells = <2>;
469			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
470			interrupt-controller;
471			#interrupt-cells = <2>;
472			clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
473				 <&pcc5 IMX8ULP_CLK_RGPIOD>;
474			clock-names = "gpio", "port";
475			gpio-ranges = <&iomuxc1 0 0 24>;
476		};
477	};
478};
479