1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH 4 * Author: Teresa Remmet <t.remmet@phytec.de> 5 */ 6 7#include <dt-bindings/net/ti-dp83867.h> 8#include "imx8mp.dtsi" 9 10/ { 11 model = "PHYTEC phyCORE-i.MX8MP"; 12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 13 14 aliases { 15 rtc0 = &rv3028; 16 rtc1 = &snvs_rtc; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x0 0x40000000 0 0x80000000>; 22 }; 23}; 24 25&A53_0 { 26 cpu-supply = <&buck2>; 27}; 28 29&A53_1 { 30 cpu-supply = <&buck2>; 31}; 32 33&A53_2 { 34 cpu-supply = <&buck2>; 35}; 36 37&A53_3 { 38 cpu-supply = <&buck2>; 39}; 40 41/* ethernet 1 */ 42&fec { 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_fec>; 45 phy-mode = "rgmii-id"; 46 phy-handle = <ðphy1>; 47 fsl,magic-packet; 48 status = "okay"; 49 50 mdio { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 ethphy1: ethernet-phy@0 { 55 compatible = "ethernet-phy-ieee802.3-c22"; 56 reg = <0>; 57 interrupt-parent = <&gpio1>; 58 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 59 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 60 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 61 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 62 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 63 ti,min-output-impedance; 64 enet-phy-lane-no-swap; 65 }; 66 }; 67}; 68 69&flexspi { 70 pinctrl-names = "default"; 71 pinctrl-0 = <&pinctrl_flexspi0>; 72 status = "okay"; 73 74 som_flash: flash@0 { 75 compatible = "jedec,spi-nor"; 76 reg = <0>; 77 spi-max-frequency = <80000000>; 78 spi-tx-bus-width = <1>; 79 spi-rx-bus-width = <4>; 80 }; 81}; 82 83&i2c1 { 84 clock-frequency = <400000>; 85 pinctrl-names = "default", "gpio"; 86 pinctrl-0 = <&pinctrl_i2c1>; 87 pinctrl-1 = <&pinctrl_i2c1_gpio>; 88 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 89 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 90 status = "okay"; 91 92 pmic: pmic@25 { 93 reg = <0x25>; 94 compatible = "nxp,pca9450c"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_pmic>; 97 interrupt-parent = <&gpio4>; 98 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 99 100 regulators { 101 buck1: BUCK1 { 102 regulator-compatible = "BUCK1"; 103 regulator-min-microvolt = <600000>; 104 regulator-max-microvolt = <2187500>; 105 regulator-boot-on; 106 regulator-always-on; 107 regulator-ramp-delay = <3125>; 108 }; 109 110 buck2: BUCK2 { 111 regulator-compatible = "BUCK2"; 112 regulator-min-microvolt = <600000>; 113 regulator-max-microvolt = <2187500>; 114 regulator-boot-on; 115 regulator-always-on; 116 regulator-ramp-delay = <3125>; 117 }; 118 119 buck4: BUCK4 { 120 regulator-compatible = "BUCK4"; 121 regulator-min-microvolt = <600000>; 122 regulator-max-microvolt = <3400000>; 123 regulator-boot-on; 124 regulator-always-on; 125 }; 126 127 buck5: BUCK5 { 128 regulator-compatible = "BUCK5"; 129 regulator-min-microvolt = <600000>; 130 regulator-max-microvolt = <3400000>; 131 regulator-boot-on; 132 regulator-always-on; 133 }; 134 135 buck6: BUCK6 { 136 regulator-compatible = "BUCK6"; 137 regulator-min-microvolt = <600000>; 138 regulator-max-microvolt = <3400000>; 139 regulator-boot-on; 140 regulator-always-on; 141 }; 142 143 ldo1: LDO1 { 144 regulator-compatible = "LDO1"; 145 regulator-min-microvolt = <1600000>; 146 regulator-max-microvolt = <3300000>; 147 regulator-boot-on; 148 regulator-always-on; 149 }; 150 151 ldo2: LDO2 { 152 regulator-compatible = "LDO2"; 153 regulator-min-microvolt = <800000>; 154 regulator-max-microvolt = <1150000>; 155 regulator-boot-on; 156 regulator-always-on; 157 }; 158 159 ldo3: LDO3 { 160 regulator-compatible = "LDO3"; 161 regulator-min-microvolt = <800000>; 162 regulator-max-microvolt = <3300000>; 163 regulator-boot-on; 164 regulator-always-on; 165 }; 166 167 ldo4: LDO4 { 168 regulator-compatible = "LDO4"; 169 regulator-min-microvolt = <800000>; 170 regulator-max-microvolt = <3300000>; 171 regulator-boot-on; 172 regulator-always-on; 173 }; 174 175 ldo5: LDO5 { 176 regulator-compatible = "LDO5"; 177 regulator-min-microvolt = <1800000>; 178 regulator-max-microvolt = <3300000>; 179 }; 180 }; 181 }; 182 183 eeprom@51 { 184 compatible = "atmel,24c32"; 185 reg = <0x51>; 186 pagesize = <32>; 187 }; 188 189 rv3028: rtc@52 { 190 compatible = "microcrystal,rv3028"; 191 reg = <0x52>; 192 trickle-resistor-ohms = <3000>; 193 }; 194}; 195 196/* eMMC */ 197&usdhc3 { 198 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 199 pinctrl-0 = <&pinctrl_usdhc3>; 200 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 201 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 202 bus-width = <8>; 203 non-removable; 204 status = "okay"; 205}; 206 207&wdog1 { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_wdog>; 210 fsl,ext-reset-output; 211 status = "okay"; 212}; 213 214&iomuxc { 215 pinctrl_fec: fecgrp { 216 fsl,pins = < 217 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 218 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 219 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 220 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 221 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 222 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 223 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 224 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 225 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 226 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 227 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 228 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 229 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 230 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 231 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 232 >; 233 }; 234 235 pinctrl_flexspi0: flexspi0grp { 236 fsl,pins = < 237 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 238 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 239 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 240 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 241 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 242 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 243 >; 244 }; 245 246 pinctrl_i2c1: i2c1grp { 247 fsl,pins = < 248 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 249 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 250 >; 251 }; 252 253 pinctrl_i2c1_gpio: i2c1gpiogrp { 254 fsl,pins = < 255 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 256 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 257 >; 258 }; 259 260 pinctrl_pmic: pmicirqgrp { 261 fsl,pins = < 262 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 263 >; 264 }; 265 266 pinctrl_usdhc3: usdhc3grp { 267 fsl,pins = < 268 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 269 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 270 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 271 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 272 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 273 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 274 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 275 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 276 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 277 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 278 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 279 >; 280 }; 281 282 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 283 fsl,pins = < 284 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 285 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 286 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 287 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 288 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 289 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 290 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 291 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 292 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 293 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 294 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 295 >; 296 }; 297 298 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 299 fsl,pins = < 300 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 301 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 302 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 303 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 304 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 305 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 306 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 307 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 308 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 309 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 310 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 311 >; 312 }; 313 314 pinctrl_wdog: wdoggrp { 315 fsl,pins = < 316 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 317 >; 318 }; 319}; 320