1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH 4 * Author: Teresa Remmet <t.remmet@phytec.de> 5 */ 6 7#include <dt-bindings/net/ti-dp83867.h> 8#include "imx8mp.dtsi" 9 10/ { 11 model = "PHYTEC phyCORE-i.MX8MP"; 12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; 13 14 aliases { 15 rtc0 = &rv3028; 16 rtc1 = &snvs_rtc; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x0 0x40000000 0 0x80000000>; 22 }; 23}; 24 25&A53_0 { 26 cpu-supply = <&buck2>; 27}; 28 29&A53_1 { 30 cpu-supply = <&buck2>; 31}; 32 33&A53_2 { 34 cpu-supply = <&buck2>; 35}; 36 37&A53_3 { 38 cpu-supply = <&buck2>; 39}; 40 41/* ethernet 1 */ 42&fec { 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_fec>; 45 phy-handle = <ðphy1>; 46 phy-mode = "rgmii-id"; 47 fsl,magic-packet; 48 status = "okay"; 49 50 mdio { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 54 ethphy1: ethernet-phy@0 { 55 compatible = "ethernet-phy-ieee802.3-c22"; 56 reg = <0>; 57 enet-phy-lane-no-swap; 58 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 59 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 60 ti,min-output-impedance; 61 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 62 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 63 }; 64 }; 65}; 66 67&flexspi { 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_flexspi0>; 70 status = "okay"; 71 72 som_flash: flash@0 { 73 compatible = "jedec,spi-nor"; 74 reg = <0>; 75 spi-max-frequency = <80000000>; 76 spi-rx-bus-width = <4>; 77 spi-tx-bus-width = <1>; 78 }; 79}; 80 81&i2c1 { 82 clock-frequency = <400000>; 83 pinctrl-names = "default", "gpio"; 84 pinctrl-0 = <&pinctrl_i2c1>; 85 pinctrl-1 = <&pinctrl_i2c1_gpio>; 86 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 87 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 88 status = "okay"; 89 90 pmic: pmic@25 { 91 compatible = "nxp,pca9450c"; 92 reg = <0x25>; 93 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 94 interrupt-parent = <&gpio4>; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_pmic>; 97 98 regulators { 99 buck1: BUCK1 { 100 regulator-always-on; 101 regulator-boot-on; 102 regulator-max-microvolt = <2187500>; 103 regulator-min-microvolt = <600000>; 104 regulator-ramp-delay = <3125>; 105 }; 106 107 buck2: BUCK2 { 108 nxp,dvs-run-voltage = <950000>; 109 nxp,dvs-standby-voltage = <850000>; 110 regulator-always-on; 111 regulator-boot-on; 112 regulator-max-microvolt = <2187500>; 113 regulator-min-microvolt = <600000>; 114 regulator-ramp-delay = <3125>; 115 }; 116 117 buck4: BUCK4 { 118 regulator-always-on; 119 regulator-boot-on; 120 regulator-max-microvolt = <3400000>; 121 regulator-min-microvolt = <600000>; 122 }; 123 124 buck5: BUCK5 { 125 regulator-always-on; 126 regulator-boot-on; 127 regulator-max-microvolt = <3400000>; 128 regulator-min-microvolt = <600000>; 129 }; 130 131 buck6: BUCK6 { 132 regulator-always-on; 133 regulator-boot-on; 134 regulator-max-microvolt = <3400000>; 135 regulator-min-microvolt = <600000>; 136 }; 137 138 ldo1: LDO1 { 139 regulator-always-on; 140 regulator-boot-on; 141 regulator-max-microvolt = <3300000>; 142 regulator-min-microvolt = <1600000>; 143 }; 144 145 ldo2: LDO2 { 146 regulator-always-on; 147 regulator-boot-on; 148 regulator-max-microvolt = <1150000>; 149 regulator-min-microvolt = <800000>; 150 }; 151 152 ldo3: LDO3 { 153 regulator-always-on; 154 regulator-boot-on; 155 regulator-max-microvolt = <3300000>; 156 regulator-min-microvolt = <800000>; 157 }; 158 159 ldo4: LDO4 { 160 regulator-max-microvolt = <3300000>; 161 regulator-min-microvolt = <800000>; 162 }; 163 164 ldo5: LDO5 { 165 regulator-always-on; 166 regulator-boot-on; 167 regulator-max-microvolt = <3300000>; 168 regulator-min-microvolt = <1800000>; 169 }; 170 }; 171 }; 172 173 eeprom@51 { 174 compatible = "atmel,24c32"; 175 reg = <0x51>; 176 pagesize = <32>; 177 }; 178 179 rv3028: rtc@52 { 180 compatible = "microcrystal,rv3028"; 181 reg = <0x52>; 182 trickle-resistor-ohms = <3000>; 183 }; 184}; 185 186/* eMMC */ 187&usdhc3 { 188 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 189 assigned-clock-rates = <400000000>; 190 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 191 pinctrl-0 = <&pinctrl_usdhc3>; 192 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 193 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 194 bus-width = <8>; 195 non-removable; 196 status = "okay"; 197}; 198 199&wdog1 { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_wdog>; 202 fsl,ext-reset-output; 203 status = "okay"; 204}; 205 206&iomuxc { 207 pinctrl_fec: fecgrp { 208 fsl,pins = < 209 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 210 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 211 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 212 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 213 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 214 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 215 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 216 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 217 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 218 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 219 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 220 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 221 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 222 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 223 >; 224 }; 225 226 pinctrl_flexspi0: flexspi0grp { 227 fsl,pins = < 228 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 229 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 230 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 231 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 232 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 233 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 234 >; 235 }; 236 237 pinctrl_i2c1: i2c1grp { 238 fsl,pins = < 239 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 240 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 241 >; 242 }; 243 244 pinctrl_i2c1_gpio: i2c1gpiogrp { 245 fsl,pins = < 246 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2 247 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2 248 >; 249 }; 250 251 pinctrl_pmic: pmicirqgrp { 252 fsl,pins = < 253 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 254 >; 255 }; 256 257 pinctrl_usdhc3: usdhc3grp { 258 fsl,pins = < 259 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 260 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 261 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 262 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 263 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 264 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 265 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 266 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 267 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 268 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 269 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 270 >; 271 }; 272 273 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 274 fsl,pins = < 275 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 276 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 277 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 278 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 279 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 280 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 281 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 282 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 283 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 284 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 285 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 286 >; 287 }; 288 289 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 290 fsl,pins = < 291 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 292 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 293 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 294 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 295 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 296 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 297 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 298 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 299 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 300 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 301 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 302 >; 303 }; 304 305 pinctrl_wdog: wdoggrp { 306 fsl,pins = < 307 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 308 >; 309 }; 310}; 311