|
Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3 |
|
| #
c2258a94 |
| 21-Apr-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: amlogic: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
meson-a1-ad401.dtb: l2-cache0: 'cache-
arm64: dts: amlogic: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
meson-a1-ad401.dtb: l2-cache0: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20230421223211.115612-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
show more ...
|
|
Revision tags: v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8 |
|
| #
3cbd431c |
| 18-Jan-2023 |
Christian Hewitt <christianshewitt@gmail.com> |
arm64: dts: meson: remove CPU opps below 1GHz for G12A boards
Amlogic G12A devices experience CPU stalls and random board wedges when
the system idles and CPU cores clock down to lower opp points. R
arm64: dts: meson: remove CPU opps below 1GHz for G12A boards
Amlogic G12A devices experience CPU stalls and random board wedges when
the system idles and CPU cores clock down to lower opp points. Recent
vendor kernels include a change to remove 100-250MHz and other distro
sources also remove the 500/667MHz points. Unless all 100-667Mhz opps
are removed or the CPU governor forced to performance stalls are still
observed, so let's remove them to improve stability and uptime.
Fixes: b190056fa9ee ("arm64: dts: meson-g12a: add cpus OPP table")
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Link: https://lore.kernel.org/r/20230119053031.21400-1-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
show more ...
|
|
Revision tags: v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78 |
|
| #
90cf8e21 |
| 08-Nov-2022 |
Jiucheng Xu <jiucheng.xu@amlogic.com> |
arm64: dts: meson: Add DDR PMU node
Add DDR PMU device node for G12 series SoC
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: htt
arm64: dts: meson: Add DDR PMU node
Add DDR PMU device node for G12 series SoC
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20221109015818.194927-4-jiucheng.xu@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
show more ...
|
| #
49f65e2e |
| 07-Nov-2022 |
Pierre Gondois <pierre.gondois@arm.com> |
arm64: dts: Update cache properties for amlogic
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Sha
arm64: dts: Update cache properties for amlogic
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-4-pierre.gondois@arm.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
show more ...
|
|
Revision tags: v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10, v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3 |
|
| #
8eef8bca |
| 04-Oct-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
arm64: dts: meson: g12a: add cooling properties
Add missing #colling-cells field for G12A SoC
Add cooling-map for passive and hot trip point
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
arm64: dts: meson: g12a: add cooling properties
Add missing #colling-cells field for G12A SoC
Add cooling-map for passive and hot trip point
Tested-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12 |
|
| #
2871626b |
| 05-Sep-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12: factor the power domain.
The power domain declared in the g12a and g12b dtsi are the same.
Move the declaration of these power domains in the g12 common dtsi.
Signed-off-by:
arm64: dts: meson: g12: factor the power domain.
The power domain declared in the g12a and g12b dtsi are the same.
Move the declaration of these power domains in the g12 common dtsi.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
| #
9ed437d6 |
| 05-Sep-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12: add a g12 layer
While the sm1 is very close to the g12a/b family, somethings apply
differently on the g12a/b and not the sm1. This introduce a new layer
of dtsi for part whic
arm64: dts: meson: g12: add a g12 layer
While the sm1 is very close to the g12a/b family, somethings apply
differently on the g12a/b and not the sm1. This introduce a new layer
of dtsi for part which apply to the g12a and g12b but not the sm1.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.2.11, v5.2.10 |
|
| #
f4f1c8d9 |
| 23-Aug-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12: add Everything-Else power domain controller
Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and setup the ri
arm64: dts: meson-g12: add Everything-Else power domain controller
Replace the VPU-centric power domain controller by the generic system-wide
Everything-Else power domain controller and setup the right power-domains
properties on the VPU, Ethernet & USB nodes.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
[khilman: minor subject edit: add dts]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5 |
|
| #
b190056f |
| 29-Jul-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12a: add cpus OPP table
Add the OPP table taken from the vendor u200 and u211 DTS.
The Amlogic G12A SoC seems to available in 3 types :
- low-speed: up to 1,8GHz
- mid-speed: up
arm64: dts: meson-g12a: add cpus OPP table
Add the OPP table taken from the vendor u200 and u211 DTS.
The Amlogic G12A SoC seems to available in 3 types :
- low-speed: up to 1,8GHz
- mid-speed: up to 1,908GHz
- high-speed: up to 2.1GHz
And the S905X2 opp voltages are slightly higher than the S905D2
OPP voltages for the low-speed table.
This adds the conservative OPP table with the S905X2 higher voltages
and the maximum low-speed OPP frequency.
The values were tested to be stable on an Amlogic U200 Reference Board,
SeiRobotics SEI510 and X96 Max Set-Top-Boxes running the arm64 cpuburn
at [1] and cycling between all the possible cpufreq translations and
checking the final frequency using the clock-measurer, script at [2].
[1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
[2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
| #
1499218c |
| 29-Jul-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
To simplify the representation of differences betweem the G12A and G12B
SoCs, move the common nodes into a meson-g12-common.dtsi fi
arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
To simplify the representation of differences betweem the G12A and G12B
SoCs, move the common nodes into a meson-g12-common.dtsi file and
express the CPU nodes and differences in meson-g12a.dtsi and meson-g12b.dtsi.
This separation will help for DVFS and future Amlogic SM1 Family support.
The sd_emmc_a quirk is added in the g12a/g12b since since it's already
known the sd_emmc_a controller is fixed in the next SM1 SoC family.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16 |
|
| #
3d4bacdc |
| 25-Jun-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson-g12a: add missing dwc2 phy-names
The G12A USB2 OTG capable PHY uses a 8bit large UTMI bus, and the OTG
controller gets the PHY but width by probing the associated phy.
By default
arm64: dts: meson-g12a: add missing dwc2 phy-names
The G12A USB2 OTG capable PHY uses a 8bit large UTMI bus, and the OTG
controller gets the PHY but width by probing the associated phy.
By default it will use 16bit wide settings if a phy is not specified,
in our case we specified the phy, but not the phy-names.
The dwc2 bindings specifies that if phys is present, phy-names shall be
"usb2-phy".
Adding phy-names = "usb2-phy" solves the OTG PHY bus configuration.
Fixes: 9baf7d6be730 ("arm64: dts: meson: g12a: Add G12A USB nodes")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9 |
|
| #
9a3f3714 |
| 10-Jun-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: sort sdio nodes correctly
Fix sdio node order in the soc device tree
Fixes: a1737347250e ("arm64: dts: meson: g12a: add SDIO controller")
Signed-off-by: Jerome Brunet <jbru
arm64: dts: meson: g12a: sort sdio nodes correctly
Fix sdio node order in the soc device tree
Fixes: a1737347250e ("arm64: dts: meson: g12a: add SDIO controller")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.1.8 |
|
| #
568465c3 |
| 08-Jun-2019 |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
arm64: dts: meson: g12a: add the GPIO interrupt controller
GPIO interrupts are used for the external Ethernet RGMII PHY interrupt
line.
Add the GPIO interrupt controller so we can describe that conn
arm64: dts: meson: g12a: add the GPIO interrupt controller
GPIO interrupts are used for the external Ethernet RGMII PHY interrupt
line.
Add the GPIO interrupt controller so we can describe that connection in
the dts files.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.1.7 |
|
| #
8a6b3ca2 |
| 03-Jun-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add SDIO controller
The Amlogic G12A SDIO Controller has a bug preventing direct DDR access,
add the port A (SDIO) pinctrl and controller nodes and mark this specific
contro
arm64: dts: meson: g12a: add SDIO controller
The Amlogic G12A SDIO Controller has a bug preventing direct DDR access,
add the port A (SDIO) pinctrl and controller nodes and mark this specific
controller with the amlogic,dram-access-quirk property.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.1.6 |
|
| #
1b2f377b |
| 27-May-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson: g12a: Add hwrng node
The Amlogic G12A has the hwrng module at the end of an unknown
"EFUSE" bus.
The hwrng is not enabled on the vendor G12A DTs, but is enabled on
next generatio
arm64: dts: meson: g12a: Add hwrng node
The Amlogic G12A has the hwrng module at the end of an unknown
"EFUSE" bus.
The hwrng is not enabled on the vendor G12A DTs, but is enabled on
next generation SM1 SoC family sharing the exact same memory mapping.
Let's add the "EFUSE" bus and the hwrng node.
This hwrng has been checked with the rng-tools rngtest FIPS tool :
rngtest: starting FIPS tests...
rngtest: bits received from input: 1630240032
rngtest: FIPS 140-2 successes: 81436
rngtest: FIPS 140-2 failures: 76
rngtest: FIPS 140-2(2001-10-10) Monobit: 10
rngtest: FIPS 140-2(2001-10-10) Poker: 6
rngtest: FIPS 140-2(2001-10-10) Runs: 26
rngtest: FIPS 140-2(2001-10-10) Long run: 34
rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
rngtest: input channel speed: (min=3.784; avg=5687.521; max=19073.486)Mibits/s
rngtest: FIPS tests speed: (min=47.684; avg=52.348; max=52.835)Mibits/s
rngtest: Program run time: 30000987 microseconds
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
|
Revision tags: v5.1.5, v5.1.4 |
|
| #
47b65cb8 |
| 20-May-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson: g12a: add drive strength for eth pins
With the X96 Max board using an external Gigabit Ethernet PHY,
add the same driver strength to the Ethernet pins as the vendor
tree.
Signed-
arm64: dts: meson: g12a: add drive strength for eth pins
With the X96 Max board using an external Gigabit Ethernet PHY,
add the same driver strength to the Ethernet pins as the vendor
tree.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
|
| #
d9b9640b |
| 20-May-2019 |
Neil Armstrong <narmstrong@baylibre.com> |
arm64: dts: meson: g12a: add drive-strength hdmi ddc pins
With the default boot settings, the DDC drive strength is too weak,
set the driver-strengh to 4mA to avoid errors on the DDC line.
Signed-o
arm64: dts: meson: g12a: add drive-strength hdmi ddc pins
With the default boot settings, the DDC drive strength is too weak,
set the driver-strengh to 4mA to avoid errors on the DDC line.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
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| #
280c17df |
| 20-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add mdio multiplexer
Add the g12a mdio multiplexer which allows to connect to either
an external phy through the SoC pins or the internal 10/100 phy
Signed-off-by: Jerome B
arm64: dts: meson: g12a: add mdio multiplexer
Add the g12a mdio multiplexer which allows to connect to either
an external phy through the SoC pins or the internal 10/100 phy
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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| #
3293252f |
| 20-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add ethernet pinctrl definitions
Add the ethernet pinctrl settings for RMII, RGMII and internal phy leds
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Ma
arm64: dts: meson: g12a: add ethernet pinctrl definitions
Add the ethernet pinctrl settings for RMII, RGMII and internal phy leds
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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| #
a466a867 |
| 20-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add ethernet mac controller
Add the synopsys ethernet mac controller embedded in the g12a SoC family.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Marti
arm64: dts: meson: g12a: add ethernet mac controller
Add the synopsys ethernet mac controller embedded in the g12a SoC family.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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|
Revision tags: v5.1.3 |
|
| #
d7556f49 |
| 16-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add tohdmitx
Add the hdmitx glue device linking the SoC audio interfaces to the
embedded Synopsys hdmi controller.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signe
arm64: dts: meson: g12a: add tohdmitx
Add the hdmitx glue device linking the SoC audio interfaces to the
embedded Synopsys hdmi controller.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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|
Revision tags: v5.1.2 |
|
| #
b894a8f1 |
| 14-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: enable hdmi_tx sound dai provider
At the moment the sysnopsys hdmi i2s driver provides a single playback
DAI. Add the corresponding sound-dai-cell to the hdmi device node.
arm64: dts: meson: g12a: enable hdmi_tx sound dai provider
At the moment the sysnopsys hdmi i2s driver provides a single playback
DAI. Add the corresponding sound-dai-cell to the hdmi device node.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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| #
e3d3b132 |
| 14-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add spdifin
Add the spdif input device node and the pinctrl definition for
this capture interface g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed
arm64: dts: meson: g12a: add spdifin
Add the spdif input device node and the pinctrl definition for
this capture interface g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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| #
9c5dc032 |
| 14-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add pdm
Add the pdm device node and the pinctrl definition for this capture
interface g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kev
arm64: dts: meson: g12a: add pdm
Add the pdm device node and the pinctrl definition for this capture
interface g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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| #
649675db |
| 14-May-2019 |
Jerome Brunet <jbrunet@baylibre.com> |
arm64: dts: meson: g12a: add spdifouts
Add the devices nodes and pinctrl definitions for the spdif outputs of
the g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by:
arm64: dts: meson: g12a: add spdifouts
Add the devices nodes and pinctrl definitions for the spdif outputs of
the g12a SoC family
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
show more ...
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