1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 apb: bus@ff600000 { 141 compatible = "simple-bus"; 142 reg = <0x0 0xff600000 0x0 0x200000>; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 146 147 hdmi_tx: hdmi-tx@0 { 148 compatible = "amlogic,meson-g12a-dw-hdmi"; 149 reg = <0x0 0x0 0x0 0x10000>; 150 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 151 resets = <&reset RESET_HDMITX_CAPB3>, 152 <&reset RESET_HDMITX_PHY>, 153 <&reset RESET_HDMITX>; 154 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 155 clocks = <&clkc CLKID_HDMI>, 156 <&clkc CLKID_HTX_PCLK>, 157 <&clkc CLKID_VPU_INTR>; 158 clock-names = "isfr", "iahb", "venci"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 status = "disabled"; 162 163 /* VPU VENC Input */ 164 hdmi_tx_venc_port: port@0 { 165 reg = <0>; 166 167 hdmi_tx_in: endpoint { 168 remote-endpoint = <&hdmi_tx_out>; 169 }; 170 }; 171 172 /* TMDS Output */ 173 hdmi_tx_tmds_port: port@1 { 174 reg = <1>; 175 }; 176 }; 177 178 periphs: bus@34400 { 179 compatible = "simple-bus"; 180 reg = <0x0 0x34400 0x0 0x400>; 181 #address-cells = <2>; 182 #size-cells = <2>; 183 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 184 185 periphs_pinctrl: pinctrl@40 { 186 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges; 190 191 gpio: bank@40 { 192 reg = <0x0 0x40 0x0 0x4c>, 193 <0x0 0xe8 0x0 0x18>, 194 <0x0 0x120 0x0 0x18>, 195 <0x0 0x2c0 0x0 0x40>, 196 <0x0 0x340 0x0 0x1c>; 197 reg-names = "gpio", 198 "pull", 199 "pull-enable", 200 "mux", 201 "ds"; 202 gpio-controller; 203 #gpio-cells = <2>; 204 gpio-ranges = <&periphs_pinctrl 0 0 86>; 205 }; 206 207 cec_ao_a_h_pins: cec_ao_a_h { 208 mux { 209 groups = "cec_ao_a_h"; 210 function = "cec_ao_a_h"; 211 bias-disable; 212 }; 213 }; 214 215 cec_ao_b_h_pins: cec_ao_b_h { 216 mux { 217 groups = "cec_ao_b_h"; 218 function = "cec_ao_b_h"; 219 bias-disable; 220 }; 221 }; 222 223 emmc_pins: emmc { 224 mux-0 { 225 groups = "emmc_nand_d0", 226 "emmc_nand_d1", 227 "emmc_nand_d2", 228 "emmc_nand_d3", 229 "emmc_nand_d4", 230 "emmc_nand_d5", 231 "emmc_nand_d6", 232 "emmc_nand_d7", 233 "emmc_cmd"; 234 function = "emmc"; 235 bias-pull-up; 236 drive-strength-microamp = <4000>; 237 }; 238 239 mux-1 { 240 groups = "emmc_clk"; 241 function = "emmc"; 242 bias-disable; 243 drive-strength-microamp = <4000>; 244 }; 245 }; 246 247 emmc_ds_pins: emmc-ds { 248 mux { 249 groups = "emmc_nand_ds"; 250 function = "emmc"; 251 bias-pull-down; 252 drive-strength-microamp = <4000>; 253 }; 254 }; 255 256 emmc_clk_gate_pins: emmc_clk_gate { 257 mux { 258 groups = "BOOT_8"; 259 function = "gpio_periphs"; 260 bias-pull-down; 261 drive-strength-microamp = <4000>; 262 }; 263 }; 264 265 hdmitx_ddc_pins: hdmitx_ddc { 266 mux { 267 groups = "hdmitx_sda", 268 "hdmitx_sck"; 269 function = "hdmitx"; 270 bias-disable; 271 }; 272 }; 273 274 hdmitx_hpd_pins: hdmitx_hpd { 275 mux { 276 groups = "hdmitx_hpd_in"; 277 function = "hdmitx"; 278 bias-disable; 279 }; 280 }; 281 282 283 i2c0_sda_c_pins: i2c0-sda-c { 284 mux { 285 groups = "i2c0_sda_c"; 286 function = "i2c0"; 287 bias-disable; 288 drive-strength-microamp = <3000>; 289 290 }; 291 }; 292 293 i2c0_sck_c_pins: i2c0-sck-c { 294 mux { 295 groups = "i2c0_sck_c"; 296 function = "i2c0"; 297 bias-disable; 298 drive-strength-microamp = <3000>; 299 }; 300 }; 301 302 i2c0_sda_z0_pins: i2c0-sda-z0 { 303 mux { 304 groups = "i2c0_sda_z0"; 305 function = "i2c0"; 306 bias-disable; 307 drive-strength-microamp = <3000>; 308 }; 309 }; 310 311 i2c0_sck_z1_pins: i2c0-sck-z1 { 312 mux { 313 groups = "i2c0_sck_z1"; 314 function = "i2c0"; 315 bias-disable; 316 drive-strength-microamp = <3000>; 317 }; 318 }; 319 320 i2c0_sda_z7_pins: i2c0-sda-z7 { 321 mux { 322 groups = "i2c0_sda_z7"; 323 function = "i2c0"; 324 bias-disable; 325 drive-strength-microamp = <3000>; 326 }; 327 }; 328 329 i2c0_sda_z8_pins: i2c0-sda-z8 { 330 mux { 331 groups = "i2c0_sda_z8"; 332 function = "i2c0"; 333 bias-disable; 334 drive-strength-microamp = <3000>; 335 }; 336 }; 337 338 i2c1_sda_x_pins: i2c1-sda-x { 339 mux { 340 groups = "i2c1_sda_x"; 341 function = "i2c1"; 342 bias-disable; 343 drive-strength-microamp = <3000>; 344 }; 345 }; 346 347 i2c1_sck_x_pins: i2c1-sck-x { 348 mux { 349 groups = "i2c1_sck_x"; 350 function = "i2c1"; 351 bias-disable; 352 drive-strength-microamp = <3000>; 353 }; 354 }; 355 356 i2c1_sda_h2_pins: i2c1-sda-h2 { 357 mux { 358 groups = "i2c1_sda_h2"; 359 function = "i2c1"; 360 bias-disable; 361 drive-strength-microamp = <3000>; 362 }; 363 }; 364 365 i2c1_sck_h3_pins: i2c1-sck-h3 { 366 mux { 367 groups = "i2c1_sck_h3"; 368 function = "i2c1"; 369 bias-disable; 370 drive-strength-microamp = <3000>; 371 }; 372 }; 373 374 i2c1_sda_h6_pins: i2c1-sda-h6 { 375 mux { 376 groups = "i2c1_sda_h6"; 377 function = "i2c1"; 378 bias-disable; 379 drive-strength-microamp = <3000>; 380 }; 381 }; 382 383 i2c1_sck_h7_pins: i2c1-sck-h7 { 384 mux { 385 groups = "i2c1_sck_h7"; 386 function = "i2c1"; 387 bias-disable; 388 drive-strength-microamp = <3000>; 389 }; 390 }; 391 392 i2c2_sda_x_pins: i2c2-sda-x { 393 mux { 394 groups = "i2c2_sda_x"; 395 function = "i2c2"; 396 bias-disable; 397 drive-strength-microamp = <3000>; 398 }; 399 }; 400 401 i2c2_sck_x_pins: i2c2-sck-x { 402 mux { 403 groups = "i2c2_sck_x"; 404 function = "i2c2"; 405 bias-disable; 406 drive-strength-microamp = <3000>; 407 }; 408 }; 409 410 i2c2_sda_z_pins: i2c2-sda-z { 411 mux { 412 groups = "i2c2_sda_z"; 413 function = "i2c2"; 414 bias-disable; 415 drive-strength-microamp = <3000>; 416 }; 417 }; 418 419 i2c2_sck_z_pins: i2c2-sck-z { 420 mux { 421 groups = "i2c2_sck_z"; 422 function = "i2c2"; 423 bias-disable; 424 drive-strength-microamp = <3000>; 425 }; 426 }; 427 428 i2c3_sda_h_pins: i2c3-sda-h { 429 mux { 430 groups = "i2c3_sda_h"; 431 function = "i2c3"; 432 bias-disable; 433 drive-strength-microamp = <3000>; 434 }; 435 }; 436 437 i2c3_sck_h_pins: i2c3-sck-h { 438 mux { 439 groups = "i2c3_sck_h"; 440 function = "i2c3"; 441 bias-disable; 442 drive-strength-microamp = <3000>; 443 }; 444 }; 445 446 i2c3_sda_a_pins: i2c3-sda-a { 447 mux { 448 groups = "i2c3_sda_a"; 449 function = "i2c3"; 450 bias-disable; 451 drive-strength-microamp = <3000>; 452 }; 453 }; 454 455 i2c3_sck_a_pins: i2c3-sck-a { 456 mux { 457 groups = "i2c3_sck_a"; 458 function = "i2c3"; 459 bias-disable; 460 drive-strength-microamp = <3000>; 461 }; 462 }; 463 464 mclk0_a_pins: mclk0-a { 465 mux { 466 groups = "mclk0_a"; 467 function = "mclk0"; 468 bias-disable; 469 drive-strength-microamp = <3000>; 470 }; 471 }; 472 473 mclk1_a_pins: mclk1-a { 474 mux { 475 groups = "mclk1_a"; 476 function = "mclk1"; 477 bias-disable; 478 drive-strength-microamp = <3000>; 479 }; 480 }; 481 482 mclk1_x_pins: mclk1-x { 483 mux { 484 groups = "mclk1_x"; 485 function = "mclk1"; 486 bias-disable; 487 drive-strength-microamp = <3000>; 488 }; 489 }; 490 491 mclk1_z_pins: mclk1-z { 492 mux { 493 groups = "mclk1_z"; 494 function = "mclk1"; 495 bias-disable; 496 drive-strength-microamp = <3000>; 497 }; 498 }; 499 500 pdm_din0_a_pins: pdm-din0-a { 501 mux { 502 groups = "pdm_din0_a"; 503 function = "pdm"; 504 bias-disable; 505 }; 506 }; 507 508 pdm_din0_c_pins: pdm-din0-c { 509 mux { 510 groups = "pdm_din0_c"; 511 function = "pdm"; 512 bias-disable; 513 }; 514 }; 515 516 pdm_din0_x_pins: pdm-din0-x { 517 mux { 518 groups = "pdm_din0_x"; 519 function = "pdm"; 520 bias-disable; 521 }; 522 }; 523 524 pdm_din0_z_pins: pdm-din0-z { 525 mux { 526 groups = "pdm_din0_z"; 527 function = "pdm"; 528 bias-disable; 529 }; 530 }; 531 532 pdm_din1_a_pins: pdm-din1-a { 533 mux { 534 groups = "pdm_din1_a"; 535 function = "pdm"; 536 bias-disable; 537 }; 538 }; 539 540 pdm_din1_c_pins: pdm-din1-c { 541 mux { 542 groups = "pdm_din1_c"; 543 function = "pdm"; 544 bias-disable; 545 }; 546 }; 547 548 pdm_din1_x_pins: pdm-din1-x { 549 mux { 550 groups = "pdm_din1_x"; 551 function = "pdm"; 552 bias-disable; 553 }; 554 }; 555 556 pdm_din1_z_pins: pdm-din1-z { 557 mux { 558 groups = "pdm_din1_z"; 559 function = "pdm"; 560 bias-disable; 561 }; 562 }; 563 564 pdm_din2_a_pins: pdm-din2-a { 565 mux { 566 groups = "pdm_din2_a"; 567 function = "pdm"; 568 bias-disable; 569 }; 570 }; 571 572 pdm_din2_c_pins: pdm-din2-c { 573 mux { 574 groups = "pdm_din2_c"; 575 function = "pdm"; 576 bias-disable; 577 }; 578 }; 579 580 pdm_din2_x_pins: pdm-din2-x { 581 mux { 582 groups = "pdm_din2_x"; 583 function = "pdm"; 584 bias-disable; 585 }; 586 }; 587 588 pdm_din2_z_pins: pdm-din2-z { 589 mux { 590 groups = "pdm_din2_z"; 591 function = "pdm"; 592 bias-disable; 593 }; 594 }; 595 596 pdm_din3_a_pins: pdm-din3-a { 597 mux { 598 groups = "pdm_din3_a"; 599 function = "pdm"; 600 bias-disable; 601 }; 602 }; 603 604 pdm_din3_c_pins: pdm-din3-c { 605 mux { 606 groups = "pdm_din3_c"; 607 function = "pdm"; 608 bias-disable; 609 }; 610 }; 611 612 pdm_din3_x_pins: pdm-din3-x { 613 mux { 614 groups = "pdm_din3_x"; 615 function = "pdm"; 616 bias-disable; 617 }; 618 }; 619 620 pdm_din3_z_pins: pdm-din3-z { 621 mux { 622 groups = "pdm_din3_z"; 623 function = "pdm"; 624 bias-disable; 625 }; 626 }; 627 628 pdm_dclk_a_pins: pdm-dclk-a { 629 mux { 630 groups = "pdm_dclk_a"; 631 function = "pdm"; 632 bias-disable; 633 drive-strength-microamp = <500>; 634 }; 635 }; 636 637 pdm_dclk_c_pins: pdm-dclk-c { 638 mux { 639 groups = "pdm_dclk_c"; 640 function = "pdm"; 641 bias-disable; 642 drive-strength-microamp = <500>; 643 }; 644 }; 645 646 pdm_dclk_x_pins: pdm-dclk-x { 647 mux { 648 groups = "pdm_dclk_x"; 649 function = "pdm"; 650 bias-disable; 651 drive-strength-microamp = <500>; 652 }; 653 }; 654 655 pdm_dclk_z_pins: pdm-dclk-z { 656 mux { 657 groups = "pdm_dclk_z"; 658 function = "pdm"; 659 bias-disable; 660 drive-strength-microamp = <500>; 661 }; 662 }; 663 664 pwm_a_pins: pwm-a { 665 mux { 666 groups = "pwm_a"; 667 function = "pwm_a"; 668 bias-disable; 669 }; 670 }; 671 672 pwm_b_x7_pins: pwm-b-x7 { 673 mux { 674 groups = "pwm_b_x7"; 675 function = "pwm_b"; 676 bias-disable; 677 }; 678 }; 679 680 pwm_b_x19_pins: pwm-b-x19 { 681 mux { 682 groups = "pwm_b_x19"; 683 function = "pwm_b"; 684 bias-disable; 685 }; 686 }; 687 688 pwm_c_c_pins: pwm-c-c { 689 mux { 690 groups = "pwm_c_c"; 691 function = "pwm_c"; 692 bias-disable; 693 }; 694 }; 695 696 pwm_c_x5_pins: pwm-c-x5 { 697 mux { 698 groups = "pwm_c_x5"; 699 function = "pwm_c"; 700 bias-disable; 701 }; 702 }; 703 704 pwm_c_x8_pins: pwm-c-x8 { 705 mux { 706 groups = "pwm_c_x8"; 707 function = "pwm_c"; 708 bias-disable; 709 }; 710 }; 711 712 pwm_d_x3_pins: pwm-d-x3 { 713 mux { 714 groups = "pwm_d_x3"; 715 function = "pwm_d"; 716 bias-disable; 717 }; 718 }; 719 720 pwm_d_x6_pins: pwm-d-x6 { 721 mux { 722 groups = "pwm_d_x6"; 723 function = "pwm_d"; 724 bias-disable; 725 }; 726 }; 727 728 pwm_e_pins: pwm-e { 729 mux { 730 groups = "pwm_e"; 731 function = "pwm_e"; 732 bias-disable; 733 }; 734 }; 735 736 pwm_f_x_pins: pwm-f-x { 737 mux { 738 groups = "pwm_f_x"; 739 function = "pwm_f"; 740 bias-disable; 741 }; 742 }; 743 744 pwm_f_h_pins: pwm-f-h { 745 mux { 746 groups = "pwm_f_h"; 747 function = "pwm_f"; 748 bias-disable; 749 }; 750 }; 751 752 sdcard_c_pins: sdcard_c { 753 mux-0 { 754 groups = "sdcard_d0_c", 755 "sdcard_d1_c", 756 "sdcard_d2_c", 757 "sdcard_d3_c", 758 "sdcard_cmd_c"; 759 function = "sdcard"; 760 bias-pull-up; 761 drive-strength-microamp = <4000>; 762 }; 763 764 mux-1 { 765 groups = "sdcard_clk_c"; 766 function = "sdcard"; 767 bias-disable; 768 drive-strength-microamp = <4000>; 769 }; 770 }; 771 772 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 773 mux { 774 groups = "GPIOC_4"; 775 function = "gpio_periphs"; 776 bias-pull-down; 777 drive-strength-microamp = <4000>; 778 }; 779 }; 780 781 sdcard_z_pins: sdcard_z { 782 mux-0 { 783 groups = "sdcard_d0_z", 784 "sdcard_d1_z", 785 "sdcard_d2_z", 786 "sdcard_d3_z", 787 "sdcard_cmd_z"; 788 function = "sdcard"; 789 bias-pull-up; 790 drive-strength-microamp = <4000>; 791 }; 792 793 mux-1 { 794 groups = "sdcard_clk_z"; 795 function = "sdcard"; 796 bias-disable; 797 drive-strength-microamp = <4000>; 798 }; 799 }; 800 801 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 802 mux { 803 groups = "GPIOZ_6"; 804 function = "gpio_periphs"; 805 bias-pull-down; 806 drive-strength-microamp = <4000>; 807 }; 808 }; 809 810 spdif_out_h_pins: spdif-out-h { 811 mux { 812 groups = "spdif_out_h"; 813 function = "spdif_out"; 814 drive-strength-microamp = <500>; 815 bias-disable; 816 }; 817 }; 818 819 spdif_out_a11_pins: spdif-out-a11 { 820 mux { 821 groups = "spdif_out_a11"; 822 function = "spdif_out"; 823 drive-strength-microamp = <500>; 824 bias-disable; 825 }; 826 }; 827 828 spdif_out_a13_pins: spdif-out-a13 { 829 mux { 830 groups = "spdif_out_a13"; 831 function = "spdif_out"; 832 drive-strength-microamp = <500>; 833 bias-disable; 834 }; 835 }; 836 837 tdm_a_din0_pins: tdm-a-din0 { 838 mux { 839 groups = "tdm_a_din0"; 840 function = "tdm_a"; 841 bias-disable; 842 }; 843 }; 844 845 846 tdm_a_din1_pins: tdm-a-din1 { 847 mux { 848 groups = "tdm_a_din1"; 849 function = "tdm_a"; 850 bias-disable; 851 }; 852 }; 853 854 tdm_a_dout0_pins: tdm-a-dout0 { 855 mux { 856 groups = "tdm_a_dout0"; 857 function = "tdm_a"; 858 bias-disable; 859 drive-strength-microamp = <3000>; 860 }; 861 }; 862 863 tdm_a_dout1_pins: tdm-a-dout1 { 864 mux { 865 groups = "tdm_a_dout1"; 866 function = "tdm_a"; 867 bias-disable; 868 drive-strength-microamp = <3000>; 869 }; 870 }; 871 872 tdm_a_fs_pins: tdm-a-fs { 873 mux { 874 groups = "tdm_a_fs"; 875 function = "tdm_a"; 876 bias-disable; 877 drive-strength-microamp = <3000>; 878 }; 879 }; 880 881 tdm_a_sclk_pins: tdm-a-sclk { 882 mux { 883 groups = "tdm_a_sclk"; 884 function = "tdm_a"; 885 bias-disable; 886 drive-strength-microamp = <3000>; 887 }; 888 }; 889 890 tdm_a_slv_fs_pins: tdm-a-slv-fs { 891 mux { 892 groups = "tdm_a_slv_fs"; 893 function = "tdm_a"; 894 bias-disable; 895 }; 896 }; 897 898 899 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 900 mux { 901 groups = "tdm_a_slv_sclk"; 902 function = "tdm_a"; 903 bias-disable; 904 }; 905 }; 906 907 tdm_b_din0_pins: tdm-b-din0 { 908 mux { 909 groups = "tdm_b_din0"; 910 function = "tdm_b"; 911 bias-disable; 912 }; 913 }; 914 915 tdm_b_din1_pins: tdm-b-din1 { 916 mux { 917 groups = "tdm_b_din1"; 918 function = "tdm_b"; 919 bias-disable; 920 }; 921 }; 922 923 tdm_b_din2_pins: tdm-b-din2 { 924 mux { 925 groups = "tdm_b_din2"; 926 function = "tdm_b"; 927 bias-disable; 928 }; 929 }; 930 931 tdm_b_din3_a_pins: tdm-b-din3-a { 932 mux { 933 groups = "tdm_b_din3_a"; 934 function = "tdm_b"; 935 bias-disable; 936 }; 937 }; 938 939 tdm_b_din3_h_pins: tdm-b-din3-h { 940 mux { 941 groups = "tdm_b_din3_h"; 942 function = "tdm_b"; 943 bias-disable; 944 }; 945 }; 946 947 tdm_b_dout0_pins: tdm-b-dout0 { 948 mux { 949 groups = "tdm_b_dout0"; 950 function = "tdm_b"; 951 bias-disable; 952 drive-strength-microamp = <3000>; 953 }; 954 }; 955 956 tdm_b_dout1_pins: tdm-b-dout1 { 957 mux { 958 groups = "tdm_b_dout1"; 959 function = "tdm_b"; 960 bias-disable; 961 drive-strength-microamp = <3000>; 962 }; 963 }; 964 965 tdm_b_dout2_pins: tdm-b-dout2 { 966 mux { 967 groups = "tdm_b_dout2"; 968 function = "tdm_b"; 969 bias-disable; 970 drive-strength-microamp = <3000>; 971 }; 972 }; 973 974 tdm_b_dout3_a_pins: tdm-b-dout3-a { 975 mux { 976 groups = "tdm_b_dout3_a"; 977 function = "tdm_b"; 978 bias-disable; 979 drive-strength-microamp = <3000>; 980 }; 981 }; 982 983 tdm_b_dout3_h_pins: tdm-b-dout3-h { 984 mux { 985 groups = "tdm_b_dout3_h"; 986 function = "tdm_b"; 987 bias-disable; 988 drive-strength-microamp = <3000>; 989 }; 990 }; 991 992 tdm_b_fs_pins: tdm-b-fs { 993 mux { 994 groups = "tdm_b_fs"; 995 function = "tdm_b"; 996 bias-disable; 997 drive-strength-microamp = <3000>; 998 }; 999 }; 1000 1001 tdm_b_sclk_pins: tdm-b-sclk { 1002 mux { 1003 groups = "tdm_b_sclk"; 1004 function = "tdm_b"; 1005 bias-disable; 1006 drive-strength-microamp = <3000>; 1007 }; 1008 }; 1009 1010 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1011 mux { 1012 groups = "tdm_b_slv_fs"; 1013 function = "tdm_b"; 1014 bias-disable; 1015 }; 1016 }; 1017 1018 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1019 mux { 1020 groups = "tdm_b_slv_sclk"; 1021 function = "tdm_b"; 1022 bias-disable; 1023 }; 1024 }; 1025 1026 tdm_c_din0_a_pins: tdm-c-din0-a { 1027 mux { 1028 groups = "tdm_c_din0_a"; 1029 function = "tdm_c"; 1030 bias-disable; 1031 }; 1032 }; 1033 1034 tdm_c_din0_z_pins: tdm-c-din0-z { 1035 mux { 1036 groups = "tdm_c_din0_z"; 1037 function = "tdm_c"; 1038 bias-disable; 1039 }; 1040 }; 1041 1042 tdm_c_din1_a_pins: tdm-c-din1-a { 1043 mux { 1044 groups = "tdm_c_din1_a"; 1045 function = "tdm_c"; 1046 bias-disable; 1047 }; 1048 }; 1049 1050 tdm_c_din1_z_pins: tdm-c-din1-z { 1051 mux { 1052 groups = "tdm_c_din1_z"; 1053 function = "tdm_c"; 1054 bias-disable; 1055 }; 1056 }; 1057 1058 tdm_c_din2_a_pins: tdm-c-din2-a { 1059 mux { 1060 groups = "tdm_c_din2_a"; 1061 function = "tdm_c"; 1062 bias-disable; 1063 }; 1064 }; 1065 1066 tdm_c_din2_z_pins: tdm-c-din2-z { 1067 mux { 1068 groups = "tdm_c_din2_z"; 1069 function = "tdm_c"; 1070 bias-disable; 1071 }; 1072 }; 1073 1074 tdm_c_din3_a_pins: tdm-c-din3-a { 1075 mux { 1076 groups = "tdm_c_din3_a"; 1077 function = "tdm_c"; 1078 bias-disable; 1079 }; 1080 }; 1081 1082 tdm_c_din3_z_pins: tdm-c-din3-z { 1083 mux { 1084 groups = "tdm_c_din3_z"; 1085 function = "tdm_c"; 1086 bias-disable; 1087 }; 1088 }; 1089 1090 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1091 mux { 1092 groups = "tdm_c_dout0_a"; 1093 function = "tdm_c"; 1094 bias-disable; 1095 drive-strength-microamp = <3000>; 1096 }; 1097 }; 1098 1099 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1100 mux { 1101 groups = "tdm_c_dout0_z"; 1102 function = "tdm_c"; 1103 bias-disable; 1104 drive-strength-microamp = <3000>; 1105 }; 1106 }; 1107 1108 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1109 mux { 1110 groups = "tdm_c_dout1_a"; 1111 function = "tdm_c"; 1112 bias-disable; 1113 drive-strength-microamp = <3000>; 1114 }; 1115 }; 1116 1117 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1118 mux { 1119 groups = "tdm_c_dout1_z"; 1120 function = "tdm_c"; 1121 bias-disable; 1122 drive-strength-microamp = <3000>; 1123 }; 1124 }; 1125 1126 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1127 mux { 1128 groups = "tdm_c_dout2_a"; 1129 function = "tdm_c"; 1130 bias-disable; 1131 drive-strength-microamp = <3000>; 1132 }; 1133 }; 1134 1135 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1136 mux { 1137 groups = "tdm_c_dout2_z"; 1138 function = "tdm_c"; 1139 bias-disable; 1140 drive-strength-microamp = <3000>; 1141 }; 1142 }; 1143 1144 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1145 mux { 1146 groups = "tdm_c_dout3_a"; 1147 function = "tdm_c"; 1148 bias-disable; 1149 drive-strength-microamp = <3000>; 1150 }; 1151 }; 1152 1153 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1154 mux { 1155 groups = "tdm_c_dout3_z"; 1156 function = "tdm_c"; 1157 bias-disable; 1158 drive-strength-microamp = <3000>; 1159 }; 1160 }; 1161 1162 tdm_c_fs_a_pins: tdm-c-fs-a { 1163 mux { 1164 groups = "tdm_c_fs_a"; 1165 function = "tdm_c"; 1166 bias-disable; 1167 drive-strength-microamp = <3000>; 1168 }; 1169 }; 1170 1171 tdm_c_fs_z_pins: tdm-c-fs-z { 1172 mux { 1173 groups = "tdm_c_fs_z"; 1174 function = "tdm_c"; 1175 bias-disable; 1176 drive-strength-microamp = <3000>; 1177 }; 1178 }; 1179 1180 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1181 mux { 1182 groups = "tdm_c_sclk_a"; 1183 function = "tdm_c"; 1184 bias-disable; 1185 drive-strength-microamp = <3000>; 1186 }; 1187 }; 1188 1189 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1190 mux { 1191 groups = "tdm_c_sclk_z"; 1192 function = "tdm_c"; 1193 bias-disable; 1194 drive-strength-microamp = <3000>; 1195 }; 1196 }; 1197 1198 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1199 mux { 1200 groups = "tdm_c_slv_fs_a"; 1201 function = "tdm_c"; 1202 bias-disable; 1203 }; 1204 }; 1205 1206 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1207 mux { 1208 groups = "tdm_c_slv_fs_z"; 1209 function = "tdm_c"; 1210 bias-disable; 1211 }; 1212 }; 1213 1214 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1215 mux { 1216 groups = "tdm_c_slv_sclk_a"; 1217 function = "tdm_c"; 1218 bias-disable; 1219 }; 1220 }; 1221 1222 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1223 mux { 1224 groups = "tdm_c_slv_sclk_z"; 1225 function = "tdm_c"; 1226 bias-disable; 1227 }; 1228 }; 1229 1230 uart_a_pins: uart-a { 1231 mux { 1232 groups = "uart_a_tx", 1233 "uart_a_rx"; 1234 function = "uart_a"; 1235 bias-disable; 1236 }; 1237 }; 1238 1239 uart_a_cts_rts_pins: uart-a-cts-rts { 1240 mux { 1241 groups = "uart_a_cts", 1242 "uart_a_rts"; 1243 function = "uart_a"; 1244 bias-disable; 1245 }; 1246 }; 1247 1248 uart_b_pins: uart-b { 1249 mux { 1250 groups = "uart_b_tx", 1251 "uart_b_rx"; 1252 function = "uart_b"; 1253 bias-disable; 1254 }; 1255 }; 1256 1257 uart_c_pins: uart-c { 1258 mux { 1259 groups = "uart_c_tx", 1260 "uart_c_rx"; 1261 function = "uart_c"; 1262 bias-disable; 1263 }; 1264 }; 1265 1266 uart_c_cts_rts_pins: uart-c-cts-rts { 1267 mux { 1268 groups = "uart_c_cts", 1269 "uart_c_rts"; 1270 function = "uart_c"; 1271 bias-disable; 1272 }; 1273 }; 1274 }; 1275 }; 1276 1277 usb2_phy0: phy@36000 { 1278 compatible = "amlogic,g12a-usb2-phy"; 1279 reg = <0x0 0x36000 0x0 0x2000>; 1280 clocks = <&xtal>; 1281 clock-names = "xtal"; 1282 resets = <&reset RESET_USB_PHY20>; 1283 reset-names = "phy"; 1284 #phy-cells = <0>; 1285 }; 1286 1287 dmc: bus@38000 { 1288 compatible = "simple-bus"; 1289 reg = <0x0 0x38000 0x0 0x400>; 1290 #address-cells = <2>; 1291 #size-cells = <2>; 1292 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1293 1294 canvas: video-lut@48 { 1295 compatible = "amlogic,canvas"; 1296 reg = <0x0 0x48 0x0 0x14>; 1297 }; 1298 }; 1299 1300 usb2_phy1: phy@3a000 { 1301 compatible = "amlogic,g12a-usb2-phy"; 1302 reg = <0x0 0x3a000 0x0 0x2000>; 1303 clocks = <&xtal>; 1304 clock-names = "xtal"; 1305 resets = <&reset RESET_USB_PHY21>; 1306 reset-names = "phy"; 1307 #phy-cells = <0>; 1308 }; 1309 1310 hiu: bus@3c000 { 1311 compatible = "simple-bus"; 1312 reg = <0x0 0x3c000 0x0 0x1400>; 1313 #address-cells = <2>; 1314 #size-cells = <2>; 1315 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1316 1317 hhi: system-controller@0 { 1318 compatible = "amlogic,meson-gx-hhi-sysctrl", 1319 "simple-mfd", "syscon"; 1320 reg = <0 0 0 0x400>; 1321 1322 clkc: clock-controller { 1323 compatible = "amlogic,g12a-clkc"; 1324 #clock-cells = <1>; 1325 clocks = <&xtal>; 1326 clock-names = "xtal"; 1327 }; 1328 }; 1329 }; 1330 1331 pdm: audio-controller@40000 { 1332 compatible = "amlogic,g12a-pdm", 1333 "amlogic,axg-pdm"; 1334 reg = <0x0 0x40000 0x0 0x34>; 1335 #sound-dai-cells = <0>; 1336 sound-name-prefix = "PDM"; 1337 clocks = <&clkc_audio AUD_CLKID_PDM>, 1338 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1339 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1340 clock-names = "pclk", "dclk", "sysclk"; 1341 status = "disabled"; 1342 }; 1343 1344 audio: bus@42000 { 1345 compatible = "simple-bus"; 1346 reg = <0x0 0x42000 0x0 0x2000>; 1347 #address-cells = <2>; 1348 #size-cells = <2>; 1349 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1350 1351 clkc_audio: clock-controller@0 { 1352 status = "disabled"; 1353 compatible = "amlogic,g12a-audio-clkc"; 1354 reg = <0x0 0x0 0x0 0xb4>; 1355 #clock-cells = <1>; 1356 1357 clocks = <&clkc CLKID_AUDIO>, 1358 <&clkc CLKID_MPLL0>, 1359 <&clkc CLKID_MPLL1>, 1360 <&clkc CLKID_MPLL2>, 1361 <&clkc CLKID_MPLL3>, 1362 <&clkc CLKID_HIFI_PLL>, 1363 <&clkc CLKID_FCLK_DIV3>, 1364 <&clkc CLKID_FCLK_DIV4>, 1365 <&clkc CLKID_GP0_PLL>; 1366 clock-names = "pclk", 1367 "mst_in0", 1368 "mst_in1", 1369 "mst_in2", 1370 "mst_in3", 1371 "mst_in4", 1372 "mst_in5", 1373 "mst_in6", 1374 "mst_in7"; 1375 1376 resets = <&reset RESET_AUDIO>; 1377 }; 1378 1379 toddr_a: audio-controller@100 { 1380 compatible = "amlogic,g12a-toddr", 1381 "amlogic,axg-toddr"; 1382 reg = <0x0 0x100 0x0 0x1c>; 1383 #sound-dai-cells = <0>; 1384 sound-name-prefix = "TODDR_A"; 1385 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1386 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1387 resets = <&arb AXG_ARB_TODDR_A>; 1388 status = "disabled"; 1389 }; 1390 1391 toddr_b: audio-controller@140 { 1392 compatible = "amlogic,g12a-toddr", 1393 "amlogic,axg-toddr"; 1394 reg = <0x0 0x140 0x0 0x1c>; 1395 #sound-dai-cells = <0>; 1396 sound-name-prefix = "TODDR_B"; 1397 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1398 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1399 resets = <&arb AXG_ARB_TODDR_B>; 1400 status = "disabled"; 1401 }; 1402 1403 toddr_c: audio-controller@180 { 1404 compatible = "amlogic,g12a-toddr", 1405 "amlogic,axg-toddr"; 1406 reg = <0x0 0x180 0x0 0x1c>; 1407 #sound-dai-cells = <0>; 1408 sound-name-prefix = "TODDR_C"; 1409 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1410 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1411 resets = <&arb AXG_ARB_TODDR_C>; 1412 status = "disabled"; 1413 }; 1414 1415 frddr_a: audio-controller@1c0 { 1416 compatible = "amlogic,g12a-frddr", 1417 "amlogic,axg-frddr"; 1418 reg = <0x0 0x1c0 0x0 0x1c>; 1419 #sound-dai-cells = <0>; 1420 sound-name-prefix = "FRDDR_A"; 1421 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1422 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1423 resets = <&arb AXG_ARB_FRDDR_A>; 1424 status = "disabled"; 1425 }; 1426 1427 frddr_b: audio-controller@200 { 1428 compatible = "amlogic,g12a-frddr", 1429 "amlogic,axg-frddr"; 1430 reg = <0x0 0x200 0x0 0x1c>; 1431 #sound-dai-cells = <0>; 1432 sound-name-prefix = "FRDDR_B"; 1433 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1434 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1435 resets = <&arb AXG_ARB_FRDDR_B>; 1436 status = "disabled"; 1437 }; 1438 1439 frddr_c: audio-controller@240 { 1440 compatible = "amlogic,g12a-frddr", 1441 "amlogic,axg-frddr"; 1442 reg = <0x0 0x240 0x0 0x1c>; 1443 #sound-dai-cells = <0>; 1444 sound-name-prefix = "FRDDR_C"; 1445 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1446 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1447 resets = <&arb AXG_ARB_FRDDR_C>; 1448 status = "disabled"; 1449 }; 1450 1451 arb: reset-controller@280 { 1452 status = "disabled"; 1453 compatible = "amlogic,meson-axg-audio-arb"; 1454 reg = <0x0 0x280 0x0 0x4>; 1455 #reset-cells = <1>; 1456 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1457 }; 1458 1459 tdmin_a: audio-controller@300 { 1460 compatible = "amlogic,g12a-tdmin", 1461 "amlogic,axg-tdmin"; 1462 reg = <0x0 0x300 0x0 0x40>; 1463 sound-name-prefix = "TDMIN_A"; 1464 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1465 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1466 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1467 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1468 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1469 clock-names = "pclk", "sclk", "sclk_sel", 1470 "lrclk", "lrclk_sel"; 1471 status = "disabled"; 1472 }; 1473 1474 tdmin_b: audio-controller@340 { 1475 compatible = "amlogic,g12a-tdmin", 1476 "amlogic,axg-tdmin"; 1477 reg = <0x0 0x340 0x0 0x40>; 1478 sound-name-prefix = "TDMIN_B"; 1479 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1480 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1481 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1482 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1483 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1484 clock-names = "pclk", "sclk", "sclk_sel", 1485 "lrclk", "lrclk_sel"; 1486 status = "disabled"; 1487 }; 1488 1489 tdmin_c: audio-controller@380 { 1490 compatible = "amlogic,g12a-tdmin", 1491 "amlogic,axg-tdmin"; 1492 reg = <0x0 0x380 0x0 0x40>; 1493 sound-name-prefix = "TDMIN_C"; 1494 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1495 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1496 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1497 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1498 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1499 clock-names = "pclk", "sclk", "sclk_sel", 1500 "lrclk", "lrclk_sel"; 1501 status = "disabled"; 1502 }; 1503 1504 tdmin_lb: audio-controller@3c0 { 1505 compatible = "amlogic,g12a-tdmin", 1506 "amlogic,axg-tdmin"; 1507 reg = <0x0 0x3c0 0x0 0x40>; 1508 sound-name-prefix = "TDMIN_LB"; 1509 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1510 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1511 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1512 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1513 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1514 clock-names = "pclk", "sclk", "sclk_sel", 1515 "lrclk", "lrclk_sel"; 1516 status = "disabled"; 1517 }; 1518 1519 spdifout: audio-controller@480 { 1520 compatible = "amlogic,g12a-spdifout", 1521 "amlogic,axg-spdifout"; 1522 reg = <0x0 0x480 0x0 0x50>; 1523 #sound-dai-cells = <0>; 1524 sound-name-prefix = "SPDIFOUT"; 1525 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1526 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1527 clock-names = "pclk", "mclk"; 1528 status = "disabled"; 1529 }; 1530 1531 tdmout_a: audio-controller@500 { 1532 compatible = "amlogic,g12a-tdmout"; 1533 reg = <0x0 0x500 0x0 0x40>; 1534 sound-name-prefix = "TDMOUT_A"; 1535 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1536 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1537 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1538 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1539 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1540 clock-names = "pclk", "sclk", "sclk_sel", 1541 "lrclk", "lrclk_sel"; 1542 status = "disabled"; 1543 }; 1544 1545 tdmout_b: audio-controller@540 { 1546 compatible = "amlogic,g12a-tdmout"; 1547 reg = <0x0 0x540 0x0 0x40>; 1548 sound-name-prefix = "TDMOUT_B"; 1549 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1550 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1551 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1552 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1553 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1554 clock-names = "pclk", "sclk", "sclk_sel", 1555 "lrclk", "lrclk_sel"; 1556 status = "disabled"; 1557 }; 1558 1559 tdmout_c: audio-controller@580 { 1560 compatible = "amlogic,g12a-tdmout"; 1561 reg = <0x0 0x580 0x0 0x40>; 1562 sound-name-prefix = "TDMOUT_C"; 1563 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1564 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1565 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1566 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1567 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1568 clock-names = "pclk", "sclk", "sclk_sel", 1569 "lrclk", "lrclk_sel"; 1570 status = "disabled"; 1571 }; 1572 1573 spdifout_b: audio-controller@680 { 1574 compatible = "amlogic,g12a-spdifout", 1575 "amlogic,axg-spdifout"; 1576 reg = <0x0 0x680 0x0 0x50>; 1577 #sound-dai-cells = <0>; 1578 sound-name-prefix = "SPDIFOUT_B"; 1579 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1580 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1581 clock-names = "pclk", "mclk"; 1582 status = "disabled"; 1583 }; 1584 }; 1585 1586 usb3_pcie_phy: phy@46000 { 1587 compatible = "amlogic,g12a-usb3-pcie-phy"; 1588 reg = <0x0 0x46000 0x0 0x2000>; 1589 clocks = <&clkc CLKID_PCIE_PLL>; 1590 clock-names = "ref_clk"; 1591 resets = <&reset RESET_PCIE_PHY>; 1592 reset-names = "phy"; 1593 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1594 assigned-clock-rates = <100000000>; 1595 #phy-cells = <1>; 1596 }; 1597 }; 1598 1599 aobus: bus@ff800000 { 1600 compatible = "simple-bus"; 1601 reg = <0x0 0xff800000 0x0 0x100000>; 1602 #address-cells = <2>; 1603 #size-cells = <2>; 1604 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1605 1606 rti: sys-ctrl@0 { 1607 compatible = "amlogic,meson-gx-ao-sysctrl", 1608 "simple-mfd", "syscon"; 1609 reg = <0x0 0x0 0x0 0x100>; 1610 #address-cells = <2>; 1611 #size-cells = <2>; 1612 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1613 1614 clkc_AO: clock-controller { 1615 compatible = "amlogic,meson-g12a-aoclkc"; 1616 #clock-cells = <1>; 1617 #reset-cells = <1>; 1618 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1619 clock-names = "xtal", "mpeg-clk"; 1620 }; 1621 1622 pwrc_vpu: power-controller-vpu { 1623 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1624 #power-domain-cells = <0>; 1625 amlogic,hhi-sysctrl = <&hhi>; 1626 resets = <&reset RESET_VIU>, 1627 <&reset RESET_VENC>, 1628 <&reset RESET_VCBUS>, 1629 <&reset RESET_BT656>, 1630 <&reset RESET_RDMA>, 1631 <&reset RESET_VENCI>, 1632 <&reset RESET_VENCP>, 1633 <&reset RESET_VDAC>, 1634 <&reset RESET_VDI6>, 1635 <&reset RESET_VENCL>, 1636 <&reset RESET_VID_LOCK>; 1637 clocks = <&clkc CLKID_VPU>, 1638 <&clkc CLKID_VAPB>; 1639 clock-names = "vpu", "vapb"; 1640 /* 1641 * VPU clocking is provided by two identical clock paths 1642 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1643 * free mux to safely change frequency while running. 1644 * Same for VAPB but with a final gate after the glitch free mux. 1645 */ 1646 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1647 <&clkc CLKID_VPU_0>, 1648 <&clkc CLKID_VPU>, /* Glitch free mux */ 1649 <&clkc CLKID_VAPB_0_SEL>, 1650 <&clkc CLKID_VAPB_0>, 1651 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1652 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1653 <0>, /* Do Nothing */ 1654 <&clkc CLKID_VPU_0>, 1655 <&clkc CLKID_FCLK_DIV4>, 1656 <0>, /* Do Nothing */ 1657 <&clkc CLKID_VAPB_0>; 1658 assigned-clock-rates = <0>, /* Do Nothing */ 1659 <666666666>, 1660 <0>, /* Do Nothing */ 1661 <0>, /* Do Nothing */ 1662 <250000000>, 1663 <0>; /* Do Nothing */ 1664 }; 1665 1666 ao_pinctrl: pinctrl@14 { 1667 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1668 #address-cells = <2>; 1669 #size-cells = <2>; 1670 ranges; 1671 1672 gpio_ao: bank@14 { 1673 reg = <0x0 0x14 0x0 0x8>, 1674 <0x0 0x1c 0x0 0x8>, 1675 <0x0 0x24 0x0 0x14>; 1676 reg-names = "mux", 1677 "ds", 1678 "gpio"; 1679 gpio-controller; 1680 #gpio-cells = <2>; 1681 gpio-ranges = <&ao_pinctrl 0 0 15>; 1682 }; 1683 1684 i2c_ao_sck_pins: i2c_ao_sck_pins { 1685 mux { 1686 groups = "i2c_ao_sck"; 1687 function = "i2c_ao"; 1688 bias-disable; 1689 drive-strength-microamp = <3000>; 1690 }; 1691 }; 1692 1693 i2c_ao_sda_pins: i2c_ao_sda { 1694 mux { 1695 groups = "i2c_ao_sda"; 1696 function = "i2c_ao"; 1697 bias-disable; 1698 drive-strength-microamp = <3000>; 1699 }; 1700 }; 1701 1702 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1703 mux { 1704 groups = "i2c_ao_sck_e"; 1705 function = "i2c_ao"; 1706 bias-disable; 1707 drive-strength-microamp = <3000>; 1708 }; 1709 }; 1710 1711 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1712 mux { 1713 groups = "i2c_ao_sda_e"; 1714 function = "i2c_ao"; 1715 bias-disable; 1716 drive-strength-microamp = <3000>; 1717 }; 1718 }; 1719 1720 mclk0_ao_pins: mclk0-ao { 1721 mux { 1722 groups = "mclk0_ao"; 1723 function = "mclk0_ao"; 1724 bias-disable; 1725 drive-strength-microamp = <3000>; 1726 }; 1727 }; 1728 1729 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1730 mux { 1731 groups = "tdm_ao_b_din0"; 1732 function = "tdm_ao_b"; 1733 bias-disable; 1734 }; 1735 }; 1736 1737 spdif_ao_out_pins: spdif-ao-out { 1738 mux { 1739 groups = "spdif_ao_out"; 1740 function = "spdif_ao_out"; 1741 drive-strength-microamp = <500>; 1742 bias-disable; 1743 }; 1744 }; 1745 1746 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1747 mux { 1748 groups = "tdm_ao_b_din1"; 1749 function = "tdm_ao_b"; 1750 bias-disable; 1751 }; 1752 }; 1753 1754 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1755 mux { 1756 groups = "tdm_ao_b_din2"; 1757 function = "tdm_ao_b"; 1758 bias-disable; 1759 }; 1760 }; 1761 1762 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1763 mux { 1764 groups = "tdm_ao_b_dout0"; 1765 function = "tdm_ao_b"; 1766 bias-disable; 1767 drive-strength-microamp = <3000>; 1768 }; 1769 }; 1770 1771 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1772 mux { 1773 groups = "tdm_ao_b_dout1"; 1774 function = "tdm_ao_b"; 1775 bias-disable; 1776 drive-strength-microamp = <3000>; 1777 }; 1778 }; 1779 1780 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1781 mux { 1782 groups = "tdm_ao_b_dout2"; 1783 function = "tdm_ao_b"; 1784 bias-disable; 1785 drive-strength-microamp = <3000>; 1786 }; 1787 }; 1788 1789 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1790 mux { 1791 groups = "tdm_ao_b_fs"; 1792 function = "tdm_ao_b"; 1793 bias-disable; 1794 drive-strength-microamp = <3000>; 1795 }; 1796 }; 1797 1798 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1799 mux { 1800 groups = "tdm_ao_b_sclk"; 1801 function = "tdm_ao_b"; 1802 bias-disable; 1803 drive-strength-microamp = <3000>; 1804 }; 1805 }; 1806 1807 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1808 mux { 1809 groups = "tdm_ao_b_slv_fs"; 1810 function = "tdm_ao_b"; 1811 bias-disable; 1812 }; 1813 }; 1814 1815 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1816 mux { 1817 groups = "tdm_ao_b_slv_sclk"; 1818 function = "tdm_ao_b"; 1819 bias-disable; 1820 }; 1821 }; 1822 1823 uart_ao_a_pins: uart-a-ao { 1824 mux { 1825 groups = "uart_ao_a_tx", 1826 "uart_ao_a_rx"; 1827 function = "uart_ao_a"; 1828 bias-disable; 1829 }; 1830 }; 1831 1832 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1833 mux { 1834 groups = "uart_ao_a_cts", 1835 "uart_ao_a_rts"; 1836 function = "uart_ao_a"; 1837 bias-disable; 1838 }; 1839 }; 1840 1841 pwm_ao_a_pins: pwm-ao-a { 1842 mux { 1843 groups = "pwm_ao_a"; 1844 function = "pwm_ao_a"; 1845 bias-disable; 1846 }; 1847 }; 1848 1849 pwm_ao_b_pins: pwm-ao-b { 1850 mux { 1851 groups = "pwm_ao_b"; 1852 function = "pwm_ao_b"; 1853 bias-disable; 1854 }; 1855 }; 1856 1857 pwm_ao_c_4_pins: pwm-ao-c-4 { 1858 mux { 1859 groups = "pwm_ao_c_4"; 1860 function = "pwm_ao_c"; 1861 bias-disable; 1862 }; 1863 }; 1864 1865 pwm_ao_c_6_pins: pwm-ao-c-6 { 1866 mux { 1867 groups = "pwm_ao_c_6"; 1868 function = "pwm_ao_c"; 1869 bias-disable; 1870 }; 1871 }; 1872 1873 pwm_ao_d_5_pins: pwm-ao-d-5 { 1874 mux { 1875 groups = "pwm_ao_d_5"; 1876 function = "pwm_ao_d"; 1877 bias-disable; 1878 }; 1879 }; 1880 1881 pwm_ao_d_10_pins: pwm-ao-d-10 { 1882 mux { 1883 groups = "pwm_ao_d_10"; 1884 function = "pwm_ao_d"; 1885 bias-disable; 1886 }; 1887 }; 1888 1889 pwm_ao_d_e_pins: pwm-ao-d-e { 1890 mux { 1891 groups = "pwm_ao_d_e"; 1892 function = "pwm_ao_d"; 1893 }; 1894 }; 1895 1896 remote_input_ao_pins: remote-input-ao { 1897 mux { 1898 groups = "remote_ao_input"; 1899 function = "remote_ao_input"; 1900 bias-disable; 1901 }; 1902 }; 1903 }; 1904 }; 1905 1906 cec_AO: cec@100 { 1907 compatible = "amlogic,meson-gx-ao-cec"; 1908 reg = <0x0 0x00100 0x0 0x14>; 1909 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 1910 clocks = <&clkc_AO CLKID_AO_CEC>; 1911 clock-names = "core"; 1912 status = "disabled"; 1913 }; 1914 1915 sec_AO: ao-secure@140 { 1916 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1917 reg = <0x0 0x140 0x0 0x140>; 1918 amlogic,has-chip-id; 1919 }; 1920 1921 cecb_AO: cec@280 { 1922 compatible = "amlogic,meson-g12a-ao-cec"; 1923 reg = <0x0 0x00280 0x0 0x1c>; 1924 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1925 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 1926 clock-names = "oscin"; 1927 status = "disabled"; 1928 }; 1929 1930 pwm_AO_cd: pwm@2000 { 1931 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 1932 reg = <0x0 0x2000 0x0 0x20>; 1933 #pwm-cells = <3>; 1934 status = "disabled"; 1935 }; 1936 1937 uart_AO: serial@3000 { 1938 compatible = "amlogic,meson-gx-uart", 1939 "amlogic,meson-ao-uart"; 1940 reg = <0x0 0x3000 0x0 0x18>; 1941 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1942 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 1943 clock-names = "xtal", "pclk", "baud"; 1944 status = "disabled"; 1945 }; 1946 1947 uart_AO_B: serial@4000 { 1948 compatible = "amlogic,meson-gx-uart", 1949 "amlogic,meson-ao-uart"; 1950 reg = <0x0 0x4000 0x0 0x18>; 1951 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1952 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1953 clock-names = "xtal", "pclk", "baud"; 1954 status = "disabled"; 1955 }; 1956 1957 i2c_AO: i2c@5000 { 1958 compatible = "amlogic,meson-axg-i2c"; 1959 status = "disabled"; 1960 reg = <0x0 0x05000 0x0 0x20>; 1961 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 clocks = <&clkc CLKID_I2C>; 1965 }; 1966 1967 pwm_AO_ab: pwm@7000 { 1968 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 1969 reg = <0x0 0x7000 0x0 0x20>; 1970 #pwm-cells = <3>; 1971 status = "disabled"; 1972 }; 1973 1974 ir: ir@8000 { 1975 compatible = "amlogic,meson-gxbb-ir"; 1976 reg = <0x0 0x8000 0x0 0x20>; 1977 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1978 status = "disabled"; 1979 }; 1980 1981 saradc: adc@9000 { 1982 compatible = "amlogic,meson-g12a-saradc", 1983 "amlogic,meson-saradc"; 1984 reg = <0x0 0x9000 0x0 0x48>; 1985 #io-channel-cells = <1>; 1986 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 1987 clocks = <&xtal>, 1988 <&clkc_AO CLKID_AO_SAR_ADC>, 1989 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1990 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1991 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1992 status = "disabled"; 1993 }; 1994 }; 1995 1996 vpu: vpu@ff900000 { 1997 compatible = "amlogic,meson-g12a-vpu"; 1998 reg = <0x0 0xff900000 0x0 0x100000>, 1999 <0x0 0xff63c000 0x0 0x1000>; 2000 reg-names = "vpu", "hhi"; 2001 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2002 #address-cells = <1>; 2003 #size-cells = <0>; 2004 amlogic,canvas = <&canvas>; 2005 power-domains = <&pwrc_vpu>; 2006 2007 /* CVBS VDAC output port */ 2008 cvbs_vdac_port: port@0 { 2009 reg = <0>; 2010 }; 2011 2012 /* HDMI-TX output port */ 2013 hdmi_tx_port: port@1 { 2014 reg = <1>; 2015 2016 hdmi_tx_out: endpoint { 2017 remote-endpoint = <&hdmi_tx_in>; 2018 }; 2019 }; 2020 }; 2021 2022 gic: interrupt-controller@ffc01000 { 2023 compatible = "arm,gic-400"; 2024 reg = <0x0 0xffc01000 0 0x1000>, 2025 <0x0 0xffc02000 0 0x2000>, 2026 <0x0 0xffc04000 0 0x2000>, 2027 <0x0 0xffc06000 0 0x2000>; 2028 interrupt-controller; 2029 interrupts = <GIC_PPI 9 2030 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2031 #interrupt-cells = <3>; 2032 #address-cells = <0>; 2033 }; 2034 2035 cbus: bus@ffd00000 { 2036 compatible = "simple-bus"; 2037 reg = <0x0 0xffd00000 0x0 0x100000>; 2038 #address-cells = <2>; 2039 #size-cells = <2>; 2040 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2041 2042 reset: reset-controller@1004 { 2043 compatible = "amlogic,meson-g12a-reset", 2044 "amlogic,meson-axg-reset"; 2045 reg = <0x0 0x1004 0x0 0x9c>; 2046 #reset-cells = <1>; 2047 }; 2048 2049 pwm_ef: pwm@19000 { 2050 compatible = "amlogic,meson-g12a-ee-pwm"; 2051 reg = <0x0 0x19000 0x0 0x20>; 2052 #pwm-cells = <3>; 2053 status = "disabled"; 2054 }; 2055 2056 pwm_cd: pwm@1a000 { 2057 compatible = "amlogic,meson-g12a-ee-pwm"; 2058 reg = <0x0 0x1a000 0x0 0x20>; 2059 #pwm-cells = <3>; 2060 status = "disabled"; 2061 }; 2062 2063 pwm_ab: pwm@1b000 { 2064 compatible = "amlogic,meson-g12a-ee-pwm"; 2065 reg = <0x0 0x1b000 0x0 0x20>; 2066 #pwm-cells = <3>; 2067 status = "disabled"; 2068 }; 2069 2070 i2c3: i2c@1c000 { 2071 compatible = "amlogic,meson-axg-i2c"; 2072 status = "disabled"; 2073 reg = <0x0 0x1c000 0x0 0x20>; 2074 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2075 #address-cells = <1>; 2076 #size-cells = <0>; 2077 clocks = <&clkc CLKID_I2C>; 2078 }; 2079 2080 i2c2: i2c@1d000 { 2081 compatible = "amlogic,meson-axg-i2c"; 2082 status = "disabled"; 2083 reg = <0x0 0x1d000 0x0 0x20>; 2084 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2085 #address-cells = <1>; 2086 #size-cells = <0>; 2087 clocks = <&clkc CLKID_I2C>; 2088 }; 2089 2090 i2c1: i2c@1e000 { 2091 compatible = "amlogic,meson-axg-i2c"; 2092 status = "disabled"; 2093 reg = <0x0 0x1e000 0x0 0x20>; 2094 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2095 #address-cells = <1>; 2096 #size-cells = <0>; 2097 clocks = <&clkc CLKID_I2C>; 2098 }; 2099 2100 i2c0: i2c@1f000 { 2101 compatible = "amlogic,meson-axg-i2c"; 2102 status = "disabled"; 2103 reg = <0x0 0x1f000 0x0 0x20>; 2104 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2105 #address-cells = <1>; 2106 #size-cells = <0>; 2107 clocks = <&clkc CLKID_I2C>; 2108 }; 2109 2110 clk_msr: clock-measure@18000 { 2111 compatible = "amlogic,meson-g12a-clk-measure"; 2112 reg = <0x0 0x18000 0x0 0x10>; 2113 }; 2114 2115 uart_C: serial@22000 { 2116 compatible = "amlogic,meson-gx-uart"; 2117 reg = <0x0 0x22000 0x0 0x18>; 2118 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2119 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2120 clock-names = "xtal", "pclk", "baud"; 2121 status = "disabled"; 2122 }; 2123 2124 uart_B: serial@23000 { 2125 compatible = "amlogic,meson-gx-uart"; 2126 reg = <0x0 0x23000 0x0 0x18>; 2127 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2128 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2129 clock-names = "xtal", "pclk", "baud"; 2130 status = "disabled"; 2131 }; 2132 2133 uart_A: serial@24000 { 2134 compatible = "amlogic,meson-gx-uart"; 2135 reg = <0x0 0x24000 0x0 0x18>; 2136 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2137 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2138 clock-names = "xtal", "pclk", "baud"; 2139 status = "disabled"; 2140 }; 2141 }; 2142 2143 sd_emmc_b: sd@ffe05000 { 2144 compatible = "amlogic,meson-axg-mmc"; 2145 reg = <0x0 0xffe05000 0x0 0x800>; 2146 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2147 status = "disabled"; 2148 clocks = <&clkc CLKID_SD_EMMC_B>, 2149 <&clkc CLKID_SD_EMMC_B_CLK0>, 2150 <&clkc CLKID_FCLK_DIV2>; 2151 clock-names = "core", "clkin0", "clkin1"; 2152 resets = <&reset RESET_SD_EMMC_B>; 2153 }; 2154 2155 sd_emmc_c: mmc@ffe07000 { 2156 compatible = "amlogic,meson-axg-mmc"; 2157 reg = <0x0 0xffe07000 0x0 0x800>; 2158 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2159 status = "disabled"; 2160 clocks = <&clkc CLKID_SD_EMMC_C>, 2161 <&clkc CLKID_SD_EMMC_C_CLK0>, 2162 <&clkc CLKID_FCLK_DIV2>; 2163 clock-names = "core", "clkin0", "clkin1"; 2164 resets = <&reset RESET_SD_EMMC_C>; 2165 }; 2166 2167 usb: usb@ffe09000 { 2168 status = "disabled"; 2169 compatible = "amlogic,meson-g12a-usb-ctrl"; 2170 reg = <0x0 0xffe09000 0x0 0xa0>; 2171 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2172 #address-cells = <2>; 2173 #size-cells = <2>; 2174 ranges; 2175 2176 clocks = <&clkc CLKID_USB>; 2177 resets = <&reset RESET_USB>; 2178 2179 dr_mode = "otg"; 2180 2181 phys = <&usb2_phy0>, <&usb2_phy1>, 2182 <&usb3_pcie_phy PHY_TYPE_USB3>; 2183 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2184 2185 dwc2: usb@ff400000 { 2186 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2187 reg = <0x0 0xff400000 0x0 0x40000>; 2188 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2189 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2190 clock-names = "ddr"; 2191 phys = <&usb2_phy1>; 2192 dr_mode = "peripheral"; 2193 g-rx-fifo-size = <192>; 2194 g-np-tx-fifo-size = <128>; 2195 g-tx-fifo-size = <128 128 16 16 16>; 2196 }; 2197 2198 dwc3: usb@ff500000 { 2199 compatible = "snps,dwc3"; 2200 reg = <0x0 0xff500000 0x0 0x100000>; 2201 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2202 dr_mode = "host"; 2203 snps,dis_u2_susphy_quirk; 2204 snps,quirk-frame-length-adjustment; 2205 }; 2206 }; 2207 2208 mali: gpu@ffe40000 { 2209 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2210 reg = <0x0 0xffe40000 0x0 0x40000>; 2211 interrupt-parent = <&gic>; 2212 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2215 interrupt-names = "gpu", "mmu", "job"; 2216 clocks = <&clkc CLKID_MALI>; 2217 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2218 2219 /* 2220 * Mali clocking is provided by two identical clock paths 2221 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2222 * free mux to safely change frequency while running. 2223 */ 2224 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2225 <&clkc CLKID_MALI_0>, 2226 <&clkc CLKID_MALI>; /* Glitch free mux */ 2227 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2228 <0>, /* Do Nothing */ 2229 <&clkc CLKID_MALI_0>; 2230 assigned-clock-rates = <0>, /* Do Nothing */ 2231 <800000000>, 2232 <0>; /* Do Nothing */ 2233 }; 2234 }; 2235 2236 timer { 2237 compatible = "arm,armv8-timer"; 2238 interrupts = <GIC_PPI 13 2239 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2240 <GIC_PPI 14 2241 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2242 <GIC_PPI 11 2243 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2244 <GIC_PPI 10 2245 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2246 }; 2247 2248 xtal: xtal-clk { 2249 compatible = "fixed-clock"; 2250 clock-frequency = <24000000>; 2251 clock-output-names = "xtal"; 2252 #clock-cells = <0>; 2253 }; 2254 2255}; 2256