1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 15 16/ { 17 compatible = "amlogic,g12a"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 cpus { 57 #address-cells = <0x2>; 58 #size-cells = <0x0>; 59 60 cpu0: cpu@0 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x0 0x0>; 64 enable-method = "psci"; 65 next-level-cache = <&l2>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 reg = <0x0 0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2>; 82 }; 83 84 cpu3: cpu@3 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x0 0x3>; 88 enable-method = "psci"; 89 next-level-cache = <&l2>; 90 }; 91 92 l2: l2-cache0 { 93 compatible = "cache"; 94 }; 95 }; 96 97 efuse: efuse { 98 compatible = "amlogic,meson-gxbb-efuse"; 99 clocks = <&clkc CLKID_EFUSE>; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 read-only; 103 }; 104 105 psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 110 reserved-memory { 111 #address-cells = <2>; 112 #size-cells = <2>; 113 ranges; 114 115 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 116 secmon_reserved: secmon@5000000 { 117 reg = <0x0 0x05000000 0x0 0x300000>; 118 no-map; 119 }; 120 121 linux,cma { 122 compatible = "shared-dma-pool"; 123 reusable; 124 size = <0x0 0x10000000>; 125 alignment = <0x0 0x400000>; 126 linux,cma-default; 127 }; 128 }; 129 130 sm: secure-monitor { 131 compatible = "amlogic,meson-gxbb-sm"; 132 }; 133 134 soc { 135 compatible = "simple-bus"; 136 #address-cells = <2>; 137 #size-cells = <2>; 138 ranges; 139 140 apb: bus@ff600000 { 141 compatible = "simple-bus"; 142 reg = <0x0 0xff600000 0x0 0x200000>; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 146 147 hdmi_tx: hdmi-tx@0 { 148 compatible = "amlogic,meson-g12a-dw-hdmi"; 149 reg = <0x0 0x0 0x0 0x10000>; 150 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 151 resets = <&reset RESET_HDMITX_CAPB3>, 152 <&reset RESET_HDMITX_PHY>, 153 <&reset RESET_HDMITX>; 154 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 155 clocks = <&clkc CLKID_HDMI>, 156 <&clkc CLKID_HTX_PCLK>, 157 <&clkc CLKID_VPU_INTR>; 158 clock-names = "isfr", "iahb", "venci"; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 status = "disabled"; 162 163 /* VPU VENC Input */ 164 hdmi_tx_venc_port: port@0 { 165 reg = <0>; 166 167 hdmi_tx_in: endpoint { 168 remote-endpoint = <&hdmi_tx_out>; 169 }; 170 }; 171 172 /* TMDS Output */ 173 hdmi_tx_tmds_port: port@1 { 174 reg = <1>; 175 }; 176 }; 177 178 periphs: bus@34400 { 179 compatible = "simple-bus"; 180 reg = <0x0 0x34400 0x0 0x400>; 181 #address-cells = <2>; 182 #size-cells = <2>; 183 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 184 185 periphs_pinctrl: pinctrl@40 { 186 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges; 190 191 gpio: bank@40 { 192 reg = <0x0 0x40 0x0 0x4c>, 193 <0x0 0xe8 0x0 0x18>, 194 <0x0 0x120 0x0 0x18>, 195 <0x0 0x2c0 0x0 0x40>, 196 <0x0 0x340 0x0 0x1c>; 197 reg-names = "gpio", 198 "pull", 199 "pull-enable", 200 "mux", 201 "ds"; 202 gpio-controller; 203 #gpio-cells = <2>; 204 gpio-ranges = <&periphs_pinctrl 0 0 86>; 205 }; 206 207 cec_ao_a_h_pins: cec_ao_a_h { 208 mux { 209 groups = "cec_ao_a_h"; 210 function = "cec_ao_a_h"; 211 bias-disable; 212 }; 213 }; 214 215 cec_ao_b_h_pins: cec_ao_b_h { 216 mux { 217 groups = "cec_ao_b_h"; 218 function = "cec_ao_b_h"; 219 bias-disable; 220 }; 221 }; 222 223 emmc_pins: emmc { 224 mux-0 { 225 groups = "emmc_nand_d0", 226 "emmc_nand_d1", 227 "emmc_nand_d2", 228 "emmc_nand_d3", 229 "emmc_nand_d4", 230 "emmc_nand_d5", 231 "emmc_nand_d6", 232 "emmc_nand_d7", 233 "emmc_cmd"; 234 function = "emmc"; 235 bias-pull-up; 236 drive-strength-microamp = <4000>; 237 }; 238 239 mux-1 { 240 groups = "emmc_clk"; 241 function = "emmc"; 242 bias-disable; 243 drive-strength-microamp = <4000>; 244 }; 245 }; 246 247 emmc_ds_pins: emmc-ds { 248 mux { 249 groups = "emmc_nand_ds"; 250 function = "emmc"; 251 bias-pull-down; 252 drive-strength-microamp = <4000>; 253 }; 254 }; 255 256 emmc_clk_gate_pins: emmc_clk_gate { 257 mux { 258 groups = "BOOT_8"; 259 function = "gpio_periphs"; 260 bias-pull-down; 261 drive-strength-microamp = <4000>; 262 }; 263 }; 264 265 hdmitx_ddc_pins: hdmitx_ddc { 266 mux { 267 groups = "hdmitx_sda", 268 "hdmitx_sck"; 269 function = "hdmitx"; 270 bias-disable; 271 }; 272 }; 273 274 hdmitx_hpd_pins: hdmitx_hpd { 275 mux { 276 groups = "hdmitx_hpd_in"; 277 function = "hdmitx"; 278 bias-disable; 279 }; 280 }; 281 282 283 i2c0_sda_c_pins: i2c0-sda-c { 284 mux { 285 groups = "i2c0_sda_c"; 286 function = "i2c0"; 287 bias-disable; 288 drive-strength-microamp = <3000>; 289 290 }; 291 }; 292 293 i2c0_sck_c_pins: i2c0-sck-c { 294 mux { 295 groups = "i2c0_sck_c"; 296 function = "i2c0"; 297 bias-disable; 298 drive-strength-microamp = <3000>; 299 }; 300 }; 301 302 i2c0_sda_z0_pins: i2c0-sda-z0 { 303 mux { 304 groups = "i2c0_sda_z0"; 305 function = "i2c0"; 306 bias-disable; 307 drive-strength-microamp = <3000>; 308 }; 309 }; 310 311 i2c0_sck_z1_pins: i2c0-sck-z1 { 312 mux { 313 groups = "i2c0_sck_z1"; 314 function = "i2c0"; 315 bias-disable; 316 drive-strength-microamp = <3000>; 317 }; 318 }; 319 320 i2c0_sda_z7_pins: i2c0-sda-z7 { 321 mux { 322 groups = "i2c0_sda_z7"; 323 function = "i2c0"; 324 bias-disable; 325 drive-strength-microamp = <3000>; 326 }; 327 }; 328 329 i2c0_sda_z8_pins: i2c0-sda-z8 { 330 mux { 331 groups = "i2c0_sda_z8"; 332 function = "i2c0"; 333 bias-disable; 334 drive-strength-microamp = <3000>; 335 }; 336 }; 337 338 i2c1_sda_x_pins: i2c1-sda-x { 339 mux { 340 groups = "i2c1_sda_x"; 341 function = "i2c1"; 342 bias-disable; 343 drive-strength-microamp = <3000>; 344 }; 345 }; 346 347 i2c1_sck_x_pins: i2c1-sck-x { 348 mux { 349 groups = "i2c1_sck_x"; 350 function = "i2c1"; 351 bias-disable; 352 drive-strength-microamp = <3000>; 353 }; 354 }; 355 356 i2c1_sda_h2_pins: i2c1-sda-h2 { 357 mux { 358 groups = "i2c1_sda_h2"; 359 function = "i2c1"; 360 bias-disable; 361 drive-strength-microamp = <3000>; 362 }; 363 }; 364 365 i2c1_sck_h3_pins: i2c1-sck-h3 { 366 mux { 367 groups = "i2c1_sck_h3"; 368 function = "i2c1"; 369 bias-disable; 370 drive-strength-microamp = <3000>; 371 }; 372 }; 373 374 i2c1_sda_h6_pins: i2c1-sda-h6 { 375 mux { 376 groups = "i2c1_sda_h6"; 377 function = "i2c1"; 378 bias-disable; 379 drive-strength-microamp = <3000>; 380 }; 381 }; 382 383 i2c1_sck_h7_pins: i2c1-sck-h7 { 384 mux { 385 groups = "i2c1_sck_h7"; 386 function = "i2c1"; 387 bias-disable; 388 drive-strength-microamp = <3000>; 389 }; 390 }; 391 392 i2c2_sda_x_pins: i2c2-sda-x { 393 mux { 394 groups = "i2c2_sda_x"; 395 function = "i2c2"; 396 bias-disable; 397 drive-strength-microamp = <3000>; 398 }; 399 }; 400 401 i2c2_sck_x_pins: i2c2-sck-x { 402 mux { 403 groups = "i2c2_sck_x"; 404 function = "i2c2"; 405 bias-disable; 406 drive-strength-microamp = <3000>; 407 }; 408 }; 409 410 i2c2_sda_z_pins: i2c2-sda-z { 411 mux { 412 groups = "i2c2_sda_z"; 413 function = "i2c2"; 414 bias-disable; 415 drive-strength-microamp = <3000>; 416 }; 417 }; 418 419 i2c2_sck_z_pins: i2c2-sck-z { 420 mux { 421 groups = "i2c2_sck_z"; 422 function = "i2c2"; 423 bias-disable; 424 drive-strength-microamp = <3000>; 425 }; 426 }; 427 428 i2c3_sda_h_pins: i2c3-sda-h { 429 mux { 430 groups = "i2c3_sda_h"; 431 function = "i2c3"; 432 bias-disable; 433 drive-strength-microamp = <3000>; 434 }; 435 }; 436 437 i2c3_sck_h_pins: i2c3-sck-h { 438 mux { 439 groups = "i2c3_sck_h"; 440 function = "i2c3"; 441 bias-disable; 442 drive-strength-microamp = <3000>; 443 }; 444 }; 445 446 i2c3_sda_a_pins: i2c3-sda-a { 447 mux { 448 groups = "i2c3_sda_a"; 449 function = "i2c3"; 450 bias-disable; 451 drive-strength-microamp = <3000>; 452 }; 453 }; 454 455 i2c3_sck_a_pins: i2c3-sck-a { 456 mux { 457 groups = "i2c3_sck_a"; 458 function = "i2c3"; 459 bias-disable; 460 drive-strength-microamp = <3000>; 461 }; 462 }; 463 464 mclk0_a_pins: mclk0-a { 465 mux { 466 groups = "mclk0_a"; 467 function = "mclk0"; 468 bias-disable; 469 drive-strength-microamp = <3000>; 470 }; 471 }; 472 473 mclk1_a_pins: mclk1-a { 474 mux { 475 groups = "mclk1_a"; 476 function = "mclk1"; 477 bias-disable; 478 drive-strength-microamp = <3000>; 479 }; 480 }; 481 482 mclk1_x_pins: mclk1-x { 483 mux { 484 groups = "mclk1_x"; 485 function = "mclk1"; 486 bias-disable; 487 drive-strength-microamp = <3000>; 488 }; 489 }; 490 491 mclk1_z_pins: mclk1-z { 492 mux { 493 groups = "mclk1_z"; 494 function = "mclk1"; 495 bias-disable; 496 drive-strength-microamp = <3000>; 497 }; 498 }; 499 500 pwm_a_pins: pwm-a { 501 mux { 502 groups = "pwm_a"; 503 function = "pwm_a"; 504 bias-disable; 505 }; 506 }; 507 508 pwm_b_x7_pins: pwm-b-x7 { 509 mux { 510 groups = "pwm_b_x7"; 511 function = "pwm_b"; 512 bias-disable; 513 }; 514 }; 515 516 pwm_b_x19_pins: pwm-b-x19 { 517 mux { 518 groups = "pwm_b_x19"; 519 function = "pwm_b"; 520 bias-disable; 521 }; 522 }; 523 524 pwm_c_c_pins: pwm-c-c { 525 mux { 526 groups = "pwm_c_c"; 527 function = "pwm_c"; 528 bias-disable; 529 }; 530 }; 531 532 pwm_c_x5_pins: pwm-c-x5 { 533 mux { 534 groups = "pwm_c_x5"; 535 function = "pwm_c"; 536 bias-disable; 537 }; 538 }; 539 540 pwm_c_x8_pins: pwm-c-x8 { 541 mux { 542 groups = "pwm_c_x8"; 543 function = "pwm_c"; 544 bias-disable; 545 }; 546 }; 547 548 pwm_d_x3_pins: pwm-d-x3 { 549 mux { 550 groups = "pwm_d_x3"; 551 function = "pwm_d"; 552 bias-disable; 553 }; 554 }; 555 556 pwm_d_x6_pins: pwm-d-x6 { 557 mux { 558 groups = "pwm_d_x6"; 559 function = "pwm_d"; 560 bias-disable; 561 }; 562 }; 563 564 pwm_e_pins: pwm-e { 565 mux { 566 groups = "pwm_e"; 567 function = "pwm_e"; 568 bias-disable; 569 }; 570 }; 571 572 pwm_f_x_pins: pwm-f-x { 573 mux { 574 groups = "pwm_f_x"; 575 function = "pwm_f"; 576 bias-disable; 577 }; 578 }; 579 580 pwm_f_h_pins: pwm-f-h { 581 mux { 582 groups = "pwm_f_h"; 583 function = "pwm_f"; 584 bias-disable; 585 }; 586 }; 587 588 sdcard_c_pins: sdcard_c { 589 mux-0 { 590 groups = "sdcard_d0_c", 591 "sdcard_d1_c", 592 "sdcard_d2_c", 593 "sdcard_d3_c", 594 "sdcard_cmd_c"; 595 function = "sdcard"; 596 bias-pull-up; 597 drive-strength-microamp = <4000>; 598 }; 599 600 mux-1 { 601 groups = "sdcard_clk_c"; 602 function = "sdcard"; 603 bias-disable; 604 drive-strength-microamp = <4000>; 605 }; 606 }; 607 608 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 609 mux { 610 groups = "GPIOC_4"; 611 function = "gpio_periphs"; 612 bias-pull-down; 613 drive-strength-microamp = <4000>; 614 }; 615 }; 616 617 sdcard_z_pins: sdcard_z { 618 mux-0 { 619 groups = "sdcard_d0_z", 620 "sdcard_d1_z", 621 "sdcard_d2_z", 622 "sdcard_d3_z", 623 "sdcard_cmd_z"; 624 function = "sdcard"; 625 bias-pull-up; 626 drive-strength-microamp = <4000>; 627 }; 628 629 mux-1 { 630 groups = "sdcard_clk_z"; 631 function = "sdcard"; 632 bias-disable; 633 drive-strength-microamp = <4000>; 634 }; 635 }; 636 637 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 638 mux { 639 groups = "GPIOZ_6"; 640 function = "gpio_periphs"; 641 bias-pull-down; 642 drive-strength-microamp = <4000>; 643 }; 644 }; 645 646 spdif_out_h_pins: spdif-out-h { 647 mux { 648 groups = "spdif_out_h"; 649 function = "spdif_out"; 650 drive-strength-microamp = <500>; 651 bias-disable; 652 }; 653 }; 654 655 spdif_out_a11_pins: spdif-out-a11 { 656 mux { 657 groups = "spdif_out_a11"; 658 function = "spdif_out"; 659 drive-strength-microamp = <500>; 660 bias-disable; 661 }; 662 }; 663 664 spdif_out_a13_pins: spdif-out-a13 { 665 mux { 666 groups = "spdif_out_a13"; 667 function = "spdif_out"; 668 drive-strength-microamp = <500>; 669 bias-disable; 670 }; 671 }; 672 673 tdm_a_din0_pins: tdm-a-din0 { 674 mux { 675 groups = "tdm_a_din0"; 676 function = "tdm_a"; 677 bias-disable; 678 }; 679 }; 680 681 682 tdm_a_din1_pins: tdm-a-din1 { 683 mux { 684 groups = "tdm_a_din1"; 685 function = "tdm_a"; 686 bias-disable; 687 }; 688 }; 689 690 tdm_a_dout0_pins: tdm-a-dout0 { 691 mux { 692 groups = "tdm_a_dout0"; 693 function = "tdm_a"; 694 bias-disable; 695 drive-strength-microamp = <3000>; 696 }; 697 }; 698 699 tdm_a_dout1_pins: tdm-a-dout1 { 700 mux { 701 groups = "tdm_a_dout1"; 702 function = "tdm_a"; 703 bias-disable; 704 drive-strength-microamp = <3000>; 705 }; 706 }; 707 708 tdm_a_fs_pins: tdm-a-fs { 709 mux { 710 groups = "tdm_a_fs"; 711 function = "tdm_a"; 712 bias-disable; 713 drive-strength-microamp = <3000>; 714 }; 715 }; 716 717 tdm_a_sclk_pins: tdm-a-sclk { 718 mux { 719 groups = "tdm_a_sclk"; 720 function = "tdm_a"; 721 bias-disable; 722 drive-strength-microamp = <3000>; 723 }; 724 }; 725 726 tdm_a_slv_fs_pins: tdm-a-slv-fs { 727 mux { 728 groups = "tdm_a_slv_fs"; 729 function = "tdm_a"; 730 bias-disable; 731 }; 732 }; 733 734 735 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 736 mux { 737 groups = "tdm_a_slv_sclk"; 738 function = "tdm_a"; 739 bias-disable; 740 }; 741 }; 742 743 tdm_b_din0_pins: tdm-b-din0 { 744 mux { 745 groups = "tdm_b_din0"; 746 function = "tdm_b"; 747 bias-disable; 748 }; 749 }; 750 751 tdm_b_din1_pins: tdm-b-din1 { 752 mux { 753 groups = "tdm_b_din1"; 754 function = "tdm_b"; 755 bias-disable; 756 }; 757 }; 758 759 tdm_b_din2_pins: tdm-b-din2 { 760 mux { 761 groups = "tdm_b_din2"; 762 function = "tdm_b"; 763 bias-disable; 764 }; 765 }; 766 767 tdm_b_din3_a_pins: tdm-b-din3-a { 768 mux { 769 groups = "tdm_b_din3_a"; 770 function = "tdm_b"; 771 bias-disable; 772 }; 773 }; 774 775 tdm_b_din3_h_pins: tdm-b-din3-h { 776 mux { 777 groups = "tdm_b_din3_h"; 778 function = "tdm_b"; 779 bias-disable; 780 }; 781 }; 782 783 tdm_b_dout0_pins: tdm-b-dout0 { 784 mux { 785 groups = "tdm_b_dout0"; 786 function = "tdm_b"; 787 bias-disable; 788 drive-strength-microamp = <3000>; 789 }; 790 }; 791 792 tdm_b_dout1_pins: tdm-b-dout1 { 793 mux { 794 groups = "tdm_b_dout1"; 795 function = "tdm_b"; 796 bias-disable; 797 drive-strength-microamp = <3000>; 798 }; 799 }; 800 801 tdm_b_dout2_pins: tdm-b-dout2 { 802 mux { 803 groups = "tdm_b_dout2"; 804 function = "tdm_b"; 805 bias-disable; 806 drive-strength-microamp = <3000>; 807 }; 808 }; 809 810 tdm_b_dout3_a_pins: tdm-b-dout3-a { 811 mux { 812 groups = "tdm_b_dout3_a"; 813 function = "tdm_b"; 814 bias-disable; 815 drive-strength-microamp = <3000>; 816 }; 817 }; 818 819 tdm_b_dout3_h_pins: tdm-b-dout3-h { 820 mux { 821 groups = "tdm_b_dout3_h"; 822 function = "tdm_b"; 823 bias-disable; 824 drive-strength-microamp = <3000>; 825 }; 826 }; 827 828 tdm_b_fs_pins: tdm-b-fs { 829 mux { 830 groups = "tdm_b_fs"; 831 function = "tdm_b"; 832 bias-disable; 833 drive-strength-microamp = <3000>; 834 }; 835 }; 836 837 tdm_b_sclk_pins: tdm-b-sclk { 838 mux { 839 groups = "tdm_b_sclk"; 840 function = "tdm_b"; 841 bias-disable; 842 drive-strength-microamp = <3000>; 843 }; 844 }; 845 846 tdm_b_slv_fs_pins: tdm-b-slv-fs { 847 mux { 848 groups = "tdm_b_slv_fs"; 849 function = "tdm_b"; 850 bias-disable; 851 }; 852 }; 853 854 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 855 mux { 856 groups = "tdm_b_slv_sclk"; 857 function = "tdm_b"; 858 bias-disable; 859 }; 860 }; 861 862 tdm_c_din0_a_pins: tdm-c-din0-a { 863 mux { 864 groups = "tdm_c_din0_a"; 865 function = "tdm_c"; 866 bias-disable; 867 }; 868 }; 869 870 tdm_c_din0_z_pins: tdm-c-din0-z { 871 mux { 872 groups = "tdm_c_din0_z"; 873 function = "tdm_c"; 874 bias-disable; 875 }; 876 }; 877 878 tdm_c_din1_a_pins: tdm-c-din1-a { 879 mux { 880 groups = "tdm_c_din1_a"; 881 function = "tdm_c"; 882 bias-disable; 883 }; 884 }; 885 886 tdm_c_din1_z_pins: tdm-c-din1-z { 887 mux { 888 groups = "tdm_c_din1_z"; 889 function = "tdm_c"; 890 bias-disable; 891 }; 892 }; 893 894 tdm_c_din2_a_pins: tdm-c-din2-a { 895 mux { 896 groups = "tdm_c_din2_a"; 897 function = "tdm_c"; 898 bias-disable; 899 }; 900 }; 901 902 tdm_c_din2_z_pins: tdm-c-din2-z { 903 mux { 904 groups = "tdm_c_din2_z"; 905 function = "tdm_c"; 906 bias-disable; 907 }; 908 }; 909 910 tdm_c_din3_a_pins: tdm-c-din3-a { 911 mux { 912 groups = "tdm_c_din3_a"; 913 function = "tdm_c"; 914 bias-disable; 915 }; 916 }; 917 918 tdm_c_din3_z_pins: tdm-c-din3-z { 919 mux { 920 groups = "tdm_c_din3_z"; 921 function = "tdm_c"; 922 bias-disable; 923 }; 924 }; 925 926 tdm_c_dout0_a_pins: tdm-c-dout0-a { 927 mux { 928 groups = "tdm_c_dout0_a"; 929 function = "tdm_c"; 930 bias-disable; 931 drive-strength-microamp = <3000>; 932 }; 933 }; 934 935 tdm_c_dout0_z_pins: tdm-c-dout0-z { 936 mux { 937 groups = "tdm_c_dout0_z"; 938 function = "tdm_c"; 939 bias-disable; 940 drive-strength-microamp = <3000>; 941 }; 942 }; 943 944 tdm_c_dout1_a_pins: tdm-c-dout1-a { 945 mux { 946 groups = "tdm_c_dout1_a"; 947 function = "tdm_c"; 948 bias-disable; 949 drive-strength-microamp = <3000>; 950 }; 951 }; 952 953 tdm_c_dout1_z_pins: tdm-c-dout1-z { 954 mux { 955 groups = "tdm_c_dout1_z"; 956 function = "tdm_c"; 957 bias-disable; 958 drive-strength-microamp = <3000>; 959 }; 960 }; 961 962 tdm_c_dout2_a_pins: tdm-c-dout2-a { 963 mux { 964 groups = "tdm_c_dout2_a"; 965 function = "tdm_c"; 966 bias-disable; 967 drive-strength-microamp = <3000>; 968 }; 969 }; 970 971 tdm_c_dout2_z_pins: tdm-c-dout2-z { 972 mux { 973 groups = "tdm_c_dout2_z"; 974 function = "tdm_c"; 975 bias-disable; 976 drive-strength-microamp = <3000>; 977 }; 978 }; 979 980 tdm_c_dout3_a_pins: tdm-c-dout3-a { 981 mux { 982 groups = "tdm_c_dout3_a"; 983 function = "tdm_c"; 984 bias-disable; 985 drive-strength-microamp = <3000>; 986 }; 987 }; 988 989 tdm_c_dout3_z_pins: tdm-c-dout3-z { 990 mux { 991 groups = "tdm_c_dout3_z"; 992 function = "tdm_c"; 993 bias-disable; 994 drive-strength-microamp = <3000>; 995 }; 996 }; 997 998 tdm_c_fs_a_pins: tdm-c-fs-a { 999 mux { 1000 groups = "tdm_c_fs_a"; 1001 function = "tdm_c"; 1002 bias-disable; 1003 drive-strength-microamp = <3000>; 1004 }; 1005 }; 1006 1007 tdm_c_fs_z_pins: tdm-c-fs-z { 1008 mux { 1009 groups = "tdm_c_fs_z"; 1010 function = "tdm_c"; 1011 bias-disable; 1012 drive-strength-microamp = <3000>; 1013 }; 1014 }; 1015 1016 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1017 mux { 1018 groups = "tdm_c_sclk_a"; 1019 function = "tdm_c"; 1020 bias-disable; 1021 drive-strength-microamp = <3000>; 1022 }; 1023 }; 1024 1025 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1026 mux { 1027 groups = "tdm_c_sclk_z"; 1028 function = "tdm_c"; 1029 bias-disable; 1030 drive-strength-microamp = <3000>; 1031 }; 1032 }; 1033 1034 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1035 mux { 1036 groups = "tdm_c_slv_fs_a"; 1037 function = "tdm_c"; 1038 bias-disable; 1039 }; 1040 }; 1041 1042 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1043 mux { 1044 groups = "tdm_c_slv_fs_z"; 1045 function = "tdm_c"; 1046 bias-disable; 1047 }; 1048 }; 1049 1050 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1051 mux { 1052 groups = "tdm_c_slv_sclk_a"; 1053 function = "tdm_c"; 1054 bias-disable; 1055 }; 1056 }; 1057 1058 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1059 mux { 1060 groups = "tdm_c_slv_sclk_z"; 1061 function = "tdm_c"; 1062 bias-disable; 1063 }; 1064 }; 1065 1066 uart_a_pins: uart-a { 1067 mux { 1068 groups = "uart_a_tx", 1069 "uart_a_rx"; 1070 function = "uart_a"; 1071 bias-disable; 1072 }; 1073 }; 1074 1075 uart_a_cts_rts_pins: uart-a-cts-rts { 1076 mux { 1077 groups = "uart_a_cts", 1078 "uart_a_rts"; 1079 function = "uart_a"; 1080 bias-disable; 1081 }; 1082 }; 1083 1084 uart_b_pins: uart-b { 1085 mux { 1086 groups = "uart_b_tx", 1087 "uart_b_rx"; 1088 function = "uart_b"; 1089 bias-disable; 1090 }; 1091 }; 1092 1093 uart_c_pins: uart-c { 1094 mux { 1095 groups = "uart_c_tx", 1096 "uart_c_rx"; 1097 function = "uart_c"; 1098 bias-disable; 1099 }; 1100 }; 1101 1102 uart_c_cts_rts_pins: uart-c-cts-rts { 1103 mux { 1104 groups = "uart_c_cts", 1105 "uart_c_rts"; 1106 function = "uart_c"; 1107 bias-disable; 1108 }; 1109 }; 1110 }; 1111 }; 1112 1113 usb2_phy0: phy@36000 { 1114 compatible = "amlogic,g12a-usb2-phy"; 1115 reg = <0x0 0x36000 0x0 0x2000>; 1116 clocks = <&xtal>; 1117 clock-names = "xtal"; 1118 resets = <&reset RESET_USB_PHY20>; 1119 reset-names = "phy"; 1120 #phy-cells = <0>; 1121 }; 1122 1123 dmc: bus@38000 { 1124 compatible = "simple-bus"; 1125 reg = <0x0 0x38000 0x0 0x400>; 1126 #address-cells = <2>; 1127 #size-cells = <2>; 1128 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1129 1130 canvas: video-lut@48 { 1131 compatible = "amlogic,canvas"; 1132 reg = <0x0 0x48 0x0 0x14>; 1133 }; 1134 }; 1135 1136 usb2_phy1: phy@3a000 { 1137 compatible = "amlogic,g12a-usb2-phy"; 1138 reg = <0x0 0x3a000 0x0 0x2000>; 1139 clocks = <&xtal>; 1140 clock-names = "xtal"; 1141 resets = <&reset RESET_USB_PHY21>; 1142 reset-names = "phy"; 1143 #phy-cells = <0>; 1144 }; 1145 1146 hiu: bus@3c000 { 1147 compatible = "simple-bus"; 1148 reg = <0x0 0x3c000 0x0 0x1400>; 1149 #address-cells = <2>; 1150 #size-cells = <2>; 1151 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1152 1153 hhi: system-controller@0 { 1154 compatible = "amlogic,meson-gx-hhi-sysctrl", 1155 "simple-mfd", "syscon"; 1156 reg = <0 0 0 0x400>; 1157 1158 clkc: clock-controller { 1159 compatible = "amlogic,g12a-clkc"; 1160 #clock-cells = <1>; 1161 clocks = <&xtal>; 1162 clock-names = "xtal"; 1163 }; 1164 }; 1165 }; 1166 1167 audio: bus@42000 { 1168 compatible = "simple-bus"; 1169 reg = <0x0 0x42000 0x0 0x2000>; 1170 #address-cells = <2>; 1171 #size-cells = <2>; 1172 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1173 1174 clkc_audio: clock-controller@0 { 1175 status = "disabled"; 1176 compatible = "amlogic,g12a-audio-clkc"; 1177 reg = <0x0 0x0 0x0 0xb4>; 1178 #clock-cells = <1>; 1179 1180 clocks = <&clkc CLKID_AUDIO>, 1181 <&clkc CLKID_MPLL0>, 1182 <&clkc CLKID_MPLL1>, 1183 <&clkc CLKID_MPLL2>, 1184 <&clkc CLKID_MPLL3>, 1185 <&clkc CLKID_HIFI_PLL>, 1186 <&clkc CLKID_FCLK_DIV3>, 1187 <&clkc CLKID_FCLK_DIV4>, 1188 <&clkc CLKID_GP0_PLL>; 1189 clock-names = "pclk", 1190 "mst_in0", 1191 "mst_in1", 1192 "mst_in2", 1193 "mst_in3", 1194 "mst_in4", 1195 "mst_in5", 1196 "mst_in6", 1197 "mst_in7"; 1198 1199 resets = <&reset RESET_AUDIO>; 1200 }; 1201 1202 toddr_a: audio-controller@100 { 1203 compatible = "amlogic,g12a-toddr", 1204 "amlogic,axg-toddr"; 1205 reg = <0x0 0x100 0x0 0x1c>; 1206 #sound-dai-cells = <0>; 1207 sound-name-prefix = "TODDR_A"; 1208 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1209 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1210 resets = <&arb AXG_ARB_TODDR_A>; 1211 status = "disabled"; 1212 }; 1213 1214 toddr_b: audio-controller@140 { 1215 compatible = "amlogic,g12a-toddr", 1216 "amlogic,axg-toddr"; 1217 reg = <0x0 0x140 0x0 0x1c>; 1218 #sound-dai-cells = <0>; 1219 sound-name-prefix = "TODDR_B"; 1220 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1221 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1222 resets = <&arb AXG_ARB_TODDR_B>; 1223 status = "disabled"; 1224 }; 1225 1226 toddr_c: audio-controller@180 { 1227 compatible = "amlogic,g12a-toddr", 1228 "amlogic,axg-toddr"; 1229 reg = <0x0 0x180 0x0 0x1c>; 1230 #sound-dai-cells = <0>; 1231 sound-name-prefix = "TODDR_C"; 1232 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1233 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1234 resets = <&arb AXG_ARB_TODDR_C>; 1235 status = "disabled"; 1236 }; 1237 1238 frddr_a: audio-controller@1c0 { 1239 compatible = "amlogic,g12a-frddr", 1240 "amlogic,axg-frddr"; 1241 reg = <0x0 0x1c0 0x0 0x1c>; 1242 #sound-dai-cells = <0>; 1243 sound-name-prefix = "FRDDR_A"; 1244 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1245 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1246 resets = <&arb AXG_ARB_FRDDR_A>; 1247 status = "disabled"; 1248 }; 1249 1250 frddr_b: audio-controller@200 { 1251 compatible = "amlogic,g12a-frddr", 1252 "amlogic,axg-frddr"; 1253 reg = <0x0 0x200 0x0 0x1c>; 1254 #sound-dai-cells = <0>; 1255 sound-name-prefix = "FRDDR_B"; 1256 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1257 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1258 resets = <&arb AXG_ARB_FRDDR_B>; 1259 status = "disabled"; 1260 }; 1261 1262 frddr_c: audio-controller@240 { 1263 compatible = "amlogic,g12a-frddr", 1264 "amlogic,axg-frddr"; 1265 reg = <0x0 0x240 0x0 0x1c>; 1266 #sound-dai-cells = <0>; 1267 sound-name-prefix = "FRDDR_C"; 1268 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1269 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1270 resets = <&arb AXG_ARB_FRDDR_C>; 1271 status = "disabled"; 1272 }; 1273 1274 arb: reset-controller@280 { 1275 status = "disabled"; 1276 compatible = "amlogic,meson-axg-audio-arb"; 1277 reg = <0x0 0x280 0x0 0x4>; 1278 #reset-cells = <1>; 1279 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1280 }; 1281 1282 tdmin_a: audio-controller@300 { 1283 compatible = "amlogic,g12a-tdmin", 1284 "amlogic,axg-tdmin"; 1285 reg = <0x0 0x300 0x0 0x40>; 1286 sound-name-prefix = "TDMIN_A"; 1287 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1288 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1289 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1290 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1291 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1292 clock-names = "pclk", "sclk", "sclk_sel", 1293 "lrclk", "lrclk_sel"; 1294 status = "disabled"; 1295 }; 1296 1297 tdmin_b: audio-controller@340 { 1298 compatible = "amlogic,g12a-tdmin", 1299 "amlogic,axg-tdmin"; 1300 reg = <0x0 0x340 0x0 0x40>; 1301 sound-name-prefix = "TDMIN_B"; 1302 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1303 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1304 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1305 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1306 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1307 clock-names = "pclk", "sclk", "sclk_sel", 1308 "lrclk", "lrclk_sel"; 1309 status = "disabled"; 1310 }; 1311 1312 tdmin_c: audio-controller@380 { 1313 compatible = "amlogic,g12a-tdmin", 1314 "amlogic,axg-tdmin"; 1315 reg = <0x0 0x380 0x0 0x40>; 1316 sound-name-prefix = "TDMIN_C"; 1317 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1318 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1319 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1320 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1321 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1322 clock-names = "pclk", "sclk", "sclk_sel", 1323 "lrclk", "lrclk_sel"; 1324 status = "disabled"; 1325 }; 1326 1327 tdmin_lb: audio-controller@3c0 { 1328 compatible = "amlogic,g12a-tdmin", 1329 "amlogic,axg-tdmin"; 1330 reg = <0x0 0x3c0 0x0 0x40>; 1331 sound-name-prefix = "TDMIN_LB"; 1332 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1333 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1334 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1335 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1336 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1337 clock-names = "pclk", "sclk", "sclk_sel", 1338 "lrclk", "lrclk_sel"; 1339 status = "disabled"; 1340 }; 1341 1342 spdifout: audio-controller@480 { 1343 compatible = "amlogic,g12a-spdifout", 1344 "amlogic,axg-spdifout"; 1345 reg = <0x0 0x480 0x0 0x50>; 1346 #sound-dai-cells = <0>; 1347 sound-name-prefix = "SPDIFOUT"; 1348 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1349 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1350 clock-names = "pclk", "mclk"; 1351 status = "disabled"; 1352 }; 1353 1354 tdmout_a: audio-controller@500 { 1355 compatible = "amlogic,g12a-tdmout"; 1356 reg = <0x0 0x500 0x0 0x40>; 1357 sound-name-prefix = "TDMOUT_A"; 1358 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1359 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1360 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1361 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1362 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1363 clock-names = "pclk", "sclk", "sclk_sel", 1364 "lrclk", "lrclk_sel"; 1365 status = "disabled"; 1366 }; 1367 1368 tdmout_b: audio-controller@540 { 1369 compatible = "amlogic,g12a-tdmout"; 1370 reg = <0x0 0x540 0x0 0x40>; 1371 sound-name-prefix = "TDMOUT_B"; 1372 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1373 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1374 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1375 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1376 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1377 clock-names = "pclk", "sclk", "sclk_sel", 1378 "lrclk", "lrclk_sel"; 1379 status = "disabled"; 1380 }; 1381 1382 tdmout_c: audio-controller@580 { 1383 compatible = "amlogic,g12a-tdmout"; 1384 reg = <0x0 0x580 0x0 0x40>; 1385 sound-name-prefix = "TDMOUT_C"; 1386 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1387 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1388 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1389 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1390 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1391 clock-names = "pclk", "sclk", "sclk_sel", 1392 "lrclk", "lrclk_sel"; 1393 status = "disabled"; 1394 }; 1395 1396 spdifout_b: audio-controller@680 { 1397 compatible = "amlogic,g12a-spdifout", 1398 "amlogic,axg-spdifout"; 1399 reg = <0x0 0x680 0x0 0x50>; 1400 #sound-dai-cells = <0>; 1401 sound-name-prefix = "SPDIFOUT_B"; 1402 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1403 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1404 clock-names = "pclk", "mclk"; 1405 status = "disabled"; 1406 }; 1407 }; 1408 1409 usb3_pcie_phy: phy@46000 { 1410 compatible = "amlogic,g12a-usb3-pcie-phy"; 1411 reg = <0x0 0x46000 0x0 0x2000>; 1412 clocks = <&clkc CLKID_PCIE_PLL>; 1413 clock-names = "ref_clk"; 1414 resets = <&reset RESET_PCIE_PHY>; 1415 reset-names = "phy"; 1416 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1417 assigned-clock-rates = <100000000>; 1418 #phy-cells = <1>; 1419 }; 1420 }; 1421 1422 aobus: bus@ff800000 { 1423 compatible = "simple-bus"; 1424 reg = <0x0 0xff800000 0x0 0x100000>; 1425 #address-cells = <2>; 1426 #size-cells = <2>; 1427 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1428 1429 rti: sys-ctrl@0 { 1430 compatible = "amlogic,meson-gx-ao-sysctrl", 1431 "simple-mfd", "syscon"; 1432 reg = <0x0 0x0 0x0 0x100>; 1433 #address-cells = <2>; 1434 #size-cells = <2>; 1435 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1436 1437 clkc_AO: clock-controller { 1438 compatible = "amlogic,meson-g12a-aoclkc"; 1439 #clock-cells = <1>; 1440 #reset-cells = <1>; 1441 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1442 clock-names = "xtal", "mpeg-clk"; 1443 }; 1444 1445 pwrc_vpu: power-controller-vpu { 1446 compatible = "amlogic,meson-g12a-pwrc-vpu"; 1447 #power-domain-cells = <0>; 1448 amlogic,hhi-sysctrl = <&hhi>; 1449 resets = <&reset RESET_VIU>, 1450 <&reset RESET_VENC>, 1451 <&reset RESET_VCBUS>, 1452 <&reset RESET_BT656>, 1453 <&reset RESET_RDMA>, 1454 <&reset RESET_VENCI>, 1455 <&reset RESET_VENCP>, 1456 <&reset RESET_VDAC>, 1457 <&reset RESET_VDI6>, 1458 <&reset RESET_VENCL>, 1459 <&reset RESET_VID_LOCK>; 1460 clocks = <&clkc CLKID_VPU>, 1461 <&clkc CLKID_VAPB>; 1462 clock-names = "vpu", "vapb"; 1463 /* 1464 * VPU clocking is provided by two identical clock paths 1465 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1466 * free mux to safely change frequency while running. 1467 * Same for VAPB but with a final gate after the glitch free mux. 1468 */ 1469 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1470 <&clkc CLKID_VPU_0>, 1471 <&clkc CLKID_VPU>, /* Glitch free mux */ 1472 <&clkc CLKID_VAPB_0_SEL>, 1473 <&clkc CLKID_VAPB_0>, 1474 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1475 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1476 <0>, /* Do Nothing */ 1477 <&clkc CLKID_VPU_0>, 1478 <&clkc CLKID_FCLK_DIV4>, 1479 <0>, /* Do Nothing */ 1480 <&clkc CLKID_VAPB_0>; 1481 assigned-clock-rates = <0>, /* Do Nothing */ 1482 <666666666>, 1483 <0>, /* Do Nothing */ 1484 <0>, /* Do Nothing */ 1485 <250000000>, 1486 <0>; /* Do Nothing */ 1487 }; 1488 1489 ao_pinctrl: pinctrl@14 { 1490 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1491 #address-cells = <2>; 1492 #size-cells = <2>; 1493 ranges; 1494 1495 gpio_ao: bank@14 { 1496 reg = <0x0 0x14 0x0 0x8>, 1497 <0x0 0x1c 0x0 0x8>, 1498 <0x0 0x24 0x0 0x14>; 1499 reg-names = "mux", 1500 "ds", 1501 "gpio"; 1502 gpio-controller; 1503 #gpio-cells = <2>; 1504 gpio-ranges = <&ao_pinctrl 0 0 15>; 1505 }; 1506 1507 i2c_ao_sck_pins: i2c_ao_sck_pins { 1508 mux { 1509 groups = "i2c_ao_sck"; 1510 function = "i2c_ao"; 1511 bias-disable; 1512 drive-strength-microamp = <3000>; 1513 }; 1514 }; 1515 1516 i2c_ao_sda_pins: i2c_ao_sda { 1517 mux { 1518 groups = "i2c_ao_sda"; 1519 function = "i2c_ao"; 1520 bias-disable; 1521 drive-strength-microamp = <3000>; 1522 }; 1523 }; 1524 1525 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1526 mux { 1527 groups = "i2c_ao_sck_e"; 1528 function = "i2c_ao"; 1529 bias-disable; 1530 drive-strength-microamp = <3000>; 1531 }; 1532 }; 1533 1534 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1535 mux { 1536 groups = "i2c_ao_sda_e"; 1537 function = "i2c_ao"; 1538 bias-disable; 1539 drive-strength-microamp = <3000>; 1540 }; 1541 }; 1542 1543 mclk0_ao_pins: mclk0-ao { 1544 mux { 1545 groups = "mclk0_ao"; 1546 function = "mclk0_ao"; 1547 bias-disable; 1548 drive-strength-microamp = <3000>; 1549 }; 1550 }; 1551 1552 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1553 mux { 1554 groups = "tdm_ao_b_din0"; 1555 function = "tdm_ao_b"; 1556 bias-disable; 1557 }; 1558 }; 1559 1560 spdif_ao_out_pins: spdif-ao-out { 1561 mux { 1562 groups = "spdif_ao_out"; 1563 function = "spdif_ao_out"; 1564 drive-strength-microamp = <500>; 1565 bias-disable; 1566 }; 1567 }; 1568 1569 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1570 mux { 1571 groups = "tdm_ao_b_din1"; 1572 function = "tdm_ao_b"; 1573 bias-disable; 1574 }; 1575 }; 1576 1577 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1578 mux { 1579 groups = "tdm_ao_b_din2"; 1580 function = "tdm_ao_b"; 1581 bias-disable; 1582 }; 1583 }; 1584 1585 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1586 mux { 1587 groups = "tdm_ao_b_dout0"; 1588 function = "tdm_ao_b"; 1589 bias-disable; 1590 drive-strength-microamp = <3000>; 1591 }; 1592 }; 1593 1594 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1595 mux { 1596 groups = "tdm_ao_b_dout1"; 1597 function = "tdm_ao_b"; 1598 bias-disable; 1599 drive-strength-microamp = <3000>; 1600 }; 1601 }; 1602 1603 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1604 mux { 1605 groups = "tdm_ao_b_dout2"; 1606 function = "tdm_ao_b"; 1607 bias-disable; 1608 drive-strength-microamp = <3000>; 1609 }; 1610 }; 1611 1612 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1613 mux { 1614 groups = "tdm_ao_b_fs"; 1615 function = "tdm_ao_b"; 1616 bias-disable; 1617 drive-strength-microamp = <3000>; 1618 }; 1619 }; 1620 1621 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1622 mux { 1623 groups = "tdm_ao_b_sclk"; 1624 function = "tdm_ao_b"; 1625 bias-disable; 1626 drive-strength-microamp = <3000>; 1627 }; 1628 }; 1629 1630 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1631 mux { 1632 groups = "tdm_ao_b_slv_fs"; 1633 function = "tdm_ao_b"; 1634 bias-disable; 1635 }; 1636 }; 1637 1638 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1639 mux { 1640 groups = "tdm_ao_b_slv_sclk"; 1641 function = "tdm_ao_b"; 1642 bias-disable; 1643 }; 1644 }; 1645 1646 uart_ao_a_pins: uart-a-ao { 1647 mux { 1648 groups = "uart_ao_a_tx", 1649 "uart_ao_a_rx"; 1650 function = "uart_ao_a"; 1651 bias-disable; 1652 }; 1653 }; 1654 1655 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1656 mux { 1657 groups = "uart_ao_a_cts", 1658 "uart_ao_a_rts"; 1659 function = "uart_ao_a"; 1660 bias-disable; 1661 }; 1662 }; 1663 1664 pwm_ao_a_pins: pwm-ao-a { 1665 mux { 1666 groups = "pwm_ao_a"; 1667 function = "pwm_ao_a"; 1668 bias-disable; 1669 }; 1670 }; 1671 1672 pwm_ao_b_pins: pwm-ao-b { 1673 mux { 1674 groups = "pwm_ao_b"; 1675 function = "pwm_ao_b"; 1676 bias-disable; 1677 }; 1678 }; 1679 1680 pwm_ao_c_4_pins: pwm-ao-c-4 { 1681 mux { 1682 groups = "pwm_ao_c_4"; 1683 function = "pwm_ao_c"; 1684 bias-disable; 1685 }; 1686 }; 1687 1688 pwm_ao_c_6_pins: pwm-ao-c-6 { 1689 mux { 1690 groups = "pwm_ao_c_6"; 1691 function = "pwm_ao_c"; 1692 bias-disable; 1693 }; 1694 }; 1695 1696 pwm_ao_d_5_pins: pwm-ao-d-5 { 1697 mux { 1698 groups = "pwm_ao_d_5"; 1699 function = "pwm_ao_d"; 1700 bias-disable; 1701 }; 1702 }; 1703 1704 pwm_ao_d_10_pins: pwm-ao-d-10 { 1705 mux { 1706 groups = "pwm_ao_d_10"; 1707 function = "pwm_ao_d"; 1708 bias-disable; 1709 }; 1710 }; 1711 1712 pwm_ao_d_e_pins: pwm-ao-d-e { 1713 mux { 1714 groups = "pwm_ao_d_e"; 1715 function = "pwm_ao_d"; 1716 }; 1717 }; 1718 1719 remote_input_ao_pins: remote-input-ao { 1720 mux { 1721 groups = "remote_ao_input"; 1722 function = "remote_ao_input"; 1723 bias-disable; 1724 }; 1725 }; 1726 }; 1727 }; 1728 1729 cec_AO: cec@100 { 1730 compatible = "amlogic,meson-gx-ao-cec"; 1731 reg = <0x0 0x00100 0x0 0x14>; 1732 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 1733 clocks = <&clkc_AO CLKID_AO_CEC>; 1734 clock-names = "core"; 1735 status = "disabled"; 1736 }; 1737 1738 sec_AO: ao-secure@140 { 1739 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1740 reg = <0x0 0x140 0x0 0x140>; 1741 amlogic,has-chip-id; 1742 }; 1743 1744 cecb_AO: cec@280 { 1745 compatible = "amlogic,meson-g12a-ao-cec"; 1746 reg = <0x0 0x00280 0x0 0x1c>; 1747 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1748 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 1749 clock-names = "oscin"; 1750 status = "disabled"; 1751 }; 1752 1753 pwm_AO_cd: pwm@2000 { 1754 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 1755 reg = <0x0 0x2000 0x0 0x20>; 1756 #pwm-cells = <3>; 1757 status = "disabled"; 1758 }; 1759 1760 uart_AO: serial@3000 { 1761 compatible = "amlogic,meson-gx-uart", 1762 "amlogic,meson-ao-uart"; 1763 reg = <0x0 0x3000 0x0 0x18>; 1764 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1765 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 1766 clock-names = "xtal", "pclk", "baud"; 1767 status = "disabled"; 1768 }; 1769 1770 uart_AO_B: serial@4000 { 1771 compatible = "amlogic,meson-gx-uart", 1772 "amlogic,meson-ao-uart"; 1773 reg = <0x0 0x4000 0x0 0x18>; 1774 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1775 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1776 clock-names = "xtal", "pclk", "baud"; 1777 status = "disabled"; 1778 }; 1779 1780 i2c_AO: i2c@5000 { 1781 compatible = "amlogic,meson-axg-i2c"; 1782 status = "disabled"; 1783 reg = <0x0 0x05000 0x0 0x20>; 1784 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1785 #address-cells = <1>; 1786 #size-cells = <0>; 1787 clocks = <&clkc CLKID_I2C>; 1788 }; 1789 1790 pwm_AO_ab: pwm@7000 { 1791 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 1792 reg = <0x0 0x7000 0x0 0x20>; 1793 #pwm-cells = <3>; 1794 status = "disabled"; 1795 }; 1796 1797 ir: ir@8000 { 1798 compatible = "amlogic,meson-gxbb-ir"; 1799 reg = <0x0 0x8000 0x0 0x20>; 1800 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1801 status = "disabled"; 1802 }; 1803 1804 saradc: adc@9000 { 1805 compatible = "amlogic,meson-g12a-saradc", 1806 "amlogic,meson-saradc"; 1807 reg = <0x0 0x9000 0x0 0x48>; 1808 #io-channel-cells = <1>; 1809 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 1810 clocks = <&xtal>, 1811 <&clkc_AO CLKID_AO_SAR_ADC>, 1812 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1813 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1814 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1815 status = "disabled"; 1816 }; 1817 }; 1818 1819 vpu: vpu@ff900000 { 1820 compatible = "amlogic,meson-g12a-vpu"; 1821 reg = <0x0 0xff900000 0x0 0x100000>, 1822 <0x0 0xff63c000 0x0 0x1000>; 1823 reg-names = "vpu", "hhi"; 1824 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 1825 #address-cells = <1>; 1826 #size-cells = <0>; 1827 amlogic,canvas = <&canvas>; 1828 power-domains = <&pwrc_vpu>; 1829 1830 /* CVBS VDAC output port */ 1831 cvbs_vdac_port: port@0 { 1832 reg = <0>; 1833 }; 1834 1835 /* HDMI-TX output port */ 1836 hdmi_tx_port: port@1 { 1837 reg = <1>; 1838 1839 hdmi_tx_out: endpoint { 1840 remote-endpoint = <&hdmi_tx_in>; 1841 }; 1842 }; 1843 }; 1844 1845 gic: interrupt-controller@ffc01000 { 1846 compatible = "arm,gic-400"; 1847 reg = <0x0 0xffc01000 0 0x1000>, 1848 <0x0 0xffc02000 0 0x2000>, 1849 <0x0 0xffc04000 0 0x2000>, 1850 <0x0 0xffc06000 0 0x2000>; 1851 interrupt-controller; 1852 interrupts = <GIC_PPI 9 1853 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1854 #interrupt-cells = <3>; 1855 #address-cells = <0>; 1856 }; 1857 1858 cbus: bus@ffd00000 { 1859 compatible = "simple-bus"; 1860 reg = <0x0 0xffd00000 0x0 0x100000>; 1861 #address-cells = <2>; 1862 #size-cells = <2>; 1863 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 1864 1865 reset: reset-controller@1004 { 1866 compatible = "amlogic,meson-g12a-reset", 1867 "amlogic,meson-axg-reset"; 1868 reg = <0x0 0x1004 0x0 0x9c>; 1869 #reset-cells = <1>; 1870 }; 1871 1872 pwm_ef: pwm@19000 { 1873 compatible = "amlogic,meson-g12a-ee-pwm"; 1874 reg = <0x0 0x19000 0x0 0x20>; 1875 #pwm-cells = <3>; 1876 status = "disabled"; 1877 }; 1878 1879 pwm_cd: pwm@1a000 { 1880 compatible = "amlogic,meson-g12a-ee-pwm"; 1881 reg = <0x0 0x1a000 0x0 0x20>; 1882 #pwm-cells = <3>; 1883 status = "disabled"; 1884 }; 1885 1886 pwm_ab: pwm@1b000 { 1887 compatible = "amlogic,meson-g12a-ee-pwm"; 1888 reg = <0x0 0x1b000 0x0 0x20>; 1889 #pwm-cells = <3>; 1890 status = "disabled"; 1891 }; 1892 1893 i2c3: i2c@1c000 { 1894 compatible = "amlogic,meson-axg-i2c"; 1895 status = "disabled"; 1896 reg = <0x0 0x1c000 0x0 0x20>; 1897 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 clocks = <&clkc CLKID_I2C>; 1901 }; 1902 1903 i2c2: i2c@1d000 { 1904 compatible = "amlogic,meson-axg-i2c"; 1905 status = "disabled"; 1906 reg = <0x0 0x1d000 0x0 0x20>; 1907 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 clocks = <&clkc CLKID_I2C>; 1911 }; 1912 1913 i2c1: i2c@1e000 { 1914 compatible = "amlogic,meson-axg-i2c"; 1915 status = "disabled"; 1916 reg = <0x0 0x1e000 0x0 0x20>; 1917 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 clocks = <&clkc CLKID_I2C>; 1921 }; 1922 1923 i2c0: i2c@1f000 { 1924 compatible = "amlogic,meson-axg-i2c"; 1925 status = "disabled"; 1926 reg = <0x0 0x1f000 0x0 0x20>; 1927 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1928 #address-cells = <1>; 1929 #size-cells = <0>; 1930 clocks = <&clkc CLKID_I2C>; 1931 }; 1932 1933 clk_msr: clock-measure@18000 { 1934 compatible = "amlogic,meson-g12a-clk-measure"; 1935 reg = <0x0 0x18000 0x0 0x10>; 1936 }; 1937 1938 uart_C: serial@22000 { 1939 compatible = "amlogic,meson-gx-uart"; 1940 reg = <0x0 0x22000 0x0 0x18>; 1941 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 1942 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 1943 clock-names = "xtal", "pclk", "baud"; 1944 status = "disabled"; 1945 }; 1946 1947 uart_B: serial@23000 { 1948 compatible = "amlogic,meson-gx-uart"; 1949 reg = <0x0 0x23000 0x0 0x18>; 1950 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1951 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1952 clock-names = "xtal", "pclk", "baud"; 1953 status = "disabled"; 1954 }; 1955 1956 uart_A: serial@24000 { 1957 compatible = "amlogic,meson-gx-uart"; 1958 reg = <0x0 0x24000 0x0 0x18>; 1959 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1960 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1961 clock-names = "xtal", "pclk", "baud"; 1962 status = "disabled"; 1963 }; 1964 }; 1965 1966 sd_emmc_b: sd@ffe05000 { 1967 compatible = "amlogic,meson-axg-mmc"; 1968 reg = <0x0 0xffe05000 0x0 0x800>; 1969 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 1970 status = "disabled"; 1971 clocks = <&clkc CLKID_SD_EMMC_B>, 1972 <&clkc CLKID_SD_EMMC_B_CLK0>, 1973 <&clkc CLKID_FCLK_DIV2>; 1974 clock-names = "core", "clkin0", "clkin1"; 1975 resets = <&reset RESET_SD_EMMC_B>; 1976 }; 1977 1978 sd_emmc_c: mmc@ffe07000 { 1979 compatible = "amlogic,meson-axg-mmc"; 1980 reg = <0x0 0xffe07000 0x0 0x800>; 1981 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 1982 status = "disabled"; 1983 clocks = <&clkc CLKID_SD_EMMC_C>, 1984 <&clkc CLKID_SD_EMMC_C_CLK0>, 1985 <&clkc CLKID_FCLK_DIV2>; 1986 clock-names = "core", "clkin0", "clkin1"; 1987 resets = <&reset RESET_SD_EMMC_C>; 1988 }; 1989 1990 usb: usb@ffe09000 { 1991 status = "disabled"; 1992 compatible = "amlogic,meson-g12a-usb-ctrl"; 1993 reg = <0x0 0xffe09000 0x0 0xa0>; 1994 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1995 #address-cells = <2>; 1996 #size-cells = <2>; 1997 ranges; 1998 1999 clocks = <&clkc CLKID_USB>; 2000 resets = <&reset RESET_USB>; 2001 2002 dr_mode = "otg"; 2003 2004 phys = <&usb2_phy0>, <&usb2_phy1>, 2005 <&usb3_pcie_phy PHY_TYPE_USB3>; 2006 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2007 2008 dwc2: usb@ff400000 { 2009 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2010 reg = <0x0 0xff400000 0x0 0x40000>; 2011 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2012 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2013 clock-names = "ddr"; 2014 phys = <&usb2_phy1>; 2015 dr_mode = "peripheral"; 2016 g-rx-fifo-size = <192>; 2017 g-np-tx-fifo-size = <128>; 2018 g-tx-fifo-size = <128 128 16 16 16>; 2019 }; 2020 2021 dwc3: usb@ff500000 { 2022 compatible = "snps,dwc3"; 2023 reg = <0x0 0xff500000 0x0 0x100000>; 2024 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2025 dr_mode = "host"; 2026 snps,dis_u2_susphy_quirk; 2027 snps,quirk-frame-length-adjustment; 2028 }; 2029 }; 2030 2031 mali: gpu@ffe40000 { 2032 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2033 reg = <0x0 0xffe40000 0x0 0x40000>; 2034 interrupt-parent = <&gic>; 2035 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2038 interrupt-names = "gpu", "mmu", "job"; 2039 clocks = <&clkc CLKID_MALI>; 2040 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2041 2042 /* 2043 * Mali clocking is provided by two identical clock paths 2044 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2045 * free mux to safely change frequency while running. 2046 */ 2047 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2048 <&clkc CLKID_MALI_0>, 2049 <&clkc CLKID_MALI>; /* Glitch free mux */ 2050 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2051 <0>, /* Do Nothing */ 2052 <&clkc CLKID_MALI_0>; 2053 assigned-clock-rates = <0>, /* Do Nothing */ 2054 <800000000>, 2055 <0>; /* Do Nothing */ 2056 }; 2057 }; 2058 2059 timer { 2060 compatible = "arm,armv8-timer"; 2061 interrupts = <GIC_PPI 13 2062 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2063 <GIC_PPI 14 2064 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2065 <GIC_PPI 11 2066 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2067 <GIC_PPI 10 2068 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2069 }; 2070 2071 xtal: xtal-clk { 2072 compatible = "fixed-clock"; 2073 clock-frequency = <24000000>; 2074 clock-output-names = "xtal"; 2075 #clock-cells = <0>; 2076 }; 2077 2078}; 2079