ARM: l2c: check that DT files specify the required "cache-unified" property

This is a required property, and should always be specified.

Signed-off-by: Russell King <rmk+kernel@arm.

ARM: l2c: check that DT files specify the required "cache-unified" property

This is a required property, and should always be specified.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: fix register naming

We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess. Split them out
into those

ARM: l2c: fix register naming

We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess. Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices. Provide full auxiliary control register definitions.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: implement L2C-310 erratum 752271 in core L2C code

Rather than having SoCs work around L2C erratum themselves, move them
into core code. This erratum affects the double linefil

ARM: l2c: implement L2C-310 erratum 752271 in core L2C code

Rather than having SoCs work around L2C erratum themselves, move them
into core code. This erratum affects the double linefill feature which
needs to be disabled for r3p0 to r3p1-50rel0.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: provide generic hook to intercept writes to secure registers

When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort. Platform

ARM: l2c: provide generic hook to intercept writes to secure registers

When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort. Platforms normally have to call
firmware to work around this. Provide a hook for them to intercept
any L2C secure register write.

l2c_write_sec() avoids writes to secure registers which are already set
to the appropriate value, thus avoiding the overhead of needlessly
calling into the secure monitor.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: move way size calculation data into l2c_init_data

Move the way size calculation data (base of way size) out of the
switch statement into the provided initialisation data.

ARM: l2c: move way size calculation data into l2c_init_data

Move the way size calculation data (base of way size) out of the
switch statement into the provided initialisation data.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: add decode for L2C-220 cache ways

Rather than assuming these are always 8-way, it can be decoded from the
auxillary register in the same manner as L2C-210.

Signed-off-

ARM: l2c: add decode for L2C-220 cache ways

Rather than assuming these are always 8-way, it can be decoded from the
auxillary register in the same manner as L2C-210.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: move type string into l2c_init_data structure

Rather than decoding this from the ID register, store it in the
l2c_init_data structure. This simplifies things some more, and

ARM: l2c: move type string into l2c_init_data structure

Rather than decoding this from the ID register, store it in the
l2c_init_data structure. This simplifies things some more, and
allows us to better provide further details as to how we're
driving the cache. We print the cache ID value anyway should we
need to precisely identify the cache hardware.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: remove obsolete l2x0 ops for non-OF init

non-OF initialisation has never been used with any cache controller
which isn't an ARM cache controller, so we can safely get rid of th

ARM: l2c: remove obsolete l2x0 ops for non-OF init

non-OF initialisation has never been used with any cache controller
which isn't an ARM cache controller, so we can safely get rid of the
old (and buggy) l2x0_*-based operations structure.

This is also the last reference to:
- l2x0_clean_line()
- l2x0_inv_line()
- l2x0_flush_line()
- l2x0_flush_all()
- l2x0_clean_all()
- l2x0_inv_all()
- l2x0_inv_range()
- l2x0_clean_range()
- l2x0_flush_range()
- l2x0_enable()
- l2x0_resume()
so kill those functions too.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: convert Broadcom L2C-310 to new code

The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later. These
require no errata workarounds, and so we can directly call the l2c210

ARM: l2c: convert Broadcom L2C-310 to new code

The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later. These
require no errata workarounds, and so we can directly call the l2c210
functions from their methods.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: add L2C-220 specific handlers

The L2C-220 is different from the L2C-210 and L2C-310 in that every
operation is a background operation: this means we have to use
spinlocks t

ARM: l2c: add L2C-220 specific handlers

The L2C-220 is different from the L2C-210 and L2C-310 in that every
operation is a background operation: this means we have to use
spinlocks to protect all operations, and we have to wait for every
operation to complete.

Should a second operation be attempted while a previous operation
is in progress, the response will be an imprecise abort.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementations

Where no errata affect the L2C-310 handlers, they are functionally
equivalent to L2C-210. Re-use the L2C-210 handl

ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementations

Where no errata affect the L2C-310 handlers, they are functionally
equivalent to L2C-210. Re-use the L2C-210 handlers for the L2C-310
part.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: implement L2C-310 erratum 588369 as a method override

Implement L2C-310 erratum 588369 by overriding the invalidate range
and flush range methods in the outer_cache operations

ARM: l2c: implement L2C-310 erratum 588369 as a method override

Implement L2C-310 erratum 588369 by overriding the invalidate range
and flush range methods in the outer_cache operations structure.
This allows us to sensibly contain the erratum code in one place
without affecting other locations/implemetations.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: implement L2C-310 erratum 727915 as a method override

Implement L2C-310 erratum 727915 by overriding the flush_all method
in the outer_cache operations structure. This allows

ARM: l2c: implement L2C-310 erratum 727915 as a method override

Implement L2C-310 erratum 727915 by overriding the flush_all method
in the outer_cache operations structure. This allows us to sensibly
contain the erratum code in one place without affecting other
locations or implementations.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: add L2C-210 specific handlers

Add L2C-210 specific cache operation handlers. These are tailored to
the requirements of the L2C-210 cache controller, which doesn't
require

ARM: l2c: add L2C-210 specific handlers

Add L2C-210 specific cache operation handlers. These are tailored to
the requirements of the L2C-210 cache controller, which doesn't
require any workarounds. We avoid using the way operations during
normal operation, which means we can avoid locking: the only time
we use the way operations are during initialisation, and when
disabling the cache.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: move pl310_set_debug() into l2c-310 code

Move the pl310_set_debug() into the l2c-310 code area, and don't hide
it with ifdefs. Rename it to l2c310_set_debug().

Signed

ARM: l2c: move pl310_set_debug() into l2c-310 code

Move the pl310_set_debug() into the l2c-310 code area, and don't hide
it with ifdefs. Rename it to l2c310_set_debug().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: simplify l2x0 unlocking code

The l2x0 unlocking code is only called from l2x0_enable() now, so move
the logic entirely into that function and simplify it.

Signed-off-b

ARM: l2c: simplify l2x0 unlocking code

The l2x0 unlocking code is only called from l2x0_enable() now, so move
the logic entirely into that function and simplify it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: clean up save/resume functions

Rename the pl310 save/resume functions to have a l2c310 prefix - this
is it's official name. Use a local cached copy of the l2x0_base
virtua

ARM: l2c: clean up save/resume functions

Rename the pl310 save/resume functions to have a l2c310 prefix - this
is it's official name. Use a local cached copy of the l2x0_base
virtual address, and also realise that many of the resume function
tails are the same as the enable functions, so make a call to the
enable function instead of duplicating that code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OF

Add the save/resume code hooks to the non-OF implementations as well.
There's no reason for the non-OF implementatio

ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OF

Add the save/resume code hooks to the non-OF implementations as well.
There's no reason for the non-OF implementations to be any different
from the OF implementations.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: clean up L2 cache initialisation messages

Make one of them purely "English", and the other purely technical.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: l2c: implement fixups for L2 cache controller quirks/errata

Rather than putting quirk handling in __l2c_init(), move it out to a
separate function which individual implementations c

ARM: l2c: implement fixups for L2 cache controller quirks/errata

Rather than putting quirk handling in __l2c_init(), move it out to a
separate function which individual implementations can specify. This
helps to localise the quirks to those implementations which require
them.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: move aurora broadcast setup to enable function

Rather than having this hacked into the OF initialiation function, we
can handle this via the enable function instead. While her

ARM: l2c: move aurora broadcast setup to enable function

Rather than having this hacked into the OF initialiation function, we
can handle this via the enable function instead. While here, clean
up that code and comments a little.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: only write the auxiliary control register if required

Avoid unnecessary writes to the auxiliary control register if the
register already contains the required value. This allo

ARM: l2c: only write the auxiliary control register if required

Avoid unnecessary writes to the auxiliary control register if the
register already contains the required value. This allows us to
avoid invoking the platforms secure monitor code unnecessarily.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: write auxctrl register before unlocking

We should write the auxillary control register before unlocking: the
write may be necessary to enable non-secure access to the lock

ARM: l2c: write auxctrl register before unlocking

We should write the auxillary control register before unlocking: the
write may be necessary to enable non-secure access to the lock
registers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: provide enable method

Providing an enable method gives L2 cache controllers a chance to do
special handling at enable time. This allows us to remove a hack in
l2x0_unlock(

ARM: l2c: provide enable method

Providing an enable method gives L2 cache controllers a chance to do
special handling at enable time. This allows us to remove a hack in
l2x0_unlock() for Marvell Aurora L2 caches.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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ARM: l2c: group implementation specific code together

Back in the mists of time, someone decided that it would be a good idea
to group like functions together - so all the save functions

ARM: l2c: group implementation specific code together

Back in the mists of time, someone decided that it would be a good idea
to group like functions together - so all the save functions in one
place, all the resume functions in another, all the OF parsing functions
some place else.

This makes it difficult to get an overview on what a particular
implementation is doing - grouping an implementations specific functions
together makes more sense, because you can see what it's doing without
the clutter of other implementations.

Organise it according to implementation.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

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