1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/spinlock.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_address.h> 25 26 #include <asm/cacheflush.h> 27 #include <asm/hardware/cache-l2x0.h> 28 #include "cache-tauros3.h" 29 #include "cache-aurora-l2.h" 30 31 struct l2c_init_data { 32 unsigned num_lock; 33 void (*of_parse)(const struct device_node *, u32 *, u32 *); 34 void (*enable)(void __iomem *, u32, unsigned); 35 void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); 36 void (*save)(void __iomem *); 37 struct outer_cache_fns outer_cache; 38 }; 39 40 #define CACHE_LINE_SIZE 32 41 42 static void __iomem *l2x0_base; 43 static DEFINE_RAW_SPINLOCK(l2x0_lock); 44 static u32 l2x0_way_mask; /* Bitmask of active ways */ 45 static u32 l2x0_size; 46 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; 47 48 struct l2x0_regs l2x0_saved_regs; 49 50 /* 51 * Common code for all cache controllers. 52 */ 53 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) 54 { 55 /* wait for cache operation by line or way to complete */ 56 while (readl_relaxed(reg) & mask) 57 cpu_relax(); 58 } 59 60 /* 61 * This should only be called when we have a requirement that the 62 * register be written due to a work-around, as platforms running 63 * in non-secure mode may not be able to access this register. 64 */ 65 static inline void l2c_set_debug(void __iomem *base, unsigned long val) 66 { 67 outer_cache.set_debug(val); 68 } 69 70 static void __l2c_op_way(void __iomem *reg) 71 { 72 writel_relaxed(l2x0_way_mask, reg); 73 l2c_wait_mask(reg, l2x0_way_mask); 74 } 75 76 static inline void l2c_unlock(void __iomem *base, unsigned num) 77 { 78 unsigned i; 79 80 for (i = 0; i < num; i++) { 81 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + 82 i * L2X0_LOCKDOWN_STRIDE); 83 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + 84 i * L2X0_LOCKDOWN_STRIDE); 85 } 86 } 87 88 /* 89 * Enable the L2 cache controller. This function must only be 90 * called when the cache controller is known to be disabled. 91 */ 92 static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) 93 { 94 unsigned long flags; 95 96 /* Only write the aux register if it needs changing */ 97 if (readl_relaxed(base + L2X0_AUX_CTRL) != aux) 98 writel_relaxed(aux, base + L2X0_AUX_CTRL); 99 100 l2c_unlock(base, num_lock); 101 102 local_irq_save(flags); 103 __l2c_op_way(base + L2X0_INV_WAY); 104 writel_relaxed(0, base + sync_reg_offset); 105 l2c_wait_mask(base + sync_reg_offset, 1); 106 local_irq_restore(flags); 107 108 writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL); 109 } 110 111 static void l2c_disable(void) 112 { 113 void __iomem *base = l2x0_base; 114 115 outer_cache.flush_all(); 116 writel_relaxed(0, base + L2X0_CTRL); 117 dsb(st); 118 } 119 120 #ifdef CONFIG_CACHE_PL310 121 static inline void cache_wait(void __iomem *reg, unsigned long mask) 122 { 123 /* cache operations by line are atomic on PL310 */ 124 } 125 #else 126 #define cache_wait l2c_wait_mask 127 #endif 128 129 static inline void cache_sync(void) 130 { 131 void __iomem *base = l2x0_base; 132 133 writel_relaxed(0, base + sync_reg_offset); 134 cache_wait(base + L2X0_CACHE_SYNC, 1); 135 } 136 137 static inline void l2x0_clean_line(unsigned long addr) 138 { 139 void __iomem *base = l2x0_base; 140 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 141 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 142 } 143 144 static inline void l2x0_inv_line(unsigned long addr) 145 { 146 void __iomem *base = l2x0_base; 147 cache_wait(base + L2X0_INV_LINE_PA, 1); 148 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 149 } 150 151 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) 152 static inline void debug_writel(unsigned long val) 153 { 154 if (outer_cache.set_debug) 155 l2c_set_debug(l2x0_base, val); 156 } 157 #else 158 /* Optimised out for non-errata case */ 159 static inline void debug_writel(unsigned long val) 160 { 161 } 162 #endif 163 164 #ifdef CONFIG_PL310_ERRATA_588369 165 static inline void l2x0_flush_line(unsigned long addr) 166 { 167 void __iomem *base = l2x0_base; 168 169 /* Clean by PA followed by Invalidate by PA */ 170 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 171 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 172 cache_wait(base + L2X0_INV_LINE_PA, 1); 173 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 174 } 175 #else 176 177 static inline void l2x0_flush_line(unsigned long addr) 178 { 179 void __iomem *base = l2x0_base; 180 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 181 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); 182 } 183 #endif 184 185 static void l2x0_cache_sync(void) 186 { 187 unsigned long flags; 188 189 raw_spin_lock_irqsave(&l2x0_lock, flags); 190 cache_sync(); 191 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 192 } 193 194 static void __l2x0_flush_all(void) 195 { 196 debug_writel(0x03); 197 __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY); 198 cache_sync(); 199 debug_writel(0x00); 200 } 201 202 static void l2x0_flush_all(void) 203 { 204 unsigned long flags; 205 206 /* clean all ways */ 207 raw_spin_lock_irqsave(&l2x0_lock, flags); 208 __l2x0_flush_all(); 209 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 210 } 211 212 static void l2x0_clean_all(void) 213 { 214 unsigned long flags; 215 216 /* clean all ways */ 217 raw_spin_lock_irqsave(&l2x0_lock, flags); 218 __l2c_op_way(l2x0_base + L2X0_CLEAN_WAY); 219 cache_sync(); 220 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 221 } 222 223 static void l2x0_inv_all(void) 224 { 225 unsigned long flags; 226 227 /* invalidate all ways */ 228 raw_spin_lock_irqsave(&l2x0_lock, flags); 229 /* Invalidating when L2 is enabled is a nono */ 230 BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN); 231 __l2c_op_way(l2x0_base + L2X0_INV_WAY); 232 cache_sync(); 233 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 234 } 235 236 static void l2x0_inv_range(unsigned long start, unsigned long end) 237 { 238 void __iomem *base = l2x0_base; 239 unsigned long flags; 240 241 raw_spin_lock_irqsave(&l2x0_lock, flags); 242 if (start & (CACHE_LINE_SIZE - 1)) { 243 start &= ~(CACHE_LINE_SIZE - 1); 244 debug_writel(0x03); 245 l2x0_flush_line(start); 246 debug_writel(0x00); 247 start += CACHE_LINE_SIZE; 248 } 249 250 if (end & (CACHE_LINE_SIZE - 1)) { 251 end &= ~(CACHE_LINE_SIZE - 1); 252 debug_writel(0x03); 253 l2x0_flush_line(end); 254 debug_writel(0x00); 255 } 256 257 while (start < end) { 258 unsigned long blk_end = start + min(end - start, 4096UL); 259 260 while (start < blk_end) { 261 l2x0_inv_line(start); 262 start += CACHE_LINE_SIZE; 263 } 264 265 if (blk_end < end) { 266 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 267 raw_spin_lock_irqsave(&l2x0_lock, flags); 268 } 269 } 270 cache_wait(base + L2X0_INV_LINE_PA, 1); 271 cache_sync(); 272 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 273 } 274 275 static void l2x0_clean_range(unsigned long start, unsigned long end) 276 { 277 void __iomem *base = l2x0_base; 278 unsigned long flags; 279 280 if ((end - start) >= l2x0_size) { 281 l2x0_clean_all(); 282 return; 283 } 284 285 raw_spin_lock_irqsave(&l2x0_lock, flags); 286 start &= ~(CACHE_LINE_SIZE - 1); 287 while (start < end) { 288 unsigned long blk_end = start + min(end - start, 4096UL); 289 290 while (start < blk_end) { 291 l2x0_clean_line(start); 292 start += CACHE_LINE_SIZE; 293 } 294 295 if (blk_end < end) { 296 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 297 raw_spin_lock_irqsave(&l2x0_lock, flags); 298 } 299 } 300 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 301 cache_sync(); 302 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 303 } 304 305 static void l2x0_flush_range(unsigned long start, unsigned long end) 306 { 307 void __iomem *base = l2x0_base; 308 unsigned long flags; 309 310 if ((end - start) >= l2x0_size) { 311 l2x0_flush_all(); 312 return; 313 } 314 315 raw_spin_lock_irqsave(&l2x0_lock, flags); 316 start &= ~(CACHE_LINE_SIZE - 1); 317 while (start < end) { 318 unsigned long blk_end = start + min(end - start, 4096UL); 319 320 debug_writel(0x03); 321 while (start < blk_end) { 322 l2x0_flush_line(start); 323 start += CACHE_LINE_SIZE; 324 } 325 debug_writel(0x00); 326 327 if (blk_end < end) { 328 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 329 raw_spin_lock_irqsave(&l2x0_lock, flags); 330 } 331 } 332 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 333 cache_sync(); 334 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 335 } 336 337 static void l2x0_disable(void) 338 { 339 unsigned long flags; 340 341 raw_spin_lock_irqsave(&l2x0_lock, flags); 342 __l2x0_flush_all(); 343 writel_relaxed(0, l2x0_base + L2X0_CTRL); 344 dsb(st); 345 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 346 } 347 348 static void l2x0_enable(void __iomem *base, u32 aux, unsigned num_lock) 349 { 350 unsigned id; 351 352 id = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_PART_MASK; 353 if (id == L2X0_CACHE_ID_PART_L310) 354 num_lock = 8; 355 else 356 num_lock = 1; 357 358 /* l2x0 controller is disabled */ 359 writel_relaxed(aux, base + L2X0_AUX_CTRL); 360 361 /* Make sure that I&D is not locked down when starting */ 362 l2c_unlock(base, num_lock); 363 364 l2x0_inv_all(); 365 366 /* enable L2X0 */ 367 writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL); 368 } 369 370 static void l2x0_resume(void) 371 { 372 void __iomem *base = l2x0_base; 373 374 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) 375 l2x0_enable(base, l2x0_saved_regs.aux_ctrl, 0); 376 } 377 378 static const struct l2c_init_data l2x0_init_fns __initconst = { 379 .enable = l2x0_enable, 380 .outer_cache = { 381 .inv_range = l2x0_inv_range, 382 .clean_range = l2x0_clean_range, 383 .flush_range = l2x0_flush_range, 384 .flush_all = l2x0_flush_all, 385 .disable = l2x0_disable, 386 .sync = l2x0_cache_sync, 387 .resume = l2x0_resume, 388 }, 389 }; 390 391 /* 392 * L2C-210 specific code. 393 * 394 * The L2C-2x0 PA, set/way and sync operations are atomic, but we must 395 * ensure that no background operation is running. The way operations 396 * are all background tasks. 397 * 398 * While a background operation is in progress, any new operation is 399 * ignored (unspecified whether this causes an error.) Thankfully, not 400 * used on SMP. 401 * 402 * Never has a different sync register other than L2X0_CACHE_SYNC, but 403 * we use sync_reg_offset here so we can share some of this with L2C-310. 404 */ 405 static void __l2c210_cache_sync(void __iomem *base) 406 { 407 writel_relaxed(0, base + sync_reg_offset); 408 } 409 410 static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, 411 unsigned long end) 412 { 413 while (start < end) { 414 writel_relaxed(start, reg); 415 start += CACHE_LINE_SIZE; 416 } 417 } 418 419 static void l2c210_inv_range(unsigned long start, unsigned long end) 420 { 421 void __iomem *base = l2x0_base; 422 423 if (start & (CACHE_LINE_SIZE - 1)) { 424 start &= ~(CACHE_LINE_SIZE - 1); 425 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); 426 start += CACHE_LINE_SIZE; 427 } 428 429 if (end & (CACHE_LINE_SIZE - 1)) { 430 end &= ~(CACHE_LINE_SIZE - 1); 431 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); 432 } 433 434 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); 435 __l2c210_cache_sync(base); 436 } 437 438 static void l2c210_clean_range(unsigned long start, unsigned long end) 439 { 440 void __iomem *base = l2x0_base; 441 442 start &= ~(CACHE_LINE_SIZE - 1); 443 __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end); 444 __l2c210_cache_sync(base); 445 } 446 447 static void l2c210_flush_range(unsigned long start, unsigned long end) 448 { 449 void __iomem *base = l2x0_base; 450 451 start &= ~(CACHE_LINE_SIZE - 1); 452 __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end); 453 __l2c210_cache_sync(base); 454 } 455 456 static void l2c210_flush_all(void) 457 { 458 void __iomem *base = l2x0_base; 459 460 BUG_ON(!irqs_disabled()); 461 462 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 463 __l2c210_cache_sync(base); 464 } 465 466 static void l2c210_sync(void) 467 { 468 __l2c210_cache_sync(l2x0_base); 469 } 470 471 static void l2c210_resume(void) 472 { 473 void __iomem *base = l2x0_base; 474 475 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) 476 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1); 477 } 478 479 static const struct l2c_init_data l2c210_data __initconst = { 480 .num_lock = 1, 481 .enable = l2c_enable, 482 .outer_cache = { 483 .inv_range = l2c210_inv_range, 484 .clean_range = l2c210_clean_range, 485 .flush_range = l2c210_flush_range, 486 .flush_all = l2c210_flush_all, 487 .disable = l2c_disable, 488 .sync = l2c210_sync, 489 .resume = l2c210_resume, 490 }, 491 }; 492 493 /* 494 * L2C-310 specific code. 495 * 496 * Errata: 497 * 588369: PL310 R0P0->R1P0, fixed R2P0. 498 * Affects: all clean+invalidate operations 499 * clean and invalidate skips the invalidate step, so we need to issue 500 * separate operations. We also require the above debug workaround 501 * enclosing this code fragment on affected parts. On unaffected parts, 502 * we must not use this workaround without the debug register writes 503 * to avoid exposing a problem similar to 727915. 504 * 505 * 727915: PL310 R2P0->R3P0, fixed R3P1. 506 * Affects: clean+invalidate by way 507 * clean and invalidate by way runs in the background, and a store can 508 * hit the line between the clean operation and invalidate operation, 509 * resulting in the store being lost. 510 * 511 * 753970: PL310 R3P0, fixed R3P1. 512 * Affects: sync 513 * prevents merging writes after the sync operation, until another L2C 514 * operation is performed (or a number of other conditions.) 515 * 516 * 769419: PL310 R0P0->R3P1, fixed R3P2. 517 * Affects: store buffer 518 * store buffer is not automatically drained. 519 */ 520 static void l2c310_set_debug(unsigned long val) 521 { 522 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); 523 } 524 525 static void __init l2c310_save(void __iomem *base) 526 { 527 unsigned revision; 528 529 l2x0_saved_regs.tag_latency = readl_relaxed(base + 530 L2X0_TAG_LATENCY_CTRL); 531 l2x0_saved_regs.data_latency = readl_relaxed(base + 532 L2X0_DATA_LATENCY_CTRL); 533 l2x0_saved_regs.filter_end = readl_relaxed(base + 534 L2X0_ADDR_FILTER_END); 535 l2x0_saved_regs.filter_start = readl_relaxed(base + 536 L2X0_ADDR_FILTER_START); 537 538 revision = readl_relaxed(base + L2X0_CACHE_ID) & 539 L2X0_CACHE_ID_RTL_MASK; 540 541 /* From r2p0, there is Prefetch offset/control register */ 542 if (revision >= L310_CACHE_ID_RTL_R2P0) 543 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + 544 L2X0_PREFETCH_CTRL); 545 546 /* From r3p0, there is Power control register */ 547 if (revision >= L310_CACHE_ID_RTL_R3P0) 548 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + 549 L2X0_POWER_CTRL); 550 } 551 552 static void l2c310_resume(void) 553 { 554 void __iomem *base = l2x0_base; 555 556 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 557 unsigned revision; 558 559 /* restore pl310 setup */ 560 writel_relaxed(l2x0_saved_regs.tag_latency, 561 base + L2X0_TAG_LATENCY_CTRL); 562 writel_relaxed(l2x0_saved_regs.data_latency, 563 base + L2X0_DATA_LATENCY_CTRL); 564 writel_relaxed(l2x0_saved_regs.filter_end, 565 base + L2X0_ADDR_FILTER_END); 566 writel_relaxed(l2x0_saved_regs.filter_start, 567 base + L2X0_ADDR_FILTER_START); 568 569 revision = readl_relaxed(base + L2X0_CACHE_ID) & 570 L2X0_CACHE_ID_RTL_MASK; 571 572 if (revision >= L310_CACHE_ID_RTL_R2P0) 573 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 574 base + L2X0_PREFETCH_CTRL); 575 if (revision >= L310_CACHE_ID_RTL_R3P0) 576 writel_relaxed(l2x0_saved_regs.pwr_ctrl, 577 base + L2X0_POWER_CTRL); 578 579 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8); 580 } 581 } 582 583 static void __init l2c310_fixup(void __iomem *base, u32 cache_id, 584 struct outer_cache_fns *fns) 585 { 586 unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK; 587 const char *errata[4]; 588 unsigned n = 0; 589 590 if (revision <= L310_CACHE_ID_RTL_R3P0) 591 fns->set_debug = l2c310_set_debug; 592 593 if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) && 594 revision == L310_CACHE_ID_RTL_R3P0) { 595 sync_reg_offset = L2X0_DUMMY_REG; 596 errata[n++] = "753970"; 597 } 598 599 if (IS_ENABLED(CONFIG_PL310_ERRATA_769419)) 600 errata[n++] = "769419"; 601 602 if (n) { 603 unsigned i; 604 605 pr_info("L2C-310 errat%s", n > 1 ? "a" : "um"); 606 for (i = 0; i < n; i++) 607 pr_cont(" %s", errata[i]); 608 pr_cont(" enabled\n"); 609 } 610 } 611 612 static const struct l2c_init_data l2c310_init_fns __initconst = { 613 .num_lock = 8, 614 .enable = l2c_enable, 615 .fixup = l2c310_fixup, 616 .save = l2c310_save, 617 .outer_cache = { 618 .inv_range = l2x0_inv_range, 619 .clean_range = l2x0_clean_range, 620 .flush_range = l2x0_flush_range, 621 .flush_all = l2x0_flush_all, 622 .disable = l2x0_disable, 623 .sync = l2x0_cache_sync, 624 .resume = l2c310_resume, 625 }, 626 }; 627 628 static void __init __l2c_init(const struct l2c_init_data *data, 629 u32 aux_val, u32 aux_mask, u32 cache_id) 630 { 631 struct outer_cache_fns fns; 632 u32 aux; 633 u32 way_size = 0; 634 int ways; 635 int way_size_shift = L2X0_WAY_SIZE_SHIFT; 636 const char *type; 637 638 /* 639 * It is strange to save the register state before initialisation, 640 * but hey, this is what the DT implementations decided to do. 641 */ 642 if (data->save) 643 data->save(l2x0_base); 644 645 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 646 647 aux &= aux_mask; 648 aux |= aux_val; 649 650 /* Determine the number of ways */ 651 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 652 case L2X0_CACHE_ID_PART_L310: 653 if (aux & (1 << 16)) 654 ways = 16; 655 else 656 ways = 8; 657 type = "L310"; 658 break; 659 660 case L2X0_CACHE_ID_PART_L210: 661 ways = (aux >> 13) & 0xf; 662 type = "L210"; 663 break; 664 665 case AURORA_CACHE_ID: 666 ways = (aux >> 13) & 0xf; 667 ways = 2 << ((ways + 1) >> 2); 668 way_size_shift = AURORA_WAY_SIZE_SHIFT; 669 type = "Aurora"; 670 break; 671 672 default: 673 /* Assume unknown chips have 8 ways */ 674 ways = 8; 675 type = "L2x0 series"; 676 break; 677 } 678 679 l2x0_way_mask = (1 << ways) - 1; 680 681 /* 682 * L2 cache Size = Way size * Number of ways 683 */ 684 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; 685 way_size = 1 << (way_size + way_size_shift); 686 687 l2x0_size = ways * way_size * SZ_1K; 688 689 fns = data->outer_cache; 690 if (data->fixup) 691 data->fixup(l2x0_base, cache_id, &fns); 692 693 /* 694 * Check if l2x0 controller is already enabled. If we are booting 695 * in non-secure mode accessing the below registers will fault. 696 */ 697 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 698 data->enable(l2x0_base, aux, data->num_lock); 699 700 /* Re-read it in case some bits are reserved. */ 701 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 702 703 /* Save the value for resuming. */ 704 l2x0_saved_regs.aux_ctrl = aux; 705 706 outer_cache = fns; 707 708 pr_info("%s cache controller enabled, %d ways, %d kB\n", 709 type, ways, l2x0_size >> 10); 710 pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", 711 type, cache_id, aux); 712 } 713 714 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) 715 { 716 const struct l2c_init_data *data; 717 u32 cache_id; 718 719 l2x0_base = base; 720 721 cache_id = readl_relaxed(base + L2X0_CACHE_ID); 722 723 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 724 default: 725 data = &l2x0_init_fns; 726 break; 727 728 case L2X0_CACHE_ID_PART_L210: 729 data = &l2c210_data; 730 break; 731 732 case L2X0_CACHE_ID_PART_L310: 733 data = &l2c310_init_fns; 734 break; 735 } 736 737 __l2c_init(data, aux_val, aux_mask, cache_id); 738 } 739 740 #ifdef CONFIG_OF 741 static int l2_wt_override; 742 743 /* Aurora don't have the cache ID register available, so we have to 744 * pass it though the device tree */ 745 static u32 cache_id_part_number_from_dt; 746 747 static void __init l2x0_of_parse(const struct device_node *np, 748 u32 *aux_val, u32 *aux_mask) 749 { 750 u32 data[2] = { 0, 0 }; 751 u32 tag = 0; 752 u32 dirty = 0; 753 u32 val = 0, mask = 0; 754 755 of_property_read_u32(np, "arm,tag-latency", &tag); 756 if (tag) { 757 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; 758 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; 759 } 760 761 of_property_read_u32_array(np, "arm,data-latency", 762 data, ARRAY_SIZE(data)); 763 if (data[0] && data[1]) { 764 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | 765 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; 766 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | 767 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); 768 } 769 770 of_property_read_u32(np, "arm,dirty-latency", &dirty); 771 if (dirty) { 772 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; 773 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; 774 } 775 776 *aux_val &= ~mask; 777 *aux_val |= val; 778 *aux_mask &= ~mask; 779 } 780 781 static const struct l2c_init_data of_l2c210_data __initconst = { 782 .num_lock = 1, 783 .of_parse = l2x0_of_parse, 784 .enable = l2c_enable, 785 .outer_cache = { 786 .inv_range = l2c210_inv_range, 787 .clean_range = l2c210_clean_range, 788 .flush_range = l2c210_flush_range, 789 .flush_all = l2c210_flush_all, 790 .disable = l2c_disable, 791 .sync = l2c210_sync, 792 .resume = l2c210_resume, 793 }, 794 }; 795 796 static const struct l2c_init_data of_l2x0_data __initconst = { 797 .of_parse = l2x0_of_parse, 798 .enable = l2x0_enable, 799 .outer_cache = { 800 .inv_range = l2x0_inv_range, 801 .clean_range = l2x0_clean_range, 802 .flush_range = l2x0_flush_range, 803 .flush_all = l2x0_flush_all, 804 .disable = l2x0_disable, 805 .sync = l2x0_cache_sync, 806 .resume = l2x0_resume, 807 }, 808 }; 809 810 static void __init pl310_of_parse(const struct device_node *np, 811 u32 *aux_val, u32 *aux_mask) 812 { 813 u32 data[3] = { 0, 0, 0 }; 814 u32 tag[3] = { 0, 0, 0 }; 815 u32 filter[2] = { 0, 0 }; 816 817 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 818 if (tag[0] && tag[1] && tag[2]) 819 writel_relaxed( 820 ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | 821 ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | 822 ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), 823 l2x0_base + L2X0_TAG_LATENCY_CTRL); 824 825 of_property_read_u32_array(np, "arm,data-latency", 826 data, ARRAY_SIZE(data)); 827 if (data[0] && data[1] && data[2]) 828 writel_relaxed( 829 ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | 830 ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | 831 ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), 832 l2x0_base + L2X0_DATA_LATENCY_CTRL); 833 834 of_property_read_u32_array(np, "arm,filter-ranges", 835 filter, ARRAY_SIZE(filter)); 836 if (filter[1]) { 837 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), 838 l2x0_base + L2X0_ADDR_FILTER_END); 839 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, 840 l2x0_base + L2X0_ADDR_FILTER_START); 841 } 842 } 843 844 static const struct l2c_init_data of_pl310_data __initconst = { 845 .num_lock = 8, 846 .of_parse = pl310_of_parse, 847 .enable = l2c_enable, 848 .fixup = l2c310_fixup, 849 .save = l2c310_save, 850 .outer_cache = { 851 .inv_range = l2x0_inv_range, 852 .clean_range = l2x0_clean_range, 853 .flush_range = l2x0_flush_range, 854 .flush_all = l2x0_flush_all, 855 .disable = l2x0_disable, 856 .sync = l2x0_cache_sync, 857 .resume = l2c310_resume, 858 }, 859 }; 860 861 /* 862 * Note that the end addresses passed to Linux primitives are 863 * noninclusive, while the hardware cache range operations use 864 * inclusive start and end addresses. 865 */ 866 static unsigned long calc_range_end(unsigned long start, unsigned long end) 867 { 868 /* 869 * Limit the number of cache lines processed at once, 870 * since cache range operations stall the CPU pipeline 871 * until completion. 872 */ 873 if (end > start + MAX_RANGE_SIZE) 874 end = start + MAX_RANGE_SIZE; 875 876 /* 877 * Cache range operations can't straddle a page boundary. 878 */ 879 if (end > PAGE_ALIGN(start+1)) 880 end = PAGE_ALIGN(start+1); 881 882 return end; 883 } 884 885 /* 886 * Make sure 'start' and 'end' reference the same page, as L2 is PIPT 887 * and range operations only do a TLB lookup on the start address. 888 */ 889 static void aurora_pa_range(unsigned long start, unsigned long end, 890 unsigned long offset) 891 { 892 unsigned long flags; 893 894 raw_spin_lock_irqsave(&l2x0_lock, flags); 895 writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); 896 writel_relaxed(end, l2x0_base + offset); 897 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 898 899 cache_sync(); 900 } 901 902 static void aurora_inv_range(unsigned long start, unsigned long end) 903 { 904 /* 905 * round start and end adresses up to cache line size 906 */ 907 start &= ~(CACHE_LINE_SIZE - 1); 908 end = ALIGN(end, CACHE_LINE_SIZE); 909 910 /* 911 * Invalidate all full cache lines between 'start' and 'end'. 912 */ 913 while (start < end) { 914 unsigned long range_end = calc_range_end(start, end); 915 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 916 AURORA_INVAL_RANGE_REG); 917 start = range_end; 918 } 919 } 920 921 static void aurora_clean_range(unsigned long start, unsigned long end) 922 { 923 /* 924 * If L2 is forced to WT, the L2 will always be clean and we 925 * don't need to do anything here. 926 */ 927 if (!l2_wt_override) { 928 start &= ~(CACHE_LINE_SIZE - 1); 929 end = ALIGN(end, CACHE_LINE_SIZE); 930 while (start != end) { 931 unsigned long range_end = calc_range_end(start, end); 932 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 933 AURORA_CLEAN_RANGE_REG); 934 start = range_end; 935 } 936 } 937 } 938 939 static void aurora_flush_range(unsigned long start, unsigned long end) 940 { 941 start &= ~(CACHE_LINE_SIZE - 1); 942 end = ALIGN(end, CACHE_LINE_SIZE); 943 while (start != end) { 944 unsigned long range_end = calc_range_end(start, end); 945 /* 946 * If L2 is forced to WT, the L2 will always be clean and we 947 * just need to invalidate. 948 */ 949 if (l2_wt_override) 950 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 951 AURORA_INVAL_RANGE_REG); 952 else 953 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 954 AURORA_FLUSH_RANGE_REG); 955 start = range_end; 956 } 957 } 958 959 static void aurora_save(void __iomem *base) 960 { 961 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); 962 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); 963 } 964 965 static void aurora_resume(void) 966 { 967 void __iomem *base = l2x0_base; 968 969 if (!(readl(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 970 writel_relaxed(l2x0_saved_regs.aux_ctrl, base + L2X0_AUX_CTRL); 971 writel_relaxed(l2x0_saved_regs.ctrl, base + L2X0_CTRL); 972 } 973 } 974 975 /* 976 * For Aurora cache in no outer mode, enable via the CP15 coprocessor 977 * broadcasting of cache commands to L2. 978 */ 979 static void __init aurora_enable_no_outer(void __iomem *base, u32 aux, 980 unsigned num_lock) 981 { 982 u32 u; 983 984 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); 985 u |= AURORA_CTRL_FW; /* Set the FW bit */ 986 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); 987 988 isb(); 989 990 l2c_enable(base, aux, num_lock); 991 } 992 993 static void __init aurora_fixup(void __iomem *base, u32 cache_id, 994 struct outer_cache_fns *fns) 995 { 996 sync_reg_offset = AURORA_SYNC_REG; 997 } 998 999 static void __init aurora_of_parse(const struct device_node *np, 1000 u32 *aux_val, u32 *aux_mask) 1001 { 1002 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; 1003 u32 mask = AURORA_ACR_REPLACEMENT_MASK; 1004 1005 of_property_read_u32(np, "cache-id-part", 1006 &cache_id_part_number_from_dt); 1007 1008 /* Determine and save the write policy */ 1009 l2_wt_override = of_property_read_bool(np, "wt-override"); 1010 1011 if (l2_wt_override) { 1012 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; 1013 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; 1014 } 1015 1016 *aux_val &= ~mask; 1017 *aux_val |= val; 1018 *aux_mask &= ~mask; 1019 } 1020 1021 static const struct l2c_init_data of_aurora_with_outer_data __initconst = { 1022 .num_lock = 4, 1023 .of_parse = aurora_of_parse, 1024 .enable = l2c_enable, 1025 .fixup = aurora_fixup, 1026 .save = aurora_save, 1027 .outer_cache = { 1028 .inv_range = aurora_inv_range, 1029 .clean_range = aurora_clean_range, 1030 .flush_range = aurora_flush_range, 1031 .flush_all = l2x0_flush_all, 1032 .disable = l2x0_disable, 1033 .sync = l2x0_cache_sync, 1034 .resume = aurora_resume, 1035 }, 1036 }; 1037 1038 static const struct l2c_init_data of_aurora_no_outer_data __initconst = { 1039 .num_lock = 4, 1040 .of_parse = aurora_of_parse, 1041 .enable = aurora_enable_no_outer, 1042 .fixup = aurora_fixup, 1043 .save = aurora_save, 1044 .outer_cache = { 1045 .resume = aurora_resume, 1046 }, 1047 }; 1048 1049 /* 1050 * For certain Broadcom SoCs, depending on the address range, different offsets 1051 * need to be added to the address before passing it to L2 for 1052 * invalidation/clean/flush 1053 * 1054 * Section Address Range Offset EMI 1055 * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC 1056 * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS 1057 * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC 1058 * 1059 * When the start and end addresses have crossed two different sections, we 1060 * need to break the L2 operation into two, each within its own section. 1061 * For example, if we need to invalidate addresses starts at 0xBFFF0000 and 1062 * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) 1063 * 0xC0000000 - 0xC0001000 1064 * 1065 * Note 1: 1066 * By breaking a single L2 operation into two, we may potentially suffer some 1067 * performance hit, but keep in mind the cross section case is very rare 1068 * 1069 * Note 2: 1070 * We do not need to handle the case when the start address is in 1071 * Section 1 and the end address is in Section 3, since it is not a valid use 1072 * case 1073 * 1074 * Note 3: 1075 * Section 1 in practical terms can no longer be used on rev A2. Because of 1076 * that the code does not need to handle section 1 at all. 1077 * 1078 */ 1079 #define BCM_SYS_EMI_START_ADDR 0x40000000UL 1080 #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL 1081 1082 #define BCM_SYS_EMI_OFFSET 0x40000000UL 1083 #define BCM_VC_EMI_OFFSET 0x80000000UL 1084 1085 static inline int bcm_addr_is_sys_emi(unsigned long addr) 1086 { 1087 return (addr >= BCM_SYS_EMI_START_ADDR) && 1088 (addr < BCM_VC_EMI_SEC3_START_ADDR); 1089 } 1090 1091 static inline unsigned long bcm_l2_phys_addr(unsigned long addr) 1092 { 1093 if (bcm_addr_is_sys_emi(addr)) 1094 return addr + BCM_SYS_EMI_OFFSET; 1095 else 1096 return addr + BCM_VC_EMI_OFFSET; 1097 } 1098 1099 static void bcm_inv_range(unsigned long start, unsigned long end) 1100 { 1101 unsigned long new_start, new_end; 1102 1103 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1104 1105 if (unlikely(end <= start)) 1106 return; 1107 1108 new_start = bcm_l2_phys_addr(start); 1109 new_end = bcm_l2_phys_addr(end); 1110 1111 /* normal case, no cross section between start and end */ 1112 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1113 l2x0_inv_range(new_start, new_end); 1114 return; 1115 } 1116 1117 /* They cross sections, so it can only be a cross from section 1118 * 2 to section 3 1119 */ 1120 l2x0_inv_range(new_start, 1121 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1122 l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1123 new_end); 1124 } 1125 1126 static void bcm_clean_range(unsigned long start, unsigned long end) 1127 { 1128 unsigned long new_start, new_end; 1129 1130 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1131 1132 if (unlikely(end <= start)) 1133 return; 1134 1135 if ((end - start) >= l2x0_size) { 1136 l2x0_clean_all(); 1137 return; 1138 } 1139 1140 new_start = bcm_l2_phys_addr(start); 1141 new_end = bcm_l2_phys_addr(end); 1142 1143 /* normal case, no cross section between start and end */ 1144 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1145 l2x0_clean_range(new_start, new_end); 1146 return; 1147 } 1148 1149 /* They cross sections, so it can only be a cross from section 1150 * 2 to section 3 1151 */ 1152 l2x0_clean_range(new_start, 1153 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1154 l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1155 new_end); 1156 } 1157 1158 static void bcm_flush_range(unsigned long start, unsigned long end) 1159 { 1160 unsigned long new_start, new_end; 1161 1162 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1163 1164 if (unlikely(end <= start)) 1165 return; 1166 1167 if ((end - start) >= l2x0_size) { 1168 l2x0_flush_all(); 1169 return; 1170 } 1171 1172 new_start = bcm_l2_phys_addr(start); 1173 new_end = bcm_l2_phys_addr(end); 1174 1175 /* normal case, no cross section between start and end */ 1176 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1177 l2x0_flush_range(new_start, new_end); 1178 return; 1179 } 1180 1181 /* They cross sections, so it can only be a cross from section 1182 * 2 to section 3 1183 */ 1184 l2x0_flush_range(new_start, 1185 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1186 l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1187 new_end); 1188 } 1189 1190 static const struct l2c_init_data of_bcm_l2x0_data __initconst = { 1191 .num_lock = 8, 1192 .of_parse = pl310_of_parse, 1193 .enable = l2c_enable, 1194 .fixup = l2c310_fixup, 1195 .save = l2c310_save, 1196 .outer_cache = { 1197 .inv_range = bcm_inv_range, 1198 .clean_range = bcm_clean_range, 1199 .flush_range = bcm_flush_range, 1200 .flush_all = l2x0_flush_all, 1201 .disable = l2x0_disable, 1202 .sync = l2x0_cache_sync, 1203 .resume = l2c310_resume, 1204 }, 1205 }; 1206 1207 static void __init tauros3_save(void __iomem *base) 1208 { 1209 l2x0_saved_regs.aux2_ctrl = 1210 readl_relaxed(base + TAUROS3_AUX2_CTRL); 1211 l2x0_saved_regs.prefetch_ctrl = 1212 readl_relaxed(base + L2X0_PREFETCH_CTRL); 1213 } 1214 1215 static void tauros3_resume(void) 1216 { 1217 void __iomem *base = l2x0_base; 1218 1219 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 1220 writel_relaxed(l2x0_saved_regs.aux2_ctrl, 1221 base + TAUROS3_AUX2_CTRL); 1222 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 1223 base + L2X0_PREFETCH_CTRL); 1224 1225 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8); 1226 } 1227 } 1228 1229 static const struct l2c_init_data of_tauros3_data __initconst = { 1230 .num_lock = 8, 1231 .enable = l2c_enable, 1232 .save = tauros3_save, 1233 /* Tauros3 broadcasts L1 cache operations to L2 */ 1234 .outer_cache = { 1235 .resume = tauros3_resume, 1236 }, 1237 }; 1238 1239 #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } 1240 static const struct of_device_id l2x0_ids[] __initconst = { 1241 L2C_ID("arm,l210-cache", of_l2c210_data), 1242 L2C_ID("arm,l220-cache", of_l2x0_data), 1243 L2C_ID("arm,pl310-cache", of_pl310_data), 1244 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1245 L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data), 1246 L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data), 1247 L2C_ID("marvell,tauros3-cache", of_tauros3_data), 1248 /* Deprecated IDs */ 1249 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1250 {} 1251 }; 1252 1253 int __init l2x0_of_init(u32 aux_val, u32 aux_mask) 1254 { 1255 const struct l2c_init_data *data; 1256 struct device_node *np; 1257 struct resource res; 1258 u32 cache_id; 1259 1260 np = of_find_matching_node(NULL, l2x0_ids); 1261 if (!np) 1262 return -ENODEV; 1263 1264 if (of_address_to_resource(np, 0, &res)) 1265 return -ENODEV; 1266 1267 l2x0_base = ioremap(res.start, resource_size(&res)); 1268 if (!l2x0_base) 1269 return -ENOMEM; 1270 1271 l2x0_saved_regs.phy_base = res.start; 1272 1273 data = of_match_node(l2x0_ids, np)->data; 1274 1275 /* L2 configuration can only be changed if the cache is disabled */ 1276 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 1277 if (data->of_parse) 1278 data->of_parse(np, &aux_val, &aux_mask); 1279 1280 if (cache_id_part_number_from_dt) 1281 cache_id = cache_id_part_number_from_dt; 1282 else 1283 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 1284 1285 __l2c_init(data, aux_val, aux_mask, cache_id); 1286 1287 return 0; 1288 } 1289 #endif 1290