1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/spinlock.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_address.h> 25 26 #include <asm/cacheflush.h> 27 #include <asm/hardware/cache-l2x0.h> 28 #include "cache-tauros3.h" 29 #include "cache-aurora-l2.h" 30 31 struct l2c_init_data { 32 unsigned num_lock; 33 void (*of_parse)(const struct device_node *, u32 *, u32 *); 34 void (*enable)(void __iomem *, u32, unsigned); 35 void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); 36 void (*save)(void __iomem *); 37 struct outer_cache_fns outer_cache; 38 }; 39 40 #define CACHE_LINE_SIZE 32 41 42 static void __iomem *l2x0_base; 43 static DEFINE_RAW_SPINLOCK(l2x0_lock); 44 static u32 l2x0_way_mask; /* Bitmask of active ways */ 45 static u32 l2x0_size; 46 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; 47 48 struct l2x0_regs l2x0_saved_regs; 49 50 /* 51 * Common code for all cache controllers. 52 */ 53 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) 54 { 55 /* wait for cache operation by line or way to complete */ 56 while (readl_relaxed(reg) & mask) 57 cpu_relax(); 58 } 59 60 /* 61 * This should only be called when we have a requirement that the 62 * register be written due to a work-around, as platforms running 63 * in non-secure mode may not be able to access this register. 64 */ 65 static inline void l2c_set_debug(void __iomem *base, unsigned long val) 66 { 67 outer_cache.set_debug(val); 68 } 69 70 static void __l2c_op_way(void __iomem *reg) 71 { 72 writel_relaxed(l2x0_way_mask, reg); 73 l2c_wait_mask(reg, l2x0_way_mask); 74 } 75 76 static inline void l2c_unlock(void __iomem *base, unsigned num) 77 { 78 unsigned i; 79 80 for (i = 0; i < num; i++) { 81 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + 82 i * L2X0_LOCKDOWN_STRIDE); 83 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + 84 i * L2X0_LOCKDOWN_STRIDE); 85 } 86 } 87 88 /* 89 * Enable the L2 cache controller. This function must only be 90 * called when the cache controller is known to be disabled. 91 */ 92 static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) 93 { 94 unsigned long flags; 95 96 /* Only write the aux register if it needs changing */ 97 if (readl_relaxed(base + L2X0_AUX_CTRL) != aux) 98 writel_relaxed(aux, base + L2X0_AUX_CTRL); 99 100 l2c_unlock(base, num_lock); 101 102 local_irq_save(flags); 103 __l2c_op_way(base + L2X0_INV_WAY); 104 writel_relaxed(0, base + sync_reg_offset); 105 l2c_wait_mask(base + sync_reg_offset, 1); 106 local_irq_restore(flags); 107 108 writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL); 109 } 110 111 static void l2c_disable(void) 112 { 113 void __iomem *base = l2x0_base; 114 115 outer_cache.flush_all(); 116 writel_relaxed(0, base + L2X0_CTRL); 117 dsb(st); 118 } 119 120 #ifdef CONFIG_CACHE_PL310 121 static inline void cache_wait(void __iomem *reg, unsigned long mask) 122 { 123 /* cache operations by line are atomic on PL310 */ 124 } 125 #else 126 #define cache_wait l2c_wait_mask 127 #endif 128 129 static inline void cache_sync(void) 130 { 131 void __iomem *base = l2x0_base; 132 133 writel_relaxed(0, base + sync_reg_offset); 134 cache_wait(base + L2X0_CACHE_SYNC, 1); 135 } 136 137 static inline void l2x0_clean_line(unsigned long addr) 138 { 139 void __iomem *base = l2x0_base; 140 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 141 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 142 } 143 144 static inline void l2x0_inv_line(unsigned long addr) 145 { 146 void __iomem *base = l2x0_base; 147 cache_wait(base + L2X0_INV_LINE_PA, 1); 148 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 149 } 150 151 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) 152 static inline void debug_writel(unsigned long val) 153 { 154 if (outer_cache.set_debug) 155 l2c_set_debug(l2x0_base, val); 156 } 157 158 static void pl310_set_debug(unsigned long val) 159 { 160 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); 161 } 162 #else 163 /* Optimised out for non-errata case */ 164 static inline void debug_writel(unsigned long val) 165 { 166 } 167 168 #define pl310_set_debug NULL 169 #endif 170 171 #ifdef CONFIG_PL310_ERRATA_588369 172 static inline void l2x0_flush_line(unsigned long addr) 173 { 174 void __iomem *base = l2x0_base; 175 176 /* Clean by PA followed by Invalidate by PA */ 177 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 178 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 179 cache_wait(base + L2X0_INV_LINE_PA, 1); 180 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 181 } 182 #else 183 184 static inline void l2x0_flush_line(unsigned long addr) 185 { 186 void __iomem *base = l2x0_base; 187 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 188 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); 189 } 190 #endif 191 192 static void l2x0_cache_sync(void) 193 { 194 unsigned long flags; 195 196 raw_spin_lock_irqsave(&l2x0_lock, flags); 197 cache_sync(); 198 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 199 } 200 201 static void __l2x0_flush_all(void) 202 { 203 debug_writel(0x03); 204 __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY); 205 cache_sync(); 206 debug_writel(0x00); 207 } 208 209 static void l2x0_flush_all(void) 210 { 211 unsigned long flags; 212 213 /* clean all ways */ 214 raw_spin_lock_irqsave(&l2x0_lock, flags); 215 __l2x0_flush_all(); 216 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 217 } 218 219 static void l2x0_clean_all(void) 220 { 221 unsigned long flags; 222 223 /* clean all ways */ 224 raw_spin_lock_irqsave(&l2x0_lock, flags); 225 __l2c_op_way(l2x0_base + L2X0_CLEAN_WAY); 226 cache_sync(); 227 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 228 } 229 230 static void l2x0_inv_all(void) 231 { 232 unsigned long flags; 233 234 /* invalidate all ways */ 235 raw_spin_lock_irqsave(&l2x0_lock, flags); 236 /* Invalidating when L2 is enabled is a nono */ 237 BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN); 238 __l2c_op_way(l2x0_base + L2X0_INV_WAY); 239 cache_sync(); 240 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 241 } 242 243 static void l2x0_inv_range(unsigned long start, unsigned long end) 244 { 245 void __iomem *base = l2x0_base; 246 unsigned long flags; 247 248 raw_spin_lock_irqsave(&l2x0_lock, flags); 249 if (start & (CACHE_LINE_SIZE - 1)) { 250 start &= ~(CACHE_LINE_SIZE - 1); 251 debug_writel(0x03); 252 l2x0_flush_line(start); 253 debug_writel(0x00); 254 start += CACHE_LINE_SIZE; 255 } 256 257 if (end & (CACHE_LINE_SIZE - 1)) { 258 end &= ~(CACHE_LINE_SIZE - 1); 259 debug_writel(0x03); 260 l2x0_flush_line(end); 261 debug_writel(0x00); 262 } 263 264 while (start < end) { 265 unsigned long blk_end = start + min(end - start, 4096UL); 266 267 while (start < blk_end) { 268 l2x0_inv_line(start); 269 start += CACHE_LINE_SIZE; 270 } 271 272 if (blk_end < end) { 273 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 274 raw_spin_lock_irqsave(&l2x0_lock, flags); 275 } 276 } 277 cache_wait(base + L2X0_INV_LINE_PA, 1); 278 cache_sync(); 279 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 280 } 281 282 static void l2x0_clean_range(unsigned long start, unsigned long end) 283 { 284 void __iomem *base = l2x0_base; 285 unsigned long flags; 286 287 if ((end - start) >= l2x0_size) { 288 l2x0_clean_all(); 289 return; 290 } 291 292 raw_spin_lock_irqsave(&l2x0_lock, flags); 293 start &= ~(CACHE_LINE_SIZE - 1); 294 while (start < end) { 295 unsigned long blk_end = start + min(end - start, 4096UL); 296 297 while (start < blk_end) { 298 l2x0_clean_line(start); 299 start += CACHE_LINE_SIZE; 300 } 301 302 if (blk_end < end) { 303 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 304 raw_spin_lock_irqsave(&l2x0_lock, flags); 305 } 306 } 307 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 308 cache_sync(); 309 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 310 } 311 312 static void l2x0_flush_range(unsigned long start, unsigned long end) 313 { 314 void __iomem *base = l2x0_base; 315 unsigned long flags; 316 317 if ((end - start) >= l2x0_size) { 318 l2x0_flush_all(); 319 return; 320 } 321 322 raw_spin_lock_irqsave(&l2x0_lock, flags); 323 start &= ~(CACHE_LINE_SIZE - 1); 324 while (start < end) { 325 unsigned long blk_end = start + min(end - start, 4096UL); 326 327 debug_writel(0x03); 328 while (start < blk_end) { 329 l2x0_flush_line(start); 330 start += CACHE_LINE_SIZE; 331 } 332 debug_writel(0x00); 333 334 if (blk_end < end) { 335 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 336 raw_spin_lock_irqsave(&l2x0_lock, flags); 337 } 338 } 339 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 340 cache_sync(); 341 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 342 } 343 344 static void l2x0_disable(void) 345 { 346 unsigned long flags; 347 348 raw_spin_lock_irqsave(&l2x0_lock, flags); 349 __l2x0_flush_all(); 350 writel_relaxed(0, l2x0_base + L2X0_CTRL); 351 dsb(st); 352 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 353 } 354 355 static void l2x0_unlock(u32 cache_id) 356 { 357 int lockregs; 358 359 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 360 case L2X0_CACHE_ID_PART_L310: 361 lockregs = 8; 362 break; 363 default: 364 /* L210 and unknown types */ 365 lockregs = 1; 366 break; 367 } 368 369 l2c_unlock(l2x0_base, lockregs); 370 } 371 372 static void l2x0_enable(void __iomem *base, u32 aux, unsigned num_lock) 373 { 374 /* l2x0 controller is disabled */ 375 writel_relaxed(aux, base + L2X0_AUX_CTRL); 376 377 /* Make sure that I&D is not locked down when starting */ 378 l2x0_unlock(readl_relaxed(base + L2X0_CACHE_ID)); 379 380 l2x0_inv_all(); 381 382 /* enable L2X0 */ 383 writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL); 384 } 385 386 static void l2x0_resume(void) 387 { 388 void __iomem *base = l2x0_base; 389 390 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) 391 l2x0_enable(base, l2x0_saved_regs.aux_ctrl, 0); 392 } 393 394 static const struct l2c_init_data l2x0_init_fns __initconst = { 395 .enable = l2x0_enable, 396 .outer_cache = { 397 .inv_range = l2x0_inv_range, 398 .clean_range = l2x0_clean_range, 399 .flush_range = l2x0_flush_range, 400 .flush_all = l2x0_flush_all, 401 .disable = l2x0_disable, 402 .sync = l2x0_cache_sync, 403 .resume = l2x0_resume, 404 }, 405 }; 406 407 /* 408 * L2C-310 specific code. 409 * 410 * Errata: 411 * 588369: PL310 R0P0->R1P0, fixed R2P0. 412 * Affects: all clean+invalidate operations 413 * clean and invalidate skips the invalidate step, so we need to issue 414 * separate operations. We also require the above debug workaround 415 * enclosing this code fragment on affected parts. On unaffected parts, 416 * we must not use this workaround without the debug register writes 417 * to avoid exposing a problem similar to 727915. 418 * 419 * 727915: PL310 R2P0->R3P0, fixed R3P1. 420 * Affects: clean+invalidate by way 421 * clean and invalidate by way runs in the background, and a store can 422 * hit the line between the clean operation and invalidate operation, 423 * resulting in the store being lost. 424 * 425 * 753970: PL310 R3P0, fixed R3P1. 426 * Affects: sync 427 * prevents merging writes after the sync operation, until another L2C 428 * operation is performed (or a number of other conditions.) 429 * 430 * 769419: PL310 R0P0->R3P1, fixed R3P2. 431 * Affects: store buffer 432 * store buffer is not automatically drained. 433 */ 434 static void __init l2c310_save(void __iomem *base) 435 { 436 unsigned revision; 437 438 l2x0_saved_regs.tag_latency = readl_relaxed(base + 439 L2X0_TAG_LATENCY_CTRL); 440 l2x0_saved_regs.data_latency = readl_relaxed(base + 441 L2X0_DATA_LATENCY_CTRL); 442 l2x0_saved_regs.filter_end = readl_relaxed(base + 443 L2X0_ADDR_FILTER_END); 444 l2x0_saved_regs.filter_start = readl_relaxed(base + 445 L2X0_ADDR_FILTER_START); 446 447 revision = readl_relaxed(base + L2X0_CACHE_ID) & 448 L2X0_CACHE_ID_RTL_MASK; 449 450 /* From r2p0, there is Prefetch offset/control register */ 451 if (revision >= L310_CACHE_ID_RTL_R2P0) 452 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + 453 L2X0_PREFETCH_CTRL); 454 455 /* From r3p0, there is Power control register */ 456 if (revision >= L310_CACHE_ID_RTL_R3P0) 457 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + 458 L2X0_POWER_CTRL); 459 } 460 461 static void l2c310_resume(void) 462 { 463 void __iomem *base = l2x0_base; 464 465 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 466 unsigned revision; 467 468 /* restore pl310 setup */ 469 writel_relaxed(l2x0_saved_regs.tag_latency, 470 base + L2X0_TAG_LATENCY_CTRL); 471 writel_relaxed(l2x0_saved_regs.data_latency, 472 base + L2X0_DATA_LATENCY_CTRL); 473 writel_relaxed(l2x0_saved_regs.filter_end, 474 base + L2X0_ADDR_FILTER_END); 475 writel_relaxed(l2x0_saved_regs.filter_start, 476 base + L2X0_ADDR_FILTER_START); 477 478 revision = readl_relaxed(base + L2X0_CACHE_ID) & 479 L2X0_CACHE_ID_RTL_MASK; 480 481 if (revision >= L310_CACHE_ID_RTL_R2P0) 482 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 483 base + L2X0_PREFETCH_CTRL); 484 if (revision >= L310_CACHE_ID_RTL_R3P0) 485 writel_relaxed(l2x0_saved_regs.pwr_ctrl, 486 base + L2X0_POWER_CTRL); 487 488 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8); 489 } 490 } 491 492 static void __init l2c310_fixup(void __iomem *base, u32 cache_id, 493 struct outer_cache_fns *fns) 494 { 495 unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK; 496 const char *errata[4]; 497 unsigned n = 0; 498 499 if (revision <= L310_CACHE_ID_RTL_R3P0) 500 fns->set_debug = pl310_set_debug; 501 502 if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) && 503 revision == L310_CACHE_ID_RTL_R3P0) { 504 sync_reg_offset = L2X0_DUMMY_REG; 505 errata[n++] = "753970"; 506 } 507 508 if (IS_ENABLED(CONFIG_PL310_ERRATA_769419)) 509 errata[n++] = "769419"; 510 511 if (n) { 512 unsigned i; 513 514 pr_info("L2C-310 errat%s", n > 1 ? "a" : "um"); 515 for (i = 0; i < n; i++) 516 pr_cont(" %s", errata[i]); 517 pr_cont(" enabled\n"); 518 } 519 } 520 521 static const struct l2c_init_data l2c310_init_fns __initconst = { 522 .num_lock = 8, 523 .enable = l2c_enable, 524 .fixup = l2c310_fixup, 525 .save = l2c310_save, 526 .outer_cache = { 527 .inv_range = l2x0_inv_range, 528 .clean_range = l2x0_clean_range, 529 .flush_range = l2x0_flush_range, 530 .flush_all = l2x0_flush_all, 531 .disable = l2x0_disable, 532 .sync = l2x0_cache_sync, 533 .resume = l2c310_resume, 534 }, 535 }; 536 537 static void __init __l2c_init(const struct l2c_init_data *data, 538 u32 aux_val, u32 aux_mask, u32 cache_id) 539 { 540 struct outer_cache_fns fns; 541 u32 aux; 542 u32 way_size = 0; 543 int ways; 544 int way_size_shift = L2X0_WAY_SIZE_SHIFT; 545 const char *type; 546 547 /* 548 * It is strange to save the register state before initialisation, 549 * but hey, this is what the DT implementations decided to do. 550 */ 551 if (data->save) 552 data->save(l2x0_base); 553 554 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 555 556 aux &= aux_mask; 557 aux |= aux_val; 558 559 /* Determine the number of ways */ 560 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 561 case L2X0_CACHE_ID_PART_L310: 562 if (aux & (1 << 16)) 563 ways = 16; 564 else 565 ways = 8; 566 type = "L310"; 567 break; 568 569 case L2X0_CACHE_ID_PART_L210: 570 ways = (aux >> 13) & 0xf; 571 type = "L210"; 572 break; 573 574 case AURORA_CACHE_ID: 575 ways = (aux >> 13) & 0xf; 576 ways = 2 << ((ways + 1) >> 2); 577 way_size_shift = AURORA_WAY_SIZE_SHIFT; 578 type = "Aurora"; 579 break; 580 581 default: 582 /* Assume unknown chips have 8 ways */ 583 ways = 8; 584 type = "L2x0 series"; 585 break; 586 } 587 588 l2x0_way_mask = (1 << ways) - 1; 589 590 /* 591 * L2 cache Size = Way size * Number of ways 592 */ 593 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; 594 way_size = 1 << (way_size + way_size_shift); 595 596 l2x0_size = ways * way_size * SZ_1K; 597 598 fns = data->outer_cache; 599 if (data->fixup) 600 data->fixup(l2x0_base, cache_id, &fns); 601 602 /* 603 * Check if l2x0 controller is already enabled. If we are booting 604 * in non-secure mode accessing the below registers will fault. 605 */ 606 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 607 data->enable(l2x0_base, aux, data->num_lock); 608 609 /* Re-read it in case some bits are reserved. */ 610 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 611 612 /* Save the value for resuming. */ 613 l2x0_saved_regs.aux_ctrl = aux; 614 615 outer_cache = fns; 616 617 pr_info("%s cache controller enabled, %d ways, %d kB\n", 618 type, ways, l2x0_size >> 10); 619 pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", 620 type, cache_id, aux); 621 } 622 623 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) 624 { 625 const struct l2c_init_data *data; 626 u32 cache_id; 627 628 l2x0_base = base; 629 630 cache_id = readl_relaxed(base + L2X0_CACHE_ID); 631 632 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 633 default: 634 data = &l2x0_init_fns; 635 break; 636 637 case L2X0_CACHE_ID_PART_L310: 638 data = &l2c310_init_fns; 639 break; 640 } 641 642 __l2c_init(data, aux_val, aux_mask, cache_id); 643 } 644 645 #ifdef CONFIG_OF 646 static int l2_wt_override; 647 648 /* Aurora don't have the cache ID register available, so we have to 649 * pass it though the device tree */ 650 static u32 cache_id_part_number_from_dt; 651 652 static void __init l2x0_of_parse(const struct device_node *np, 653 u32 *aux_val, u32 *aux_mask) 654 { 655 u32 data[2] = { 0, 0 }; 656 u32 tag = 0; 657 u32 dirty = 0; 658 u32 val = 0, mask = 0; 659 660 of_property_read_u32(np, "arm,tag-latency", &tag); 661 if (tag) { 662 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; 663 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; 664 } 665 666 of_property_read_u32_array(np, "arm,data-latency", 667 data, ARRAY_SIZE(data)); 668 if (data[0] && data[1]) { 669 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | 670 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; 671 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | 672 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); 673 } 674 675 of_property_read_u32(np, "arm,dirty-latency", &dirty); 676 if (dirty) { 677 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; 678 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; 679 } 680 681 *aux_val &= ~mask; 682 *aux_val |= val; 683 *aux_mask &= ~mask; 684 } 685 686 static const struct l2c_init_data of_l2x0_data __initconst = { 687 .of_parse = l2x0_of_parse, 688 .enable = l2x0_enable, 689 .outer_cache = { 690 .inv_range = l2x0_inv_range, 691 .clean_range = l2x0_clean_range, 692 .flush_range = l2x0_flush_range, 693 .flush_all = l2x0_flush_all, 694 .disable = l2x0_disable, 695 .sync = l2x0_cache_sync, 696 .resume = l2x0_resume, 697 }, 698 }; 699 700 static void __init pl310_of_parse(const struct device_node *np, 701 u32 *aux_val, u32 *aux_mask) 702 { 703 u32 data[3] = { 0, 0, 0 }; 704 u32 tag[3] = { 0, 0, 0 }; 705 u32 filter[2] = { 0, 0 }; 706 707 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 708 if (tag[0] && tag[1] && tag[2]) 709 writel_relaxed( 710 ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | 711 ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | 712 ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), 713 l2x0_base + L2X0_TAG_LATENCY_CTRL); 714 715 of_property_read_u32_array(np, "arm,data-latency", 716 data, ARRAY_SIZE(data)); 717 if (data[0] && data[1] && data[2]) 718 writel_relaxed( 719 ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | 720 ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | 721 ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), 722 l2x0_base + L2X0_DATA_LATENCY_CTRL); 723 724 of_property_read_u32_array(np, "arm,filter-ranges", 725 filter, ARRAY_SIZE(filter)); 726 if (filter[1]) { 727 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), 728 l2x0_base + L2X0_ADDR_FILTER_END); 729 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, 730 l2x0_base + L2X0_ADDR_FILTER_START); 731 } 732 } 733 734 static const struct l2c_init_data of_pl310_data __initconst = { 735 .num_lock = 8, 736 .of_parse = pl310_of_parse, 737 .enable = l2c_enable, 738 .fixup = l2c310_fixup, 739 .save = l2c310_save, 740 .outer_cache = { 741 .inv_range = l2x0_inv_range, 742 .clean_range = l2x0_clean_range, 743 .flush_range = l2x0_flush_range, 744 .flush_all = l2x0_flush_all, 745 .disable = l2x0_disable, 746 .sync = l2x0_cache_sync, 747 .resume = l2c310_resume, 748 }, 749 }; 750 751 /* 752 * Note that the end addresses passed to Linux primitives are 753 * noninclusive, while the hardware cache range operations use 754 * inclusive start and end addresses. 755 */ 756 static unsigned long calc_range_end(unsigned long start, unsigned long end) 757 { 758 /* 759 * Limit the number of cache lines processed at once, 760 * since cache range operations stall the CPU pipeline 761 * until completion. 762 */ 763 if (end > start + MAX_RANGE_SIZE) 764 end = start + MAX_RANGE_SIZE; 765 766 /* 767 * Cache range operations can't straddle a page boundary. 768 */ 769 if (end > PAGE_ALIGN(start+1)) 770 end = PAGE_ALIGN(start+1); 771 772 return end; 773 } 774 775 /* 776 * Make sure 'start' and 'end' reference the same page, as L2 is PIPT 777 * and range operations only do a TLB lookup on the start address. 778 */ 779 static void aurora_pa_range(unsigned long start, unsigned long end, 780 unsigned long offset) 781 { 782 unsigned long flags; 783 784 raw_spin_lock_irqsave(&l2x0_lock, flags); 785 writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); 786 writel_relaxed(end, l2x0_base + offset); 787 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 788 789 cache_sync(); 790 } 791 792 static void aurora_inv_range(unsigned long start, unsigned long end) 793 { 794 /* 795 * round start and end adresses up to cache line size 796 */ 797 start &= ~(CACHE_LINE_SIZE - 1); 798 end = ALIGN(end, CACHE_LINE_SIZE); 799 800 /* 801 * Invalidate all full cache lines between 'start' and 'end'. 802 */ 803 while (start < end) { 804 unsigned long range_end = calc_range_end(start, end); 805 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 806 AURORA_INVAL_RANGE_REG); 807 start = range_end; 808 } 809 } 810 811 static void aurora_clean_range(unsigned long start, unsigned long end) 812 { 813 /* 814 * If L2 is forced to WT, the L2 will always be clean and we 815 * don't need to do anything here. 816 */ 817 if (!l2_wt_override) { 818 start &= ~(CACHE_LINE_SIZE - 1); 819 end = ALIGN(end, CACHE_LINE_SIZE); 820 while (start != end) { 821 unsigned long range_end = calc_range_end(start, end); 822 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 823 AURORA_CLEAN_RANGE_REG); 824 start = range_end; 825 } 826 } 827 } 828 829 static void aurora_flush_range(unsigned long start, unsigned long end) 830 { 831 start &= ~(CACHE_LINE_SIZE - 1); 832 end = ALIGN(end, CACHE_LINE_SIZE); 833 while (start != end) { 834 unsigned long range_end = calc_range_end(start, end); 835 /* 836 * If L2 is forced to WT, the L2 will always be clean and we 837 * just need to invalidate. 838 */ 839 if (l2_wt_override) 840 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 841 AURORA_INVAL_RANGE_REG); 842 else 843 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 844 AURORA_FLUSH_RANGE_REG); 845 start = range_end; 846 } 847 } 848 849 static void aurora_save(void __iomem *base) 850 { 851 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); 852 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); 853 } 854 855 static void aurora_resume(void) 856 { 857 void __iomem *base = l2x0_base; 858 859 if (!(readl(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 860 writel_relaxed(l2x0_saved_regs.aux_ctrl, base + L2X0_AUX_CTRL); 861 writel_relaxed(l2x0_saved_regs.ctrl, base + L2X0_CTRL); 862 } 863 } 864 865 /* 866 * For Aurora cache in no outer mode, enable via the CP15 coprocessor 867 * broadcasting of cache commands to L2. 868 */ 869 static void __init aurora_enable_no_outer(void __iomem *base, u32 aux, 870 unsigned num_lock) 871 { 872 u32 u; 873 874 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); 875 u |= AURORA_CTRL_FW; /* Set the FW bit */ 876 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); 877 878 isb(); 879 880 l2c_enable(base, aux, num_lock); 881 } 882 883 static void __init aurora_fixup(void __iomem *base, u32 cache_id, 884 struct outer_cache_fns *fns) 885 { 886 sync_reg_offset = AURORA_SYNC_REG; 887 } 888 889 static void __init aurora_of_parse(const struct device_node *np, 890 u32 *aux_val, u32 *aux_mask) 891 { 892 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; 893 u32 mask = AURORA_ACR_REPLACEMENT_MASK; 894 895 of_property_read_u32(np, "cache-id-part", 896 &cache_id_part_number_from_dt); 897 898 /* Determine and save the write policy */ 899 l2_wt_override = of_property_read_bool(np, "wt-override"); 900 901 if (l2_wt_override) { 902 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; 903 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; 904 } 905 906 *aux_val &= ~mask; 907 *aux_val |= val; 908 *aux_mask &= ~mask; 909 } 910 911 static const struct l2c_init_data of_aurora_with_outer_data __initconst = { 912 .num_lock = 4, 913 .of_parse = aurora_of_parse, 914 .enable = l2c_enable, 915 .fixup = aurora_fixup, 916 .save = aurora_save, 917 .outer_cache = { 918 .inv_range = aurora_inv_range, 919 .clean_range = aurora_clean_range, 920 .flush_range = aurora_flush_range, 921 .flush_all = l2x0_flush_all, 922 .disable = l2x0_disable, 923 .sync = l2x0_cache_sync, 924 .resume = aurora_resume, 925 }, 926 }; 927 928 static const struct l2c_init_data of_aurora_no_outer_data __initconst = { 929 .num_lock = 4, 930 .of_parse = aurora_of_parse, 931 .enable = aurora_enable_no_outer, 932 .fixup = aurora_fixup, 933 .save = aurora_save, 934 .outer_cache = { 935 .resume = aurora_resume, 936 }, 937 }; 938 939 /* 940 * For certain Broadcom SoCs, depending on the address range, different offsets 941 * need to be added to the address before passing it to L2 for 942 * invalidation/clean/flush 943 * 944 * Section Address Range Offset EMI 945 * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC 946 * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS 947 * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC 948 * 949 * When the start and end addresses have crossed two different sections, we 950 * need to break the L2 operation into two, each within its own section. 951 * For example, if we need to invalidate addresses starts at 0xBFFF0000 and 952 * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) 953 * 0xC0000000 - 0xC0001000 954 * 955 * Note 1: 956 * By breaking a single L2 operation into two, we may potentially suffer some 957 * performance hit, but keep in mind the cross section case is very rare 958 * 959 * Note 2: 960 * We do not need to handle the case when the start address is in 961 * Section 1 and the end address is in Section 3, since it is not a valid use 962 * case 963 * 964 * Note 3: 965 * Section 1 in practical terms can no longer be used on rev A2. Because of 966 * that the code does not need to handle section 1 at all. 967 * 968 */ 969 #define BCM_SYS_EMI_START_ADDR 0x40000000UL 970 #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL 971 972 #define BCM_SYS_EMI_OFFSET 0x40000000UL 973 #define BCM_VC_EMI_OFFSET 0x80000000UL 974 975 static inline int bcm_addr_is_sys_emi(unsigned long addr) 976 { 977 return (addr >= BCM_SYS_EMI_START_ADDR) && 978 (addr < BCM_VC_EMI_SEC3_START_ADDR); 979 } 980 981 static inline unsigned long bcm_l2_phys_addr(unsigned long addr) 982 { 983 if (bcm_addr_is_sys_emi(addr)) 984 return addr + BCM_SYS_EMI_OFFSET; 985 else 986 return addr + BCM_VC_EMI_OFFSET; 987 } 988 989 static void bcm_inv_range(unsigned long start, unsigned long end) 990 { 991 unsigned long new_start, new_end; 992 993 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 994 995 if (unlikely(end <= start)) 996 return; 997 998 new_start = bcm_l2_phys_addr(start); 999 new_end = bcm_l2_phys_addr(end); 1000 1001 /* normal case, no cross section between start and end */ 1002 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1003 l2x0_inv_range(new_start, new_end); 1004 return; 1005 } 1006 1007 /* They cross sections, so it can only be a cross from section 1008 * 2 to section 3 1009 */ 1010 l2x0_inv_range(new_start, 1011 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1012 l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1013 new_end); 1014 } 1015 1016 static void bcm_clean_range(unsigned long start, unsigned long end) 1017 { 1018 unsigned long new_start, new_end; 1019 1020 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1021 1022 if (unlikely(end <= start)) 1023 return; 1024 1025 if ((end - start) >= l2x0_size) { 1026 l2x0_clean_all(); 1027 return; 1028 } 1029 1030 new_start = bcm_l2_phys_addr(start); 1031 new_end = bcm_l2_phys_addr(end); 1032 1033 /* normal case, no cross section between start and end */ 1034 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1035 l2x0_clean_range(new_start, new_end); 1036 return; 1037 } 1038 1039 /* They cross sections, so it can only be a cross from section 1040 * 2 to section 3 1041 */ 1042 l2x0_clean_range(new_start, 1043 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1044 l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1045 new_end); 1046 } 1047 1048 static void bcm_flush_range(unsigned long start, unsigned long end) 1049 { 1050 unsigned long new_start, new_end; 1051 1052 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1053 1054 if (unlikely(end <= start)) 1055 return; 1056 1057 if ((end - start) >= l2x0_size) { 1058 l2x0_flush_all(); 1059 return; 1060 } 1061 1062 new_start = bcm_l2_phys_addr(start); 1063 new_end = bcm_l2_phys_addr(end); 1064 1065 /* normal case, no cross section between start and end */ 1066 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1067 l2x0_flush_range(new_start, new_end); 1068 return; 1069 } 1070 1071 /* They cross sections, so it can only be a cross from section 1072 * 2 to section 3 1073 */ 1074 l2x0_flush_range(new_start, 1075 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1076 l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1077 new_end); 1078 } 1079 1080 static const struct l2c_init_data of_bcm_l2x0_data __initconst = { 1081 .num_lock = 8, 1082 .of_parse = pl310_of_parse, 1083 .enable = l2c_enable, 1084 .fixup = l2c310_fixup, 1085 .save = l2c310_save, 1086 .outer_cache = { 1087 .inv_range = bcm_inv_range, 1088 .clean_range = bcm_clean_range, 1089 .flush_range = bcm_flush_range, 1090 .flush_all = l2x0_flush_all, 1091 .disable = l2x0_disable, 1092 .sync = l2x0_cache_sync, 1093 .resume = l2c310_resume, 1094 }, 1095 }; 1096 1097 static void __init tauros3_save(void __iomem *base) 1098 { 1099 l2x0_saved_regs.aux2_ctrl = 1100 readl_relaxed(base + TAUROS3_AUX2_CTRL); 1101 l2x0_saved_regs.prefetch_ctrl = 1102 readl_relaxed(base + L2X0_PREFETCH_CTRL); 1103 } 1104 1105 static void tauros3_resume(void) 1106 { 1107 void __iomem *base = l2x0_base; 1108 1109 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 1110 writel_relaxed(l2x0_saved_regs.aux2_ctrl, 1111 base + TAUROS3_AUX2_CTRL); 1112 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 1113 base + L2X0_PREFETCH_CTRL); 1114 1115 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8); 1116 } 1117 } 1118 1119 static const struct l2c_init_data of_tauros3_data __initconst = { 1120 .num_lock = 8, 1121 .enable = l2c_enable, 1122 .save = tauros3_save, 1123 /* Tauros3 broadcasts L1 cache operations to L2 */ 1124 .outer_cache = { 1125 .resume = tauros3_resume, 1126 }, 1127 }; 1128 1129 #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } 1130 static const struct of_device_id l2x0_ids[] __initconst = { 1131 L2C_ID("arm,l210-cache", of_l2x0_data), 1132 L2C_ID("arm,l220-cache", of_l2x0_data), 1133 L2C_ID("arm,pl310-cache", of_pl310_data), 1134 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1135 L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data), 1136 L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data), 1137 L2C_ID("marvell,tauros3-cache", of_tauros3_data), 1138 /* Deprecated IDs */ 1139 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1140 {} 1141 }; 1142 1143 int __init l2x0_of_init(u32 aux_val, u32 aux_mask) 1144 { 1145 const struct l2c_init_data *data; 1146 struct device_node *np; 1147 struct resource res; 1148 u32 cache_id; 1149 1150 np = of_find_matching_node(NULL, l2x0_ids); 1151 if (!np) 1152 return -ENODEV; 1153 1154 if (of_address_to_resource(np, 0, &res)) 1155 return -ENODEV; 1156 1157 l2x0_base = ioremap(res.start, resource_size(&res)); 1158 if (!l2x0_base) 1159 return -ENOMEM; 1160 1161 l2x0_saved_regs.phy_base = res.start; 1162 1163 data = of_match_node(l2x0_ids, np)->data; 1164 1165 /* L2 configuration can only be changed if the cache is disabled */ 1166 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 1167 if (data->of_parse) 1168 data->of_parse(np, &aux_val, &aux_mask); 1169 1170 if (cache_id_part_number_from_dt) 1171 cache_id = cache_id_part_number_from_dt; 1172 else 1173 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 1174 1175 __l2c_init(data, aux_val, aux_mask, cache_id); 1176 1177 return 0; 1178 } 1179 #endif 1180