1 /* 2 * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support 3 * 4 * Copyright (C) 2007 ARM Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #include <linux/err.h> 20 #include <linux/init.h> 21 #include <linux/spinlock.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_address.h> 25 26 #include <asm/cacheflush.h> 27 #include <asm/hardware/cache-l2x0.h> 28 #include "cache-tauros3.h" 29 #include "cache-aurora-l2.h" 30 31 struct l2c_init_data { 32 unsigned num_lock; 33 void (*of_parse)(const struct device_node *, u32 *, u32 *); 34 void (*enable)(void __iomem *, u32, unsigned); 35 void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); 36 void (*save)(void __iomem *); 37 struct outer_cache_fns outer_cache; 38 }; 39 40 #define CACHE_LINE_SIZE 32 41 42 static void __iomem *l2x0_base; 43 static DEFINE_RAW_SPINLOCK(l2x0_lock); 44 static u32 l2x0_way_mask; /* Bitmask of active ways */ 45 static u32 l2x0_size; 46 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; 47 48 struct l2x0_regs l2x0_saved_regs; 49 50 /* 51 * Common code for all cache controllers. 52 */ 53 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) 54 { 55 /* wait for cache operation by line or way to complete */ 56 while (readl_relaxed(reg) & mask) 57 cpu_relax(); 58 } 59 60 /* 61 * This should only be called when we have a requirement that the 62 * register be written due to a work-around, as platforms running 63 * in non-secure mode may not be able to access this register. 64 */ 65 static inline void l2c_set_debug(void __iomem *base, unsigned long val) 66 { 67 outer_cache.set_debug(val); 68 } 69 70 static void __l2c_op_way(void __iomem *reg) 71 { 72 writel_relaxed(l2x0_way_mask, reg); 73 l2c_wait_mask(reg, l2x0_way_mask); 74 } 75 76 static inline void l2c_unlock(void __iomem *base, unsigned num) 77 { 78 unsigned i; 79 80 for (i = 0; i < num; i++) { 81 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + 82 i * L2X0_LOCKDOWN_STRIDE); 83 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + 84 i * L2X0_LOCKDOWN_STRIDE); 85 } 86 } 87 88 /* 89 * Enable the L2 cache controller. This function must only be 90 * called when the cache controller is known to be disabled. 91 */ 92 static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) 93 { 94 unsigned long flags; 95 96 /* Only write the aux register if it needs changing */ 97 if (readl_relaxed(base + L2X0_AUX_CTRL) != aux) 98 writel_relaxed(aux, base + L2X0_AUX_CTRL); 99 100 l2c_unlock(base, num_lock); 101 102 local_irq_save(flags); 103 __l2c_op_way(base + L2X0_INV_WAY); 104 writel_relaxed(0, base + sync_reg_offset); 105 l2c_wait_mask(base + sync_reg_offset, 1); 106 local_irq_restore(flags); 107 108 writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL); 109 } 110 111 static void l2c_disable(void) 112 { 113 void __iomem *base = l2x0_base; 114 115 outer_cache.flush_all(); 116 writel_relaxed(0, base + L2X0_CTRL); 117 dsb(st); 118 } 119 120 #ifdef CONFIG_CACHE_PL310 121 static inline void cache_wait(void __iomem *reg, unsigned long mask) 122 { 123 /* cache operations by line are atomic on PL310 */ 124 } 125 #else 126 #define cache_wait l2c_wait_mask 127 #endif 128 129 static inline void cache_sync(void) 130 { 131 void __iomem *base = l2x0_base; 132 133 writel_relaxed(0, base + sync_reg_offset); 134 cache_wait(base + L2X0_CACHE_SYNC, 1); 135 } 136 137 static inline void l2x0_clean_line(unsigned long addr) 138 { 139 void __iomem *base = l2x0_base; 140 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 141 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 142 } 143 144 static inline void l2x0_inv_line(unsigned long addr) 145 { 146 void __iomem *base = l2x0_base; 147 cache_wait(base + L2X0_INV_LINE_PA, 1); 148 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 149 } 150 151 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) 152 static inline void debug_writel(unsigned long val) 153 { 154 if (outer_cache.set_debug) 155 l2c_set_debug(l2x0_base, val); 156 } 157 #else 158 /* Optimised out for non-errata case */ 159 static inline void debug_writel(unsigned long val) 160 { 161 } 162 #endif 163 164 #ifdef CONFIG_PL310_ERRATA_588369 165 static inline void l2x0_flush_line(unsigned long addr) 166 { 167 void __iomem *base = l2x0_base; 168 169 /* Clean by PA followed by Invalidate by PA */ 170 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 171 writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA); 172 cache_wait(base + L2X0_INV_LINE_PA, 1); 173 writel_relaxed(addr, base + L2X0_INV_LINE_PA); 174 } 175 #else 176 177 static inline void l2x0_flush_line(unsigned long addr) 178 { 179 void __iomem *base = l2x0_base; 180 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 181 writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA); 182 } 183 #endif 184 185 static void l2x0_cache_sync(void) 186 { 187 unsigned long flags; 188 189 raw_spin_lock_irqsave(&l2x0_lock, flags); 190 cache_sync(); 191 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 192 } 193 194 static void __l2x0_flush_all(void) 195 { 196 debug_writel(0x03); 197 __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY); 198 cache_sync(); 199 debug_writel(0x00); 200 } 201 202 static void l2x0_flush_all(void) 203 { 204 unsigned long flags; 205 206 /* clean all ways */ 207 raw_spin_lock_irqsave(&l2x0_lock, flags); 208 __l2x0_flush_all(); 209 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 210 } 211 212 static void l2x0_clean_all(void) 213 { 214 unsigned long flags; 215 216 /* clean all ways */ 217 raw_spin_lock_irqsave(&l2x0_lock, flags); 218 __l2c_op_way(l2x0_base + L2X0_CLEAN_WAY); 219 cache_sync(); 220 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 221 } 222 223 static void l2x0_inv_all(void) 224 { 225 unsigned long flags; 226 227 /* invalidate all ways */ 228 raw_spin_lock_irqsave(&l2x0_lock, flags); 229 /* Invalidating when L2 is enabled is a nono */ 230 BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN); 231 __l2c_op_way(l2x0_base + L2X0_INV_WAY); 232 cache_sync(); 233 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 234 } 235 236 static void l2x0_inv_range(unsigned long start, unsigned long end) 237 { 238 void __iomem *base = l2x0_base; 239 unsigned long flags; 240 241 raw_spin_lock_irqsave(&l2x0_lock, flags); 242 if (start & (CACHE_LINE_SIZE - 1)) { 243 start &= ~(CACHE_LINE_SIZE - 1); 244 debug_writel(0x03); 245 l2x0_flush_line(start); 246 debug_writel(0x00); 247 start += CACHE_LINE_SIZE; 248 } 249 250 if (end & (CACHE_LINE_SIZE - 1)) { 251 end &= ~(CACHE_LINE_SIZE - 1); 252 debug_writel(0x03); 253 l2x0_flush_line(end); 254 debug_writel(0x00); 255 } 256 257 while (start < end) { 258 unsigned long blk_end = start + min(end - start, 4096UL); 259 260 while (start < blk_end) { 261 l2x0_inv_line(start); 262 start += CACHE_LINE_SIZE; 263 } 264 265 if (blk_end < end) { 266 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 267 raw_spin_lock_irqsave(&l2x0_lock, flags); 268 } 269 } 270 cache_wait(base + L2X0_INV_LINE_PA, 1); 271 cache_sync(); 272 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 273 } 274 275 static void l2x0_clean_range(unsigned long start, unsigned long end) 276 { 277 void __iomem *base = l2x0_base; 278 unsigned long flags; 279 280 if ((end - start) >= l2x0_size) { 281 l2x0_clean_all(); 282 return; 283 } 284 285 raw_spin_lock_irqsave(&l2x0_lock, flags); 286 start &= ~(CACHE_LINE_SIZE - 1); 287 while (start < end) { 288 unsigned long blk_end = start + min(end - start, 4096UL); 289 290 while (start < blk_end) { 291 l2x0_clean_line(start); 292 start += CACHE_LINE_SIZE; 293 } 294 295 if (blk_end < end) { 296 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 297 raw_spin_lock_irqsave(&l2x0_lock, flags); 298 } 299 } 300 cache_wait(base + L2X0_CLEAN_LINE_PA, 1); 301 cache_sync(); 302 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 303 } 304 305 static void l2x0_flush_range(unsigned long start, unsigned long end) 306 { 307 void __iomem *base = l2x0_base; 308 unsigned long flags; 309 310 if ((end - start) >= l2x0_size) { 311 l2x0_flush_all(); 312 return; 313 } 314 315 raw_spin_lock_irqsave(&l2x0_lock, flags); 316 start &= ~(CACHE_LINE_SIZE - 1); 317 while (start < end) { 318 unsigned long blk_end = start + min(end - start, 4096UL); 319 320 debug_writel(0x03); 321 while (start < blk_end) { 322 l2x0_flush_line(start); 323 start += CACHE_LINE_SIZE; 324 } 325 debug_writel(0x00); 326 327 if (blk_end < end) { 328 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 329 raw_spin_lock_irqsave(&l2x0_lock, flags); 330 } 331 } 332 cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); 333 cache_sync(); 334 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 335 } 336 337 static void l2x0_disable(void) 338 { 339 unsigned long flags; 340 341 raw_spin_lock_irqsave(&l2x0_lock, flags); 342 __l2x0_flush_all(); 343 writel_relaxed(0, l2x0_base + L2X0_CTRL); 344 dsb(st); 345 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 346 } 347 348 static void l2x0_enable(void __iomem *base, u32 aux, unsigned num_lock) 349 { 350 unsigned id; 351 352 id = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_PART_MASK; 353 if (id == L2X0_CACHE_ID_PART_L310) 354 num_lock = 8; 355 else 356 num_lock = 1; 357 358 /* l2x0 controller is disabled */ 359 writel_relaxed(aux, base + L2X0_AUX_CTRL); 360 361 /* Make sure that I&D is not locked down when starting */ 362 l2c_unlock(base, num_lock); 363 364 l2x0_inv_all(); 365 366 /* enable L2X0 */ 367 writel_relaxed(L2X0_CTRL_EN, base + L2X0_CTRL); 368 } 369 370 static void l2x0_resume(void) 371 { 372 void __iomem *base = l2x0_base; 373 374 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) 375 l2x0_enable(base, l2x0_saved_regs.aux_ctrl, 0); 376 } 377 378 static const struct l2c_init_data l2x0_init_fns __initconst = { 379 .enable = l2x0_enable, 380 .outer_cache = { 381 .inv_range = l2x0_inv_range, 382 .clean_range = l2x0_clean_range, 383 .flush_range = l2x0_flush_range, 384 .flush_all = l2x0_flush_all, 385 .disable = l2x0_disable, 386 .sync = l2x0_cache_sync, 387 .resume = l2x0_resume, 388 }, 389 }; 390 391 /* 392 * L2C-210 specific code. 393 * 394 * The L2C-2x0 PA, set/way and sync operations are atomic, but we must 395 * ensure that no background operation is running. The way operations 396 * are all background tasks. 397 * 398 * While a background operation is in progress, any new operation is 399 * ignored (unspecified whether this causes an error.) Thankfully, not 400 * used on SMP. 401 * 402 * Never has a different sync register other than L2X0_CACHE_SYNC, but 403 * we use sync_reg_offset here so we can share some of this with L2C-310. 404 */ 405 static void __l2c210_cache_sync(void __iomem *base) 406 { 407 writel_relaxed(0, base + sync_reg_offset); 408 } 409 410 static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, 411 unsigned long end) 412 { 413 while (start < end) { 414 writel_relaxed(start, reg); 415 start += CACHE_LINE_SIZE; 416 } 417 } 418 419 static void l2c210_inv_range(unsigned long start, unsigned long end) 420 { 421 void __iomem *base = l2x0_base; 422 423 if (start & (CACHE_LINE_SIZE - 1)) { 424 start &= ~(CACHE_LINE_SIZE - 1); 425 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); 426 start += CACHE_LINE_SIZE; 427 } 428 429 if (end & (CACHE_LINE_SIZE - 1)) { 430 end &= ~(CACHE_LINE_SIZE - 1); 431 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); 432 } 433 434 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); 435 __l2c210_cache_sync(base); 436 } 437 438 static void l2c210_clean_range(unsigned long start, unsigned long end) 439 { 440 void __iomem *base = l2x0_base; 441 442 start &= ~(CACHE_LINE_SIZE - 1); 443 __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end); 444 __l2c210_cache_sync(base); 445 } 446 447 static void l2c210_flush_range(unsigned long start, unsigned long end) 448 { 449 void __iomem *base = l2x0_base; 450 451 start &= ~(CACHE_LINE_SIZE - 1); 452 __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end); 453 __l2c210_cache_sync(base); 454 } 455 456 static void l2c210_flush_all(void) 457 { 458 void __iomem *base = l2x0_base; 459 460 BUG_ON(!irqs_disabled()); 461 462 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 463 __l2c210_cache_sync(base); 464 } 465 466 static void l2c210_sync(void) 467 { 468 __l2c210_cache_sync(l2x0_base); 469 } 470 471 static void l2c210_resume(void) 472 { 473 void __iomem *base = l2x0_base; 474 475 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) 476 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1); 477 } 478 479 static const struct l2c_init_data l2c210_data __initconst = { 480 .num_lock = 1, 481 .enable = l2c_enable, 482 .outer_cache = { 483 .inv_range = l2c210_inv_range, 484 .clean_range = l2c210_clean_range, 485 .flush_range = l2c210_flush_range, 486 .flush_all = l2c210_flush_all, 487 .disable = l2c_disable, 488 .sync = l2c210_sync, 489 .resume = l2c210_resume, 490 }, 491 }; 492 493 /* 494 * L2C-310 specific code. 495 * 496 * Errata: 497 * 588369: PL310 R0P0->R1P0, fixed R2P0. 498 * Affects: all clean+invalidate operations 499 * clean and invalidate skips the invalidate step, so we need to issue 500 * separate operations. We also require the above debug workaround 501 * enclosing this code fragment on affected parts. On unaffected parts, 502 * we must not use this workaround without the debug register writes 503 * to avoid exposing a problem similar to 727915. 504 * 505 * 727915: PL310 R2P0->R3P0, fixed R3P1. 506 * Affects: clean+invalidate by way 507 * clean and invalidate by way runs in the background, and a store can 508 * hit the line between the clean operation and invalidate operation, 509 * resulting in the store being lost. 510 * 511 * 753970: PL310 R3P0, fixed R3P1. 512 * Affects: sync 513 * prevents merging writes after the sync operation, until another L2C 514 * operation is performed (or a number of other conditions.) 515 * 516 * 769419: PL310 R0P0->R3P1, fixed R3P2. 517 * Affects: store buffer 518 * store buffer is not automatically drained. 519 */ 520 static void l2c310_set_debug(unsigned long val) 521 { 522 writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); 523 } 524 525 static void l2c310_inv_range_erratum(unsigned long start, unsigned long end) 526 { 527 void __iomem *base = l2x0_base; 528 529 if ((start | end) & (CACHE_LINE_SIZE - 1)) { 530 unsigned long flags; 531 532 /* Erratum 588369 for both clean+invalidate operations */ 533 raw_spin_lock_irqsave(&l2x0_lock, flags); 534 l2c_set_debug(base, 0x03); 535 536 if (start & (CACHE_LINE_SIZE - 1)) { 537 start &= ~(CACHE_LINE_SIZE - 1); 538 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); 539 writel_relaxed(start, base + L2X0_INV_LINE_PA); 540 start += CACHE_LINE_SIZE; 541 } 542 543 if (end & (CACHE_LINE_SIZE - 1)) { 544 end &= ~(CACHE_LINE_SIZE - 1); 545 writel_relaxed(end, base + L2X0_CLEAN_LINE_PA); 546 writel_relaxed(end, base + L2X0_INV_LINE_PA); 547 } 548 549 l2c_set_debug(base, 0x00); 550 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 551 } 552 553 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); 554 __l2c210_cache_sync(base); 555 } 556 557 static void l2c310_flush_range_erratum(unsigned long start, unsigned long end) 558 { 559 raw_spinlock_t *lock = &l2x0_lock; 560 unsigned long flags; 561 void __iomem *base = l2x0_base; 562 563 raw_spin_lock_irqsave(lock, flags); 564 while (start < end) { 565 unsigned long blk_end = start + min(end - start, 4096UL); 566 567 l2c_set_debug(base, 0x03); 568 while (start < blk_end) { 569 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); 570 writel_relaxed(start, base + L2X0_INV_LINE_PA); 571 start += CACHE_LINE_SIZE; 572 } 573 l2c_set_debug(base, 0x00); 574 575 if (blk_end < end) { 576 raw_spin_unlock_irqrestore(lock, flags); 577 raw_spin_lock_irqsave(lock, flags); 578 } 579 } 580 raw_spin_unlock_irqrestore(lock, flags); 581 __l2c210_cache_sync(base); 582 } 583 584 static void l2c310_flush_all_erratum(void) 585 { 586 void __iomem *base = l2x0_base; 587 unsigned long flags; 588 589 raw_spin_lock_irqsave(&l2x0_lock, flags); 590 l2c_set_debug(base, 0x03); 591 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); 592 l2c_set_debug(base, 0x00); 593 __l2c210_cache_sync(base); 594 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 595 } 596 597 static void __init l2c310_save(void __iomem *base) 598 { 599 unsigned revision; 600 601 l2x0_saved_regs.tag_latency = readl_relaxed(base + 602 L2X0_TAG_LATENCY_CTRL); 603 l2x0_saved_regs.data_latency = readl_relaxed(base + 604 L2X0_DATA_LATENCY_CTRL); 605 l2x0_saved_regs.filter_end = readl_relaxed(base + 606 L2X0_ADDR_FILTER_END); 607 l2x0_saved_regs.filter_start = readl_relaxed(base + 608 L2X0_ADDR_FILTER_START); 609 610 revision = readl_relaxed(base + L2X0_CACHE_ID) & 611 L2X0_CACHE_ID_RTL_MASK; 612 613 /* From r2p0, there is Prefetch offset/control register */ 614 if (revision >= L310_CACHE_ID_RTL_R2P0) 615 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + 616 L2X0_PREFETCH_CTRL); 617 618 /* From r3p0, there is Power control register */ 619 if (revision >= L310_CACHE_ID_RTL_R3P0) 620 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + 621 L2X0_POWER_CTRL); 622 } 623 624 static void l2c310_resume(void) 625 { 626 void __iomem *base = l2x0_base; 627 628 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 629 unsigned revision; 630 631 /* restore pl310 setup */ 632 writel_relaxed(l2x0_saved_regs.tag_latency, 633 base + L2X0_TAG_LATENCY_CTRL); 634 writel_relaxed(l2x0_saved_regs.data_latency, 635 base + L2X0_DATA_LATENCY_CTRL); 636 writel_relaxed(l2x0_saved_regs.filter_end, 637 base + L2X0_ADDR_FILTER_END); 638 writel_relaxed(l2x0_saved_regs.filter_start, 639 base + L2X0_ADDR_FILTER_START); 640 641 revision = readl_relaxed(base + L2X0_CACHE_ID) & 642 L2X0_CACHE_ID_RTL_MASK; 643 644 if (revision >= L310_CACHE_ID_RTL_R2P0) 645 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 646 base + L2X0_PREFETCH_CTRL); 647 if (revision >= L310_CACHE_ID_RTL_R3P0) 648 writel_relaxed(l2x0_saved_regs.pwr_ctrl, 649 base + L2X0_POWER_CTRL); 650 651 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8); 652 } 653 } 654 655 static void __init l2c310_fixup(void __iomem *base, u32 cache_id, 656 struct outer_cache_fns *fns) 657 { 658 unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK; 659 const char *errata[4]; 660 unsigned n = 0; 661 662 /* For compatibility */ 663 if (revision <= L310_CACHE_ID_RTL_R3P0) 664 fns->set_debug = l2c310_set_debug; 665 666 if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) && 667 revision < L310_CACHE_ID_RTL_R2P0 && 668 /* For bcm compatibility */ 669 fns->inv_range == l2x0_inv_range) { 670 fns->inv_range = l2c310_inv_range_erratum; 671 fns->flush_range = l2c310_flush_range_erratum; 672 errata[n++] = "588369"; 673 } 674 675 if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) && 676 revision >= L310_CACHE_ID_RTL_R2P0 && 677 revision < L310_CACHE_ID_RTL_R3P1) { 678 fns->flush_all = l2c310_flush_all_erratum; 679 errata[n++] = "727915"; 680 } 681 682 if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) && 683 revision == L310_CACHE_ID_RTL_R3P0) { 684 sync_reg_offset = L2X0_DUMMY_REG; 685 errata[n++] = "753970"; 686 } 687 688 if (IS_ENABLED(CONFIG_PL310_ERRATA_769419)) 689 errata[n++] = "769419"; 690 691 if (n) { 692 unsigned i; 693 694 pr_info("L2C-310 errat%s", n > 1 ? "a" : "um"); 695 for (i = 0; i < n; i++) 696 pr_cont(" %s", errata[i]); 697 pr_cont(" enabled\n"); 698 } 699 } 700 701 static const struct l2c_init_data l2c310_init_fns __initconst = { 702 .num_lock = 8, 703 .enable = l2c_enable, 704 .fixup = l2c310_fixup, 705 .save = l2c310_save, 706 .outer_cache = { 707 .inv_range = l2x0_inv_range, 708 .clean_range = l2x0_clean_range, 709 .flush_range = l2x0_flush_range, 710 .flush_all = l2x0_flush_all, 711 .disable = l2x0_disable, 712 .sync = l2x0_cache_sync, 713 .resume = l2c310_resume, 714 }, 715 }; 716 717 static void __init __l2c_init(const struct l2c_init_data *data, 718 u32 aux_val, u32 aux_mask, u32 cache_id) 719 { 720 struct outer_cache_fns fns; 721 u32 aux; 722 u32 way_size = 0; 723 int ways; 724 int way_size_shift = L2X0_WAY_SIZE_SHIFT; 725 const char *type; 726 727 /* 728 * It is strange to save the register state before initialisation, 729 * but hey, this is what the DT implementations decided to do. 730 */ 731 if (data->save) 732 data->save(l2x0_base); 733 734 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 735 736 aux &= aux_mask; 737 aux |= aux_val; 738 739 /* Determine the number of ways */ 740 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 741 case L2X0_CACHE_ID_PART_L310: 742 if (aux & (1 << 16)) 743 ways = 16; 744 else 745 ways = 8; 746 type = "L310"; 747 break; 748 749 case L2X0_CACHE_ID_PART_L210: 750 ways = (aux >> 13) & 0xf; 751 type = "L210"; 752 break; 753 754 case AURORA_CACHE_ID: 755 ways = (aux >> 13) & 0xf; 756 ways = 2 << ((ways + 1) >> 2); 757 way_size_shift = AURORA_WAY_SIZE_SHIFT; 758 type = "Aurora"; 759 break; 760 761 default: 762 /* Assume unknown chips have 8 ways */ 763 ways = 8; 764 type = "L2x0 series"; 765 break; 766 } 767 768 l2x0_way_mask = (1 << ways) - 1; 769 770 /* 771 * L2 cache Size = Way size * Number of ways 772 */ 773 way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17; 774 way_size = 1 << (way_size + way_size_shift); 775 776 l2x0_size = ways * way_size * SZ_1K; 777 778 fns = data->outer_cache; 779 if (data->fixup) 780 data->fixup(l2x0_base, cache_id, &fns); 781 782 /* 783 * Check if l2x0 controller is already enabled. If we are booting 784 * in non-secure mode accessing the below registers will fault. 785 */ 786 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 787 data->enable(l2x0_base, aux, data->num_lock); 788 789 /* Re-read it in case some bits are reserved. */ 790 aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); 791 792 /* Save the value for resuming. */ 793 l2x0_saved_regs.aux_ctrl = aux; 794 795 outer_cache = fns; 796 797 pr_info("%s cache controller enabled, %d ways, %d kB\n", 798 type, ways, l2x0_size >> 10); 799 pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n", 800 type, cache_id, aux); 801 } 802 803 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) 804 { 805 const struct l2c_init_data *data; 806 u32 cache_id; 807 808 l2x0_base = base; 809 810 cache_id = readl_relaxed(base + L2X0_CACHE_ID); 811 812 switch (cache_id & L2X0_CACHE_ID_PART_MASK) { 813 default: 814 data = &l2x0_init_fns; 815 break; 816 817 case L2X0_CACHE_ID_PART_L210: 818 data = &l2c210_data; 819 break; 820 821 case L2X0_CACHE_ID_PART_L310: 822 data = &l2c310_init_fns; 823 break; 824 } 825 826 __l2c_init(data, aux_val, aux_mask, cache_id); 827 } 828 829 #ifdef CONFIG_OF 830 static int l2_wt_override; 831 832 /* Aurora don't have the cache ID register available, so we have to 833 * pass it though the device tree */ 834 static u32 cache_id_part_number_from_dt; 835 836 static void __init l2x0_of_parse(const struct device_node *np, 837 u32 *aux_val, u32 *aux_mask) 838 { 839 u32 data[2] = { 0, 0 }; 840 u32 tag = 0; 841 u32 dirty = 0; 842 u32 val = 0, mask = 0; 843 844 of_property_read_u32(np, "arm,tag-latency", &tag); 845 if (tag) { 846 mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; 847 val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; 848 } 849 850 of_property_read_u32_array(np, "arm,data-latency", 851 data, ARRAY_SIZE(data)); 852 if (data[0] && data[1]) { 853 mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | 854 L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; 855 val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | 856 ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); 857 } 858 859 of_property_read_u32(np, "arm,dirty-latency", &dirty); 860 if (dirty) { 861 mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; 862 val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; 863 } 864 865 *aux_val &= ~mask; 866 *aux_val |= val; 867 *aux_mask &= ~mask; 868 } 869 870 static const struct l2c_init_data of_l2c210_data __initconst = { 871 .num_lock = 1, 872 .of_parse = l2x0_of_parse, 873 .enable = l2c_enable, 874 .outer_cache = { 875 .inv_range = l2c210_inv_range, 876 .clean_range = l2c210_clean_range, 877 .flush_range = l2c210_flush_range, 878 .flush_all = l2c210_flush_all, 879 .disable = l2c_disable, 880 .sync = l2c210_sync, 881 .resume = l2c210_resume, 882 }, 883 }; 884 885 static const struct l2c_init_data of_l2x0_data __initconst = { 886 .of_parse = l2x0_of_parse, 887 .enable = l2x0_enable, 888 .outer_cache = { 889 .inv_range = l2x0_inv_range, 890 .clean_range = l2x0_clean_range, 891 .flush_range = l2x0_flush_range, 892 .flush_all = l2x0_flush_all, 893 .disable = l2x0_disable, 894 .sync = l2x0_cache_sync, 895 .resume = l2x0_resume, 896 }, 897 }; 898 899 static void __init pl310_of_parse(const struct device_node *np, 900 u32 *aux_val, u32 *aux_mask) 901 { 902 u32 data[3] = { 0, 0, 0 }; 903 u32 tag[3] = { 0, 0, 0 }; 904 u32 filter[2] = { 0, 0 }; 905 906 of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); 907 if (tag[0] && tag[1] && tag[2]) 908 writel_relaxed( 909 ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | 910 ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | 911 ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), 912 l2x0_base + L2X0_TAG_LATENCY_CTRL); 913 914 of_property_read_u32_array(np, "arm,data-latency", 915 data, ARRAY_SIZE(data)); 916 if (data[0] && data[1] && data[2]) 917 writel_relaxed( 918 ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | 919 ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | 920 ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), 921 l2x0_base + L2X0_DATA_LATENCY_CTRL); 922 923 of_property_read_u32_array(np, "arm,filter-ranges", 924 filter, ARRAY_SIZE(filter)); 925 if (filter[1]) { 926 writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), 927 l2x0_base + L2X0_ADDR_FILTER_END); 928 writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, 929 l2x0_base + L2X0_ADDR_FILTER_START); 930 } 931 } 932 933 static const struct l2c_init_data of_pl310_data __initconst = { 934 .num_lock = 8, 935 .of_parse = pl310_of_parse, 936 .enable = l2c_enable, 937 .fixup = l2c310_fixup, 938 .save = l2c310_save, 939 .outer_cache = { 940 .inv_range = l2x0_inv_range, 941 .clean_range = l2x0_clean_range, 942 .flush_range = l2x0_flush_range, 943 .flush_all = l2x0_flush_all, 944 .disable = l2x0_disable, 945 .sync = l2x0_cache_sync, 946 .resume = l2c310_resume, 947 }, 948 }; 949 950 /* 951 * Note that the end addresses passed to Linux primitives are 952 * noninclusive, while the hardware cache range operations use 953 * inclusive start and end addresses. 954 */ 955 static unsigned long calc_range_end(unsigned long start, unsigned long end) 956 { 957 /* 958 * Limit the number of cache lines processed at once, 959 * since cache range operations stall the CPU pipeline 960 * until completion. 961 */ 962 if (end > start + MAX_RANGE_SIZE) 963 end = start + MAX_RANGE_SIZE; 964 965 /* 966 * Cache range operations can't straddle a page boundary. 967 */ 968 if (end > PAGE_ALIGN(start+1)) 969 end = PAGE_ALIGN(start+1); 970 971 return end; 972 } 973 974 /* 975 * Make sure 'start' and 'end' reference the same page, as L2 is PIPT 976 * and range operations only do a TLB lookup on the start address. 977 */ 978 static void aurora_pa_range(unsigned long start, unsigned long end, 979 unsigned long offset) 980 { 981 unsigned long flags; 982 983 raw_spin_lock_irqsave(&l2x0_lock, flags); 984 writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); 985 writel_relaxed(end, l2x0_base + offset); 986 raw_spin_unlock_irqrestore(&l2x0_lock, flags); 987 988 cache_sync(); 989 } 990 991 static void aurora_inv_range(unsigned long start, unsigned long end) 992 { 993 /* 994 * round start and end adresses up to cache line size 995 */ 996 start &= ~(CACHE_LINE_SIZE - 1); 997 end = ALIGN(end, CACHE_LINE_SIZE); 998 999 /* 1000 * Invalidate all full cache lines between 'start' and 'end'. 1001 */ 1002 while (start < end) { 1003 unsigned long range_end = calc_range_end(start, end); 1004 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 1005 AURORA_INVAL_RANGE_REG); 1006 start = range_end; 1007 } 1008 } 1009 1010 static void aurora_clean_range(unsigned long start, unsigned long end) 1011 { 1012 /* 1013 * If L2 is forced to WT, the L2 will always be clean and we 1014 * don't need to do anything here. 1015 */ 1016 if (!l2_wt_override) { 1017 start &= ~(CACHE_LINE_SIZE - 1); 1018 end = ALIGN(end, CACHE_LINE_SIZE); 1019 while (start != end) { 1020 unsigned long range_end = calc_range_end(start, end); 1021 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 1022 AURORA_CLEAN_RANGE_REG); 1023 start = range_end; 1024 } 1025 } 1026 } 1027 1028 static void aurora_flush_range(unsigned long start, unsigned long end) 1029 { 1030 start &= ~(CACHE_LINE_SIZE - 1); 1031 end = ALIGN(end, CACHE_LINE_SIZE); 1032 while (start != end) { 1033 unsigned long range_end = calc_range_end(start, end); 1034 /* 1035 * If L2 is forced to WT, the L2 will always be clean and we 1036 * just need to invalidate. 1037 */ 1038 if (l2_wt_override) 1039 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 1040 AURORA_INVAL_RANGE_REG); 1041 else 1042 aurora_pa_range(start, range_end - CACHE_LINE_SIZE, 1043 AURORA_FLUSH_RANGE_REG); 1044 start = range_end; 1045 } 1046 } 1047 1048 static void aurora_save(void __iomem *base) 1049 { 1050 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); 1051 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); 1052 } 1053 1054 static void aurora_resume(void) 1055 { 1056 void __iomem *base = l2x0_base; 1057 1058 if (!(readl(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 1059 writel_relaxed(l2x0_saved_regs.aux_ctrl, base + L2X0_AUX_CTRL); 1060 writel_relaxed(l2x0_saved_regs.ctrl, base + L2X0_CTRL); 1061 } 1062 } 1063 1064 /* 1065 * For Aurora cache in no outer mode, enable via the CP15 coprocessor 1066 * broadcasting of cache commands to L2. 1067 */ 1068 static void __init aurora_enable_no_outer(void __iomem *base, u32 aux, 1069 unsigned num_lock) 1070 { 1071 u32 u; 1072 1073 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); 1074 u |= AURORA_CTRL_FW; /* Set the FW bit */ 1075 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); 1076 1077 isb(); 1078 1079 l2c_enable(base, aux, num_lock); 1080 } 1081 1082 static void __init aurora_fixup(void __iomem *base, u32 cache_id, 1083 struct outer_cache_fns *fns) 1084 { 1085 sync_reg_offset = AURORA_SYNC_REG; 1086 } 1087 1088 static void __init aurora_of_parse(const struct device_node *np, 1089 u32 *aux_val, u32 *aux_mask) 1090 { 1091 u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU; 1092 u32 mask = AURORA_ACR_REPLACEMENT_MASK; 1093 1094 of_property_read_u32(np, "cache-id-part", 1095 &cache_id_part_number_from_dt); 1096 1097 /* Determine and save the write policy */ 1098 l2_wt_override = of_property_read_bool(np, "wt-override"); 1099 1100 if (l2_wt_override) { 1101 val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY; 1102 mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK; 1103 } 1104 1105 *aux_val &= ~mask; 1106 *aux_val |= val; 1107 *aux_mask &= ~mask; 1108 } 1109 1110 static const struct l2c_init_data of_aurora_with_outer_data __initconst = { 1111 .num_lock = 4, 1112 .of_parse = aurora_of_parse, 1113 .enable = l2c_enable, 1114 .fixup = aurora_fixup, 1115 .save = aurora_save, 1116 .outer_cache = { 1117 .inv_range = aurora_inv_range, 1118 .clean_range = aurora_clean_range, 1119 .flush_range = aurora_flush_range, 1120 .flush_all = l2x0_flush_all, 1121 .disable = l2x0_disable, 1122 .sync = l2x0_cache_sync, 1123 .resume = aurora_resume, 1124 }, 1125 }; 1126 1127 static const struct l2c_init_data of_aurora_no_outer_data __initconst = { 1128 .num_lock = 4, 1129 .of_parse = aurora_of_parse, 1130 .enable = aurora_enable_no_outer, 1131 .fixup = aurora_fixup, 1132 .save = aurora_save, 1133 .outer_cache = { 1134 .resume = aurora_resume, 1135 }, 1136 }; 1137 1138 /* 1139 * For certain Broadcom SoCs, depending on the address range, different offsets 1140 * need to be added to the address before passing it to L2 for 1141 * invalidation/clean/flush 1142 * 1143 * Section Address Range Offset EMI 1144 * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC 1145 * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS 1146 * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC 1147 * 1148 * When the start and end addresses have crossed two different sections, we 1149 * need to break the L2 operation into two, each within its own section. 1150 * For example, if we need to invalidate addresses starts at 0xBFFF0000 and 1151 * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2) 1152 * 0xC0000000 - 0xC0001000 1153 * 1154 * Note 1: 1155 * By breaking a single L2 operation into two, we may potentially suffer some 1156 * performance hit, but keep in mind the cross section case is very rare 1157 * 1158 * Note 2: 1159 * We do not need to handle the case when the start address is in 1160 * Section 1 and the end address is in Section 3, since it is not a valid use 1161 * case 1162 * 1163 * Note 3: 1164 * Section 1 in practical terms can no longer be used on rev A2. Because of 1165 * that the code does not need to handle section 1 at all. 1166 * 1167 */ 1168 #define BCM_SYS_EMI_START_ADDR 0x40000000UL 1169 #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL 1170 1171 #define BCM_SYS_EMI_OFFSET 0x40000000UL 1172 #define BCM_VC_EMI_OFFSET 0x80000000UL 1173 1174 static inline int bcm_addr_is_sys_emi(unsigned long addr) 1175 { 1176 return (addr >= BCM_SYS_EMI_START_ADDR) && 1177 (addr < BCM_VC_EMI_SEC3_START_ADDR); 1178 } 1179 1180 static inline unsigned long bcm_l2_phys_addr(unsigned long addr) 1181 { 1182 if (bcm_addr_is_sys_emi(addr)) 1183 return addr + BCM_SYS_EMI_OFFSET; 1184 else 1185 return addr + BCM_VC_EMI_OFFSET; 1186 } 1187 1188 static void bcm_inv_range(unsigned long start, unsigned long end) 1189 { 1190 unsigned long new_start, new_end; 1191 1192 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1193 1194 if (unlikely(end <= start)) 1195 return; 1196 1197 new_start = bcm_l2_phys_addr(start); 1198 new_end = bcm_l2_phys_addr(end); 1199 1200 /* normal case, no cross section between start and end */ 1201 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1202 l2x0_inv_range(new_start, new_end); 1203 return; 1204 } 1205 1206 /* They cross sections, so it can only be a cross from section 1207 * 2 to section 3 1208 */ 1209 l2x0_inv_range(new_start, 1210 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1211 l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1212 new_end); 1213 } 1214 1215 static void bcm_clean_range(unsigned long start, unsigned long end) 1216 { 1217 unsigned long new_start, new_end; 1218 1219 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1220 1221 if (unlikely(end <= start)) 1222 return; 1223 1224 if ((end - start) >= l2x0_size) { 1225 l2x0_clean_all(); 1226 return; 1227 } 1228 1229 new_start = bcm_l2_phys_addr(start); 1230 new_end = bcm_l2_phys_addr(end); 1231 1232 /* normal case, no cross section between start and end */ 1233 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1234 l2x0_clean_range(new_start, new_end); 1235 return; 1236 } 1237 1238 /* They cross sections, so it can only be a cross from section 1239 * 2 to section 3 1240 */ 1241 l2x0_clean_range(new_start, 1242 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1243 l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1244 new_end); 1245 } 1246 1247 static void bcm_flush_range(unsigned long start, unsigned long end) 1248 { 1249 unsigned long new_start, new_end; 1250 1251 BUG_ON(start < BCM_SYS_EMI_START_ADDR); 1252 1253 if (unlikely(end <= start)) 1254 return; 1255 1256 if ((end - start) >= l2x0_size) { 1257 l2x0_flush_all(); 1258 return; 1259 } 1260 1261 new_start = bcm_l2_phys_addr(start); 1262 new_end = bcm_l2_phys_addr(end); 1263 1264 /* normal case, no cross section between start and end */ 1265 if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) { 1266 l2x0_flush_range(new_start, new_end); 1267 return; 1268 } 1269 1270 /* They cross sections, so it can only be a cross from section 1271 * 2 to section 3 1272 */ 1273 l2x0_flush_range(new_start, 1274 bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1)); 1275 l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR), 1276 new_end); 1277 } 1278 1279 static const struct l2c_init_data of_bcm_l2x0_data __initconst = { 1280 .num_lock = 8, 1281 .of_parse = pl310_of_parse, 1282 .enable = l2c_enable, 1283 .fixup = l2c310_fixup, 1284 .save = l2c310_save, 1285 .outer_cache = { 1286 .inv_range = bcm_inv_range, 1287 .clean_range = bcm_clean_range, 1288 .flush_range = bcm_flush_range, 1289 .flush_all = l2x0_flush_all, 1290 .disable = l2x0_disable, 1291 .sync = l2x0_cache_sync, 1292 .resume = l2c310_resume, 1293 }, 1294 }; 1295 1296 static void __init tauros3_save(void __iomem *base) 1297 { 1298 l2x0_saved_regs.aux2_ctrl = 1299 readl_relaxed(base + TAUROS3_AUX2_CTRL); 1300 l2x0_saved_regs.prefetch_ctrl = 1301 readl_relaxed(base + L2X0_PREFETCH_CTRL); 1302 } 1303 1304 static void tauros3_resume(void) 1305 { 1306 void __iomem *base = l2x0_base; 1307 1308 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) { 1309 writel_relaxed(l2x0_saved_regs.aux2_ctrl, 1310 base + TAUROS3_AUX2_CTRL); 1311 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 1312 base + L2X0_PREFETCH_CTRL); 1313 1314 l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8); 1315 } 1316 } 1317 1318 static const struct l2c_init_data of_tauros3_data __initconst = { 1319 .num_lock = 8, 1320 .enable = l2c_enable, 1321 .save = tauros3_save, 1322 /* Tauros3 broadcasts L1 cache operations to L2 */ 1323 .outer_cache = { 1324 .resume = tauros3_resume, 1325 }, 1326 }; 1327 1328 #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns } 1329 static const struct of_device_id l2x0_ids[] __initconst = { 1330 L2C_ID("arm,l210-cache", of_l2c210_data), 1331 L2C_ID("arm,l220-cache", of_l2x0_data), 1332 L2C_ID("arm,pl310-cache", of_pl310_data), 1333 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1334 L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data), 1335 L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data), 1336 L2C_ID("marvell,tauros3-cache", of_tauros3_data), 1337 /* Deprecated IDs */ 1338 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data), 1339 {} 1340 }; 1341 1342 int __init l2x0_of_init(u32 aux_val, u32 aux_mask) 1343 { 1344 const struct l2c_init_data *data; 1345 struct device_node *np; 1346 struct resource res; 1347 u32 cache_id; 1348 1349 np = of_find_matching_node(NULL, l2x0_ids); 1350 if (!np) 1351 return -ENODEV; 1352 1353 if (of_address_to_resource(np, 0, &res)) 1354 return -ENODEV; 1355 1356 l2x0_base = ioremap(res.start, resource_size(&res)); 1357 if (!l2x0_base) 1358 return -ENOMEM; 1359 1360 l2x0_saved_regs.phy_base = res.start; 1361 1362 data = of_match_node(l2x0_ids, np)->data; 1363 1364 /* L2 configuration can only be changed if the cache is disabled */ 1365 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) 1366 if (data->of_parse) 1367 data->of_parse(np, &aux_val, &aux_mask); 1368 1369 if (cache_id_part_number_from_dt) 1370 cache_id = cache_id_part_number_from_dt; 1371 else 1372 cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); 1373 1374 __l2c_init(data, aux_val, aux_mask, cache_id); 1375 1376 return 0; 1377 } 1378 #endif 1379