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Kconfig | H A D | 12-Jun-2018 | 901 | 42 | 31 | |
MAINTAINERS | H A D | 10-Dec-2018 | 628 | 20 | 18 | |
Makefile | H A D | 06-May-2018 | 190 | 11 | 6 | |
README | H A D | 18-Jun-2016 | 1.9 KiB | 55 | 50 | |
cpld.c | H A D | 06-May-2018 | 3.6 KiB | 174 | 130 | |
cpld.h | H A D | 06-May-2018 | 1.3 KiB | 46 | 32 | |
ddr.c | H A D | 10-Dec-2018 | 5.8 KiB | 253 | 200 | |
ddr.h | H A D | 06-May-2018 | 2.7 KiB | 117 | 93 | |
eth.c | H A D | 06-May-2018 | 2 KiB | 77 | 52 | |
ls1043ardb.c | H A D | 10-Dec-2018 | 6.5 KiB | 332 | 267 | |
ls1043ardb_pbi.cfg | H A D | 12-Nov-2015 | 280 | 15 | 14 | |
ls1043ardb_rcw_nand.cfg | H A D | 17-Dec-2015 | 209 | 8 | 7 | |
ls1043ardb_rcw_sd.cfg | H A D | 17-Dec-2015 | 197 | 8 | 7 |
README
1Overview 2-------- 3The LS1043A Reference Design Board (RDB) is a high-performance computing, 4evaluation, and development platform that supports the QorIQ LS1043A 5LayerScape Architecture processor. The LS1043ARDB provides SW development 6platform for the Freescale LS1043A processor series, with a complete 7debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. 8 9LS1043A SoC Overview 10-------------------- 11Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A 12SoC overview. 13 14 LS1043ARDB board Overview 15 ----------------------- 16 - SERDES Connections, 4 lanes supporting: 17 - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and 18 standard PCIe card 19 - QSGMII with x4 RJ45 connector 20 - XFI with x1 RJ45 connector 21 - DDR Controller 22 - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s 23 -IFC/Local Bus 24 - One 128MB NOR flash 16-bit data bus 25 - One 512 MB NAND flash with ECC support 26 - CPLD connection 27 - USB 3.0 28 - Two super speed USB 3.0 Type A ports 29 - SDHC: connects directly to a full SD/MMC slot 30 - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) 31 - 4 I2C controllers 32 - UART 33 - Two 4-pin serial ports at up to 115.2 Kbit/s 34 - Two DB9 D-Type connectors supporting one Serial port each 35 - ARM JTAG support 36 37Memory map from core's view 38---------------------------- 39Start Address End Address Description Size 400x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB 410x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB 420x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB 430x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB 440x00_2000_0000 0x00_20FF_FFFF DCSR 16MB 450x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB 460x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB 470x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB 480x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB 49 50Booting Options 51--------------- 52a) NOR boot 53b) NAND boot 54c) SD boot 55