xref: /openbmc/qemu/include/hw/misc/aspeed_i3c.h (revision 119df56b)
1 /*
2  * ASPEED I3C Controller
3  *
4  * Copyright (C) 2021 ASPEED Technology Inc.
5  *
6  * This code is licensed under the GPL version 2 or later.  See
7  * the COPYING file in the top-level directory.
8  */
9 
10 #ifndef ASPEED_I3C_H
11 #define ASPEED_I3C_H
12 
13 #include "hw/sysbus.h"
14 
15 #define TYPE_ASPEED_I3C "aspeed.i3c"
16 #define TYPE_ASPEED_I3C_DEVICE "aspeed.i3c.device"
17 OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C)
18 
19 #define ASPEED_I3C_NR_REGS (0x70 >> 2)
20 #define ASPEED_I3C_DEVICE_NR_REGS (0x300 >> 2)
21 #define ASPEED_I3C_NR_DEVICES 6
22 
23 OBJECT_DECLARE_SIMPLE_TYPE(AspeedI3CDevice, ASPEED_I3C_DEVICE)
24 typedef struct AspeedI3CDevice {
25     /* <private> */
26     SysBusDevice parent;
27 
28     /* <public> */
29     MemoryRegion mr;
30     qemu_irq irq;
31 
32     uint8_t id;
33     uint32_t regs[ASPEED_I3C_DEVICE_NR_REGS];
34 } AspeedI3CDevice;
35 
36 typedef struct AspeedI3CState {
37     /* <private> */
38     SysBusDevice parent;
39 
40     /* <public> */
41     MemoryRegion iomem;
42     MemoryRegion iomem_container;
43     qemu_irq irq;
44 
45     uint32_t regs[ASPEED_I3C_NR_REGS];
46     AspeedI3CDevice devices[ASPEED_I3C_NR_DEVICES];
47 } AspeedI3CState;
48 #endif /* ASPEED_I3C_H */
49