History log of /openbmc/qemu/include/hw/misc/aspeed_i3c.h (Results 1 – 1 of 1)
Revision Date Author Comments
# 119df56b 11-Jan-2022 Troy Lee <troy_lee@aspeedtech.com>

hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model.

Aspeed 2600 SDK enables I3C support by default. The I3C driver will try
to reset the device controller and set it up through device addres

hw/misc/aspeed_i3c.c: Introduce a dummy AST2600 I3C model.

Aspeed 2600 SDK enables I3C support by default. The I3C driver will try
to reset the device controller and set it up through device address table
register. This dummy model responds to these registers with default values
as listed in the ast2600v10 datasheet chapter 54.2.

This avoids a guest machine kernel panic due to referencing an
invalid kernel address if the device address table register isn't
set correctly.

Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Graeme Gregory <quic_ggregory@quicinc.com>
Message-id: 20220111084546.4145785-2-troy_lee@aspeedtech.com
[PMM: tidied commit message; fixed format strings]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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