1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor 4 * 5 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> 6 * 7 * Based on OmniVision OV96xx Camera Driver 8 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com> 9 * 10 * Based on ov772x camera driver: 11 * Copyright (C) 2008 Renesas Solutions Corp. 12 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 13 * 14 * Based on ov7670 and soc_camera_platform driver, 15 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 16 * Copyright (C) 2008 Magnus Damm 17 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 18 * 19 * Hardware specific bits initially based on former work by Matt Callow 20 * drivers/media/video/omap/sensor_ov6650.c 21 * Copyright (C) 2006 Matt Callow 22 */ 23 24 #include <linux/bitops.h> 25 #include <linux/delay.h> 26 #include <linux/i2c.h> 27 #include <linux/slab.h> 28 #include <linux/v4l2-mediabus.h> 29 #include <linux/module.h> 30 31 #include <media/v4l2-clk.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-device.h> 34 35 /* Register definitions */ 36 #define REG_GAIN 0x00 /* range 00 - 3F */ 37 #define REG_BLUE 0x01 38 #define REG_RED 0x02 39 #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */ 40 #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */ 41 42 #define REG_BRT 0x06 43 44 #define REG_PIDH 0x0a 45 #define REG_PIDL 0x0b 46 47 #define REG_AECH 0x10 48 #define REG_CLKRC 0x11 /* Data Format and Internal Clock */ 49 /* [7:6] Input system clock (MHz)*/ 50 /* 00=8, 01=12, 10=16, 11=24 */ 51 /* [5:0]: Internal Clock Pre-Scaler */ 52 #define REG_COMA 0x12 /* [7] Reset */ 53 #define REG_COMB 0x13 54 #define REG_COMC 0x14 55 #define REG_COMD 0x15 56 #define REG_COML 0x16 57 #define REG_HSTRT 0x17 58 #define REG_HSTOP 0x18 59 #define REG_VSTRT 0x19 60 #define REG_VSTOP 0x1a 61 #define REG_PSHFT 0x1b 62 #define REG_MIDH 0x1c 63 #define REG_MIDL 0x1d 64 #define REG_HSYNS 0x1e 65 #define REG_HSYNE 0x1f 66 #define REG_COME 0x20 67 #define REG_YOFF 0x21 68 #define REG_UOFF 0x22 69 #define REG_VOFF 0x23 70 #define REG_AEW 0x24 71 #define REG_AEB 0x25 72 #define REG_COMF 0x26 73 #define REG_COMG 0x27 74 #define REG_COMH 0x28 75 #define REG_COMI 0x29 76 77 #define REG_FRARL 0x2b 78 #define REG_COMJ 0x2c 79 #define REG_COMK 0x2d 80 #define REG_AVGY 0x2e 81 #define REG_REF0 0x2f 82 #define REG_REF1 0x30 83 #define REG_REF2 0x31 84 #define REG_FRAJH 0x32 85 #define REG_FRAJL 0x33 86 #define REG_FACT 0x34 87 #define REG_L1AEC 0x35 88 #define REG_AVGU 0x36 89 #define REG_AVGV 0x37 90 91 #define REG_SPCB 0x60 92 #define REG_SPCC 0x61 93 #define REG_GAM1 0x62 94 #define REG_GAM2 0x63 95 #define REG_GAM3 0x64 96 #define REG_SPCD 0x65 97 98 #define REG_SPCE 0x68 99 #define REG_ADCL 0x69 100 101 #define REG_RMCO 0x6c 102 #define REG_GMCO 0x6d 103 #define REG_BMCO 0x6e 104 105 106 /* Register bits, values, etc. */ 107 #define OV6650_PIDH 0x66 /* high byte of product ID number */ 108 #define OV6650_PIDL 0x50 /* low byte of product ID number */ 109 #define OV6650_MIDH 0x7F /* high byte of mfg ID */ 110 #define OV6650_MIDL 0xA2 /* low byte of mfg ID */ 111 112 #define DEF_GAIN 0x00 113 #define DEF_BLUE 0x80 114 #define DEF_RED 0x80 115 116 #define SAT_SHIFT 4 117 #define SAT_MASK (0xf << SAT_SHIFT) 118 #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK) 119 120 #define HUE_EN BIT(5) 121 #define HUE_MASK 0x1f 122 #define DEF_HUE 0x10 123 #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK)) 124 125 #define DEF_AECH 0x4D 126 127 #define CLKRC_6MHz 0x00 128 #define CLKRC_12MHz 0x40 129 #define CLKRC_16MHz 0x80 130 #define CLKRC_24MHz 0xc0 131 #define CLKRC_DIV_MASK 0x3f 132 #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1) 133 134 #define COMA_RESET BIT(7) 135 #define COMA_QCIF BIT(5) 136 #define COMA_RAW_RGB BIT(4) 137 #define COMA_RGB BIT(3) 138 #define COMA_BW BIT(2) 139 #define COMA_WORD_SWAP BIT(1) 140 #define COMA_BYTE_SWAP BIT(0) 141 #define DEF_COMA 0x00 142 143 #define COMB_FLIP_V BIT(7) 144 #define COMB_FLIP_H BIT(5) 145 #define COMB_BAND_FILTER BIT(4) 146 #define COMB_AWB BIT(2) 147 #define COMB_AGC BIT(1) 148 #define COMB_AEC BIT(0) 149 #define DEF_COMB 0x5f 150 151 #define COML_ONE_CHANNEL BIT(7) 152 153 #define DEF_HSTRT 0x24 154 #define DEF_HSTOP 0xd4 155 #define DEF_VSTRT 0x04 156 #define DEF_VSTOP 0x94 157 158 #define COMF_HREF_LOW BIT(4) 159 160 #define COMJ_PCLK_RISING BIT(4) 161 #define COMJ_VSYNC_HIGH BIT(0) 162 163 /* supported resolutions */ 164 #define W_QCIF (DEF_HSTOP - DEF_HSTRT) 165 #define W_CIF (W_QCIF << 1) 166 #define H_QCIF (DEF_VSTOP - DEF_VSTRT) 167 #define H_CIF (H_QCIF << 1) 168 169 #define FRAME_RATE_MAX 30 170 171 172 struct ov6650_reg { 173 u8 reg; 174 u8 val; 175 }; 176 177 struct ov6650 { 178 struct v4l2_subdev subdev; 179 struct v4l2_ctrl_handler hdl; 180 struct { 181 /* exposure/autoexposure cluster */ 182 struct v4l2_ctrl *autoexposure; 183 struct v4l2_ctrl *exposure; 184 }; 185 struct { 186 /* gain/autogain cluster */ 187 struct v4l2_ctrl *autogain; 188 struct v4l2_ctrl *gain; 189 }; 190 struct { 191 /* blue/red/autowhitebalance cluster */ 192 struct v4l2_ctrl *autowb; 193 struct v4l2_ctrl *blue; 194 struct v4l2_ctrl *red; 195 }; 196 struct v4l2_clk *clk; 197 bool half_scale; /* scale down output by 2 */ 198 struct v4l2_rect rect; /* sensor cropping window */ 199 unsigned long pclk_limit; /* from host */ 200 unsigned long pclk_max; /* from resolution and format */ 201 struct v4l2_fract tpf; /* as requested with s_frame_interval */ 202 u32 code; 203 }; 204 205 206 static u32 ov6650_codes[] = { 207 MEDIA_BUS_FMT_YUYV8_2X8, 208 MEDIA_BUS_FMT_UYVY8_2X8, 209 MEDIA_BUS_FMT_YVYU8_2X8, 210 MEDIA_BUS_FMT_VYUY8_2X8, 211 MEDIA_BUS_FMT_SBGGR8_1X8, 212 MEDIA_BUS_FMT_Y8_1X8, 213 }; 214 215 static const struct v4l2_mbus_framefmt ov6650_def_fmt = { 216 .width = W_CIF, 217 .height = H_CIF, 218 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 219 .colorspace = V4L2_COLORSPACE_SRGB, 220 .field = V4L2_FIELD_NONE, 221 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT, 222 .quantization = V4L2_QUANTIZATION_DEFAULT, 223 .xfer_func = V4L2_XFER_FUNC_DEFAULT, 224 }; 225 226 /* read a register */ 227 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val) 228 { 229 int ret; 230 u8 data = reg; 231 struct i2c_msg msg = { 232 .addr = client->addr, 233 .flags = 0, 234 .len = 1, 235 .buf = &data, 236 }; 237 238 ret = i2c_transfer(client->adapter, &msg, 1); 239 if (ret < 0) 240 goto err; 241 242 msg.flags = I2C_M_RD; 243 ret = i2c_transfer(client->adapter, &msg, 1); 244 if (ret < 0) 245 goto err; 246 247 *val = data; 248 return 0; 249 250 err: 251 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg); 252 return ret; 253 } 254 255 /* write a register */ 256 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val) 257 { 258 int ret; 259 unsigned char data[2] = { reg, val }; 260 struct i2c_msg msg = { 261 .addr = client->addr, 262 .flags = 0, 263 .len = 2, 264 .buf = data, 265 }; 266 267 ret = i2c_transfer(client->adapter, &msg, 1); 268 udelay(100); 269 270 if (ret < 0) { 271 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg); 272 return ret; 273 } 274 return 0; 275 } 276 277 278 /* Read a register, alter its bits, write it back */ 279 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask) 280 { 281 u8 val; 282 int ret; 283 284 ret = ov6650_reg_read(client, reg, &val); 285 if (ret) { 286 dev_err(&client->dev, 287 "[Read]-Modify-Write of register 0x%02x failed!\n", 288 reg); 289 return ret; 290 } 291 292 val &= ~mask; 293 val |= set; 294 295 ret = ov6650_reg_write(client, reg, val); 296 if (ret) 297 dev_err(&client->dev, 298 "Read-Modify-[Write] of register 0x%02x failed!\n", 299 reg); 300 301 return ret; 302 } 303 304 static struct ov6650 *to_ov6650(const struct i2c_client *client) 305 { 306 return container_of(i2c_get_clientdata(client), struct ov6650, subdev); 307 } 308 309 /* Start/Stop streaming from the device */ 310 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable) 311 { 312 return 0; 313 } 314 315 /* Get status of additional camera capabilities */ 316 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl) 317 { 318 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl); 319 struct v4l2_subdev *sd = &priv->subdev; 320 struct i2c_client *client = v4l2_get_subdevdata(sd); 321 uint8_t reg, reg2; 322 int ret; 323 324 switch (ctrl->id) { 325 case V4L2_CID_AUTOGAIN: 326 ret = ov6650_reg_read(client, REG_GAIN, ®); 327 if (!ret) 328 priv->gain->val = reg; 329 return ret; 330 case V4L2_CID_AUTO_WHITE_BALANCE: 331 ret = ov6650_reg_read(client, REG_BLUE, ®); 332 if (!ret) 333 ret = ov6650_reg_read(client, REG_RED, ®2); 334 if (!ret) { 335 priv->blue->val = reg; 336 priv->red->val = reg2; 337 } 338 return ret; 339 case V4L2_CID_EXPOSURE_AUTO: 340 ret = ov6650_reg_read(client, REG_AECH, ®); 341 if (!ret) 342 priv->exposure->val = reg; 343 return ret; 344 } 345 return -EINVAL; 346 } 347 348 /* Set status of additional camera capabilities */ 349 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl) 350 { 351 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl); 352 struct v4l2_subdev *sd = &priv->subdev; 353 struct i2c_client *client = v4l2_get_subdevdata(sd); 354 int ret; 355 356 switch (ctrl->id) { 357 case V4L2_CID_AUTOGAIN: 358 ret = ov6650_reg_rmw(client, REG_COMB, 359 ctrl->val ? COMB_AGC : 0, COMB_AGC); 360 if (!ret && !ctrl->val) 361 ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val); 362 return ret; 363 case V4L2_CID_AUTO_WHITE_BALANCE: 364 ret = ov6650_reg_rmw(client, REG_COMB, 365 ctrl->val ? COMB_AWB : 0, COMB_AWB); 366 if (!ret && !ctrl->val) { 367 ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val); 368 if (!ret) 369 ret = ov6650_reg_write(client, REG_RED, 370 priv->red->val); 371 } 372 return ret; 373 case V4L2_CID_SATURATION: 374 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val), 375 SAT_MASK); 376 case V4L2_CID_HUE: 377 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val), 378 HUE_MASK); 379 case V4L2_CID_BRIGHTNESS: 380 return ov6650_reg_write(client, REG_BRT, ctrl->val); 381 case V4L2_CID_EXPOSURE_AUTO: 382 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val == 383 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC); 384 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL) 385 ret = ov6650_reg_write(client, REG_AECH, 386 priv->exposure->val); 387 return ret; 388 case V4L2_CID_GAMMA: 389 return ov6650_reg_write(client, REG_GAM1, ctrl->val); 390 case V4L2_CID_VFLIP: 391 return ov6650_reg_rmw(client, REG_COMB, 392 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V); 393 case V4L2_CID_HFLIP: 394 return ov6650_reg_rmw(client, REG_COMB, 395 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H); 396 } 397 398 return -EINVAL; 399 } 400 401 #ifdef CONFIG_VIDEO_ADV_DEBUG 402 static int ov6650_get_register(struct v4l2_subdev *sd, 403 struct v4l2_dbg_register *reg) 404 { 405 struct i2c_client *client = v4l2_get_subdevdata(sd); 406 int ret; 407 u8 val; 408 409 if (reg->reg & ~0xff) 410 return -EINVAL; 411 412 reg->size = 1; 413 414 ret = ov6650_reg_read(client, reg->reg, &val); 415 if (!ret) 416 reg->val = (__u64)val; 417 418 return ret; 419 } 420 421 static int ov6650_set_register(struct v4l2_subdev *sd, 422 const struct v4l2_dbg_register *reg) 423 { 424 struct i2c_client *client = v4l2_get_subdevdata(sd); 425 426 if (reg->reg & ~0xff || reg->val & ~0xff) 427 return -EINVAL; 428 429 return ov6650_reg_write(client, reg->reg, reg->val); 430 } 431 #endif 432 433 static int ov6650_s_power(struct v4l2_subdev *sd, int on) 434 { 435 struct i2c_client *client = v4l2_get_subdevdata(sd); 436 struct ov6650 *priv = to_ov6650(client); 437 int ret = 0; 438 439 if (on) 440 ret = v4l2_clk_enable(priv->clk); 441 else 442 v4l2_clk_disable(priv->clk); 443 444 return ret; 445 } 446 447 static int ov6650_get_selection(struct v4l2_subdev *sd, 448 struct v4l2_subdev_pad_config *cfg, 449 struct v4l2_subdev_selection *sel) 450 { 451 struct i2c_client *client = v4l2_get_subdevdata(sd); 452 struct ov6650 *priv = to_ov6650(client); 453 454 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 455 return -EINVAL; 456 457 switch (sel->target) { 458 case V4L2_SEL_TGT_CROP_BOUNDS: 459 sel->r.left = DEF_HSTRT << 1; 460 sel->r.top = DEF_VSTRT << 1; 461 sel->r.width = W_CIF; 462 sel->r.height = H_CIF; 463 return 0; 464 case V4L2_SEL_TGT_CROP: 465 sel->r = priv->rect; 466 return 0; 467 default: 468 return -EINVAL; 469 } 470 } 471 472 static int ov6650_set_selection(struct v4l2_subdev *sd, 473 struct v4l2_subdev_pad_config *cfg, 474 struct v4l2_subdev_selection *sel) 475 { 476 struct i2c_client *client = v4l2_get_subdevdata(sd); 477 struct ov6650 *priv = to_ov6650(client); 478 int ret; 479 480 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE || 481 sel->target != V4L2_SEL_TGT_CROP) 482 return -EINVAL; 483 484 v4l_bound_align_image(&sel->r.width, 2, W_CIF, 1, 485 &sel->r.height, 2, H_CIF, 1, 0); 486 v4l_bound_align_image(&sel->r.left, DEF_HSTRT << 1, 487 (DEF_HSTRT << 1) + W_CIF - (__s32)sel->r.width, 1, 488 &sel->r.top, DEF_VSTRT << 1, 489 (DEF_VSTRT << 1) + H_CIF - (__s32)sel->r.height, 490 1, 0); 491 492 ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1); 493 if (!ret) { 494 priv->rect.width += priv->rect.left - sel->r.left; 495 priv->rect.left = sel->r.left; 496 ret = ov6650_reg_write(client, REG_HSTOP, 497 (sel->r.left + sel->r.width) >> 1); 498 } 499 if (!ret) { 500 priv->rect.width = sel->r.width; 501 ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1); 502 } 503 if (!ret) { 504 priv->rect.height += priv->rect.top - sel->r.top; 505 priv->rect.top = sel->r.top; 506 ret = ov6650_reg_write(client, REG_VSTOP, 507 (sel->r.top + sel->r.height) >> 1); 508 } 509 if (!ret) 510 priv->rect.height = sel->r.height; 511 512 return ret; 513 } 514 515 static int ov6650_get_fmt(struct v4l2_subdev *sd, 516 struct v4l2_subdev_pad_config *cfg, 517 struct v4l2_subdev_format *format) 518 { 519 struct v4l2_mbus_framefmt *mf = &format->format; 520 struct i2c_client *client = v4l2_get_subdevdata(sd); 521 struct ov6650 *priv = to_ov6650(client); 522 523 if (format->pad) 524 return -EINVAL; 525 526 /* initialize response with default media bus frame format */ 527 *mf = ov6650_def_fmt; 528 529 /* update media bus format code and frame size */ 530 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 531 mf->width = cfg->try_fmt.width; 532 mf->height = cfg->try_fmt.height; 533 mf->code = cfg->try_fmt.code; 534 535 } else { 536 mf->width = priv->rect.width >> priv->half_scale; 537 mf->height = priv->rect.height >> priv->half_scale; 538 mf->code = priv->code; 539 } 540 return 0; 541 } 542 543 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect) 544 { 545 return width > rect->width >> 1 || height > rect->height >> 1; 546 } 547 548 static u8 to_clkrc(struct v4l2_fract *timeperframe, 549 unsigned long pclk_limit, unsigned long pclk_max) 550 { 551 unsigned long pclk; 552 553 if (timeperframe->numerator && timeperframe->denominator) 554 pclk = pclk_max * timeperframe->denominator / 555 (FRAME_RATE_MAX * timeperframe->numerator); 556 else 557 pclk = pclk_max; 558 559 if (pclk_limit && pclk_limit < pclk) 560 pclk = pclk_limit; 561 562 return (pclk_max - 1) / pclk; 563 } 564 565 /* set the format we will capture in */ 566 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf) 567 { 568 struct i2c_client *client = v4l2_get_subdevdata(sd); 569 struct ov6650 *priv = to_ov6650(client); 570 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect); 571 struct v4l2_subdev_selection sel = { 572 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 573 .target = V4L2_SEL_TGT_CROP, 574 .r.left = priv->rect.left + (priv->rect.width >> 1) - 575 (mf->width >> (1 - half_scale)), 576 .r.top = priv->rect.top + (priv->rect.height >> 1) - 577 (mf->height >> (1 - half_scale)), 578 .r.width = mf->width << half_scale, 579 .r.height = mf->height << half_scale, 580 }; 581 u32 code = mf->code; 582 unsigned long mclk, pclk; 583 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc; 584 int ret; 585 586 /* select color matrix configuration for given color encoding */ 587 switch (code) { 588 case MEDIA_BUS_FMT_Y8_1X8: 589 dev_dbg(&client->dev, "pixel format GREY8_1X8\n"); 590 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP; 591 coma_set |= COMA_BW; 592 break; 593 case MEDIA_BUS_FMT_YUYV8_2X8: 594 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n"); 595 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP; 596 coma_set |= COMA_WORD_SWAP; 597 break; 598 case MEDIA_BUS_FMT_YVYU8_2X8: 599 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n"); 600 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP | 601 COMA_BYTE_SWAP; 602 break; 603 case MEDIA_BUS_FMT_UYVY8_2X8: 604 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n"); 605 if (half_scale) { 606 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP; 607 coma_set |= COMA_BYTE_SWAP; 608 } else { 609 coma_mask |= COMA_RGB | COMA_BW; 610 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP; 611 } 612 break; 613 case MEDIA_BUS_FMT_VYUY8_2X8: 614 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n"); 615 if (half_scale) { 616 coma_mask |= COMA_RGB | COMA_BW; 617 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP; 618 } else { 619 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP; 620 coma_set |= COMA_BYTE_SWAP; 621 } 622 break; 623 case MEDIA_BUS_FMT_SBGGR8_1X8: 624 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n"); 625 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP; 626 coma_set |= COMA_RAW_RGB | COMA_RGB; 627 break; 628 default: 629 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code); 630 return -EINVAL; 631 } 632 633 if (code == MEDIA_BUS_FMT_Y8_1X8 || 634 code == MEDIA_BUS_FMT_SBGGR8_1X8) { 635 coml_mask = COML_ONE_CHANNEL; 636 coml_set = 0; 637 priv->pclk_max = 4000000; 638 } else { 639 coml_mask = 0; 640 coml_set = COML_ONE_CHANNEL; 641 priv->pclk_max = 8000000; 642 } 643 644 if (half_scale) { 645 dev_dbg(&client->dev, "max resolution: QCIF\n"); 646 coma_set |= COMA_QCIF; 647 priv->pclk_max /= 2; 648 } else { 649 dev_dbg(&client->dev, "max resolution: CIF\n"); 650 coma_mask |= COMA_QCIF; 651 } 652 653 clkrc = CLKRC_12MHz; 654 mclk = 12000000; 655 priv->pclk_limit = 1334000; 656 dev_dbg(&client->dev, "using 12MHz input clock\n"); 657 658 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max); 659 660 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc); 661 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n", 662 mclk / pclk, 10 * mclk % pclk / pclk); 663 664 ret = ov6650_set_selection(sd, NULL, &sel); 665 if (!ret) 666 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask); 667 if (!ret) 668 ret = ov6650_reg_write(client, REG_CLKRC, clkrc); 669 if (!ret) { 670 priv->half_scale = half_scale; 671 672 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask); 673 } 674 if (!ret) 675 priv->code = code; 676 677 return ret; 678 } 679 680 static int ov6650_set_fmt(struct v4l2_subdev *sd, 681 struct v4l2_subdev_pad_config *cfg, 682 struct v4l2_subdev_format *format) 683 { 684 struct v4l2_mbus_framefmt *mf = &format->format; 685 struct i2c_client *client = v4l2_get_subdevdata(sd); 686 struct ov6650 *priv = to_ov6650(client); 687 688 if (format->pad) 689 return -EINVAL; 690 691 if (is_unscaled_ok(mf->width, mf->height, &priv->rect)) 692 v4l_bound_align_image(&mf->width, 2, W_CIF, 1, 693 &mf->height, 2, H_CIF, 1, 0); 694 695 switch (mf->code) { 696 case MEDIA_BUS_FMT_Y10_1X10: 697 mf->code = MEDIA_BUS_FMT_Y8_1X8; 698 /* fall through */ 699 case MEDIA_BUS_FMT_Y8_1X8: 700 case MEDIA_BUS_FMT_YVYU8_2X8: 701 case MEDIA_BUS_FMT_YUYV8_2X8: 702 case MEDIA_BUS_FMT_VYUY8_2X8: 703 case MEDIA_BUS_FMT_UYVY8_2X8: 704 break; 705 default: 706 mf->code = MEDIA_BUS_FMT_SBGGR8_1X8; 707 /* fall through */ 708 case MEDIA_BUS_FMT_SBGGR8_1X8: 709 break; 710 } 711 712 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { 713 /* store media bus format code and frame size in pad config */ 714 cfg->try_fmt.width = mf->width; 715 cfg->try_fmt.height = mf->height; 716 cfg->try_fmt.code = mf->code; 717 718 /* return default mbus frame format updated with pad config */ 719 *mf = ov6650_def_fmt; 720 mf->width = cfg->try_fmt.width; 721 mf->height = cfg->try_fmt.height; 722 mf->code = cfg->try_fmt.code; 723 724 } else { 725 /* apply new media bus format code and frame size */ 726 int ret = ov6650_s_fmt(sd, mf); 727 728 if (ret) 729 return ret; 730 731 /* return default format updated with active size and code */ 732 *mf = ov6650_def_fmt; 733 mf->width = priv->rect.width >> priv->half_scale; 734 mf->height = priv->rect.height >> priv->half_scale; 735 mf->code = priv->code; 736 } 737 return 0; 738 } 739 740 static int ov6650_enum_mbus_code(struct v4l2_subdev *sd, 741 struct v4l2_subdev_pad_config *cfg, 742 struct v4l2_subdev_mbus_code_enum *code) 743 { 744 if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes)) 745 return -EINVAL; 746 747 code->code = ov6650_codes[code->index]; 748 return 0; 749 } 750 751 static int ov6650_g_frame_interval(struct v4l2_subdev *sd, 752 struct v4l2_subdev_frame_interval *ival) 753 { 754 struct i2c_client *client = v4l2_get_subdevdata(sd); 755 struct ov6650 *priv = to_ov6650(client); 756 757 ival->interval.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf, 758 priv->pclk_limit, priv->pclk_max)); 759 ival->interval.denominator = FRAME_RATE_MAX; 760 761 dev_dbg(&client->dev, "Frame interval: %u/%u s\n", 762 ival->interval.numerator, ival->interval.denominator); 763 764 return 0; 765 } 766 767 static int ov6650_s_frame_interval(struct v4l2_subdev *sd, 768 struct v4l2_subdev_frame_interval *ival) 769 { 770 struct i2c_client *client = v4l2_get_subdevdata(sd); 771 struct ov6650 *priv = to_ov6650(client); 772 struct v4l2_fract *tpf = &ival->interval; 773 int div, ret; 774 u8 clkrc; 775 776 if (tpf->numerator == 0 || tpf->denominator == 0) 777 div = 1; /* Reset to full rate */ 778 else 779 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator; 780 781 if (div == 0) 782 div = 1; 783 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK)) 784 div = GET_CLKRC_DIV(CLKRC_DIV_MASK); 785 786 /* 787 * Keep result to be used as tpf limit 788 * for subsequent clock divider calculations 789 */ 790 priv->tpf.numerator = div; 791 priv->tpf.denominator = FRAME_RATE_MAX; 792 793 clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max); 794 795 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK); 796 if (!ret) { 797 tpf->numerator = GET_CLKRC_DIV(clkrc); 798 tpf->denominator = FRAME_RATE_MAX; 799 } 800 801 return ret; 802 } 803 804 /* Soft reset the camera. This has nothing to do with the RESET pin! */ 805 static int ov6650_reset(struct i2c_client *client) 806 { 807 int ret; 808 809 dev_dbg(&client->dev, "reset\n"); 810 811 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0); 812 if (ret) 813 dev_err(&client->dev, 814 "An error occurred while entering soft reset!\n"); 815 816 return ret; 817 } 818 819 /* program default register values */ 820 static int ov6650_prog_dflt(struct i2c_client *client) 821 { 822 int ret; 823 824 dev_dbg(&client->dev, "initializing\n"); 825 826 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */ 827 if (!ret) 828 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER); 829 830 return ret; 831 } 832 833 static int ov6650_video_probe(struct v4l2_subdev *sd) 834 { 835 struct i2c_client *client = v4l2_get_subdevdata(sd); 836 struct ov6650 *priv = to_ov6650(client); 837 u8 pidh, pidl, midh, midl; 838 int ret; 839 840 priv->clk = v4l2_clk_get(&client->dev, NULL); 841 if (IS_ERR(priv->clk)) { 842 ret = PTR_ERR(priv->clk); 843 dev_err(&client->dev, "v4l2_clk request err: %d\n", ret); 844 return ret; 845 } 846 847 ret = ov6650_s_power(sd, 1); 848 if (ret < 0) 849 goto eclkput; 850 851 msleep(20); 852 853 /* 854 * check and show product ID and manufacturer ID 855 */ 856 ret = ov6650_reg_read(client, REG_PIDH, &pidh); 857 if (!ret) 858 ret = ov6650_reg_read(client, REG_PIDL, &pidl); 859 if (!ret) 860 ret = ov6650_reg_read(client, REG_MIDH, &midh); 861 if (!ret) 862 ret = ov6650_reg_read(client, REG_MIDL, &midl); 863 864 if (ret) 865 goto done; 866 867 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) { 868 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n", 869 pidh, pidl); 870 ret = -ENODEV; 871 goto done; 872 } 873 874 dev_info(&client->dev, 875 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n", 876 pidh, pidl, midh, midl); 877 878 ret = ov6650_reset(client); 879 if (!ret) 880 ret = ov6650_prog_dflt(client); 881 if (!ret) { 882 struct v4l2_mbus_framefmt mf = ov6650_def_fmt; 883 884 ret = ov6650_s_fmt(sd, &mf); 885 } 886 if (!ret) 887 ret = v4l2_ctrl_handler_setup(&priv->hdl); 888 889 done: 890 ov6650_s_power(sd, 0); 891 if (!ret) 892 return 0; 893 eclkput: 894 v4l2_clk_put(priv->clk); 895 896 return ret; 897 } 898 899 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = { 900 .g_volatile_ctrl = ov6550_g_volatile_ctrl, 901 .s_ctrl = ov6550_s_ctrl, 902 }; 903 904 static const struct v4l2_subdev_core_ops ov6650_core_ops = { 905 #ifdef CONFIG_VIDEO_ADV_DEBUG 906 .g_register = ov6650_get_register, 907 .s_register = ov6650_set_register, 908 #endif 909 .s_power = ov6650_s_power, 910 }; 911 912 /* Request bus settings on camera side */ 913 static int ov6650_g_mbus_config(struct v4l2_subdev *sd, 914 struct v4l2_mbus_config *cfg) 915 { 916 917 cfg->flags = V4L2_MBUS_MASTER | 918 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING | 919 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW | 920 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW | 921 V4L2_MBUS_DATA_ACTIVE_HIGH; 922 cfg->type = V4L2_MBUS_PARALLEL; 923 924 return 0; 925 } 926 927 /* Alter bus settings on camera side */ 928 static int ov6650_s_mbus_config(struct v4l2_subdev *sd, 929 const struct v4l2_mbus_config *cfg) 930 { 931 struct i2c_client *client = v4l2_get_subdevdata(sd); 932 int ret; 933 934 if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 935 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0); 936 else 937 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING); 938 if (ret) 939 return ret; 940 941 if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) 942 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0); 943 else 944 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW); 945 if (ret) 946 return ret; 947 948 if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 949 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0); 950 else 951 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH); 952 953 return ret; 954 } 955 956 static const struct v4l2_subdev_video_ops ov6650_video_ops = { 957 .s_stream = ov6650_s_stream, 958 .g_frame_interval = ov6650_g_frame_interval, 959 .s_frame_interval = ov6650_s_frame_interval, 960 .g_mbus_config = ov6650_g_mbus_config, 961 .s_mbus_config = ov6650_s_mbus_config, 962 }; 963 964 static const struct v4l2_subdev_pad_ops ov6650_pad_ops = { 965 .enum_mbus_code = ov6650_enum_mbus_code, 966 .get_selection = ov6650_get_selection, 967 .set_selection = ov6650_set_selection, 968 .get_fmt = ov6650_get_fmt, 969 .set_fmt = ov6650_set_fmt, 970 }; 971 972 static const struct v4l2_subdev_ops ov6650_subdev_ops = { 973 .core = &ov6650_core_ops, 974 .video = &ov6650_video_ops, 975 .pad = &ov6650_pad_ops, 976 }; 977 978 static const struct v4l2_subdev_internal_ops ov6650_internal_ops = { 979 .registered = ov6650_video_probe, 980 }; 981 982 /* 983 * i2c_driver function 984 */ 985 static int ov6650_probe(struct i2c_client *client, 986 const struct i2c_device_id *did) 987 { 988 struct ov6650 *priv; 989 int ret; 990 991 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); 992 if (!priv) 993 return -ENOMEM; 994 995 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops); 996 v4l2_ctrl_handler_init(&priv->hdl, 13); 997 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 998 V4L2_CID_VFLIP, 0, 1, 1, 0); 999 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1000 V4L2_CID_HFLIP, 0, 1, 1, 0); 1001 priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1002 V4L2_CID_AUTOGAIN, 0, 1, 1, 1); 1003 priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1004 V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN); 1005 priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1006 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); 1007 priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1008 V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE); 1009 priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1010 V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED); 1011 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1012 V4L2_CID_SATURATION, 0, 0xf, 1, 0x8); 1013 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1014 V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE); 1015 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1016 V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80); 1017 priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl, 1018 &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1019 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO); 1020 priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1021 V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH); 1022 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, 1023 V4L2_CID_GAMMA, 0, 0xff, 1, 0x12); 1024 1025 priv->subdev.ctrl_handler = &priv->hdl; 1026 if (priv->hdl.error) { 1027 ret = priv->hdl.error; 1028 goto ectlhdlfree; 1029 } 1030 1031 v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true); 1032 v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true); 1033 v4l2_ctrl_auto_cluster(2, &priv->autoexposure, 1034 V4L2_EXPOSURE_MANUAL, true); 1035 1036 priv->rect.left = DEF_HSTRT << 1; 1037 priv->rect.top = DEF_VSTRT << 1; 1038 priv->rect.width = W_CIF; 1039 priv->rect.height = H_CIF; 1040 1041 priv->subdev.internal_ops = &ov6650_internal_ops; 1042 1043 ret = v4l2_async_register_subdev(&priv->subdev); 1044 if (!ret) 1045 return 0; 1046 ectlhdlfree: 1047 v4l2_ctrl_handler_free(&priv->hdl); 1048 1049 return ret; 1050 } 1051 1052 static int ov6650_remove(struct i2c_client *client) 1053 { 1054 struct ov6650 *priv = to_ov6650(client); 1055 1056 v4l2_clk_put(priv->clk); 1057 v4l2_async_unregister_subdev(&priv->subdev); 1058 v4l2_ctrl_handler_free(&priv->hdl); 1059 return 0; 1060 } 1061 1062 static const struct i2c_device_id ov6650_id[] = { 1063 { "ov6650", 0 }, 1064 { } 1065 }; 1066 MODULE_DEVICE_TABLE(i2c, ov6650_id); 1067 1068 static struct i2c_driver ov6650_i2c_driver = { 1069 .driver = { 1070 .name = "ov6650", 1071 }, 1072 .probe = ov6650_probe, 1073 .remove = ov6650_remove, 1074 .id_table = ov6650_id, 1075 }; 1076 1077 module_i2c_driver(ov6650_i2c_driver); 1078 1079 MODULE_DESCRIPTION("V4L2 subdevice driver for OmniVision OV6650 camera sensor"); 1080 MODULE_AUTHOR("Janusz Krzysztofik <jmkrzyszt@gmail.com"); 1081 MODULE_LICENSE("GPL v2"); 1082