1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo"; 170 reg = <0x0 0x0>; 171 clocks = <&cpufreq_hw 0>; 172 enable-method = "psci"; 173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 174 &LITTLE_CPU_SLEEP_1 175 &CLUSTER_SLEEP_0>; 176 next-level-cache = <&L2_0>; 177 operating-points-v2 = <&cpu0_opp_table>; 178 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 179 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 180 qcom,freq-domain = <&cpufreq_hw 0>; 181 #cooling-cells = <2>; 182 L2_0: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 L3_0: l3-cache { 188 compatible = "cache"; 189 cache-level = <3>; 190 cache-unified; 191 }; 192 }; 193 }; 194 195 CPU1: cpu@100 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo"; 198 reg = <0x0 0x100>; 199 clocks = <&cpufreq_hw 0>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 next-level-cache = <&L2_100>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 qcom,freq-domain = <&cpufreq_hw 0>; 209 #cooling-cells = <2>; 210 L2_100: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU2: cpu@200 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo"; 221 reg = <0x0 0x200>; 222 clocks = <&cpufreq_hw 0>; 223 enable-method = "psci"; 224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 225 &LITTLE_CPU_SLEEP_1 226 &CLUSTER_SLEEP_0>; 227 next-level-cache = <&L2_200>; 228 operating-points-v2 = <&cpu0_opp_table>; 229 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 230 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 231 qcom,freq-domain = <&cpufreq_hw 0>; 232 #cooling-cells = <2>; 233 L2_200: l2-cache { 234 compatible = "cache"; 235 cache-level = <2>; 236 cache-unified; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 CPU3: cpu@300 { 242 device_type = "cpu"; 243 compatible = "qcom,kryo"; 244 reg = <0x0 0x300>; 245 clocks = <&cpufreq_hw 0>; 246 enable-method = "psci"; 247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 248 &LITTLE_CPU_SLEEP_1 249 &CLUSTER_SLEEP_0>; 250 next-level-cache = <&L2_300>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 254 qcom,freq-domain = <&cpufreq_hw 0>; 255 #cooling-cells = <2>; 256 L2_300: l2-cache { 257 compatible = "cache"; 258 cache-level = <2>; 259 cache-unified; 260 next-level-cache = <&L3_0>; 261 }; 262 }; 263 264 CPU4: cpu@400 { 265 device_type = "cpu"; 266 compatible = "qcom,kryo"; 267 reg = <0x0 0x400>; 268 clocks = <&cpufreq_hw 1>; 269 enable-method = "psci"; 270 cpu-idle-states = <&BIG_CPU_SLEEP_0 271 &BIG_CPU_SLEEP_1 272 &CLUSTER_SLEEP_0>; 273 next-level-cache = <&L2_400>; 274 operating-points-v2 = <&cpu4_opp_table>; 275 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 276 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 L2_400: l2-cache { 280 compatible = "cache"; 281 cache-level = <2>; 282 cache-unified; 283 next-level-cache = <&L3_0>; 284 }; 285 }; 286 287 CPU5: cpu@500 { 288 device_type = "cpu"; 289 compatible = "qcom,kryo"; 290 reg = <0x0 0x500>; 291 clocks = <&cpufreq_hw 1>; 292 enable-method = "psci"; 293 cpu-idle-states = <&BIG_CPU_SLEEP_0 294 &BIG_CPU_SLEEP_1 295 &CLUSTER_SLEEP_0>; 296 next-level-cache = <&L2_500>; 297 operating-points-v2 = <&cpu4_opp_table>; 298 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 299 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 300 qcom,freq-domain = <&cpufreq_hw 1>; 301 #cooling-cells = <2>; 302 L2_500: l2-cache { 303 compatible = "cache"; 304 cache-level = <2>; 305 cache-unified; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU6: cpu@600 { 311 device_type = "cpu"; 312 compatible = "qcom,kryo"; 313 reg = <0x0 0x600>; 314 clocks = <&cpufreq_hw 1>; 315 enable-method = "psci"; 316 cpu-idle-states = <&BIG_CPU_SLEEP_0 317 &BIG_CPU_SLEEP_1 318 &CLUSTER_SLEEP_0>; 319 next-level-cache = <&L2_600>; 320 operating-points-v2 = <&cpu4_opp_table>; 321 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 322 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 323 qcom,freq-domain = <&cpufreq_hw 1>; 324 #cooling-cells = <2>; 325 L2_600: l2-cache { 326 compatible = "cache"; 327 cache-level = <2>; 328 cache-unified; 329 next-level-cache = <&L3_0>; 330 }; 331 }; 332 333 CPU7: cpu@700 { 334 device_type = "cpu"; 335 compatible = "qcom,kryo"; 336 reg = <0x0 0x700>; 337 clocks = <&cpufreq_hw 2>; 338 enable-method = "psci"; 339 cpu-idle-states = <&BIG_CPU_SLEEP_0 340 &BIG_CPU_SLEEP_1 341 &CLUSTER_SLEEP_0>; 342 next-level-cache = <&L2_700>; 343 operating-points-v2 = <&cpu7_opp_table>; 344 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 345 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 346 qcom,freq-domain = <&cpufreq_hw 2>; 347 #cooling-cells = <2>; 348 L2_700: l2-cache { 349 compatible = "cache"; 350 cache-level = <2>; 351 cache-unified; 352 next-level-cache = <&L3_0>; 353 }; 354 }; 355 356 cpu-map { 357 cluster0 { 358 core0 { 359 cpu = <&CPU0>; 360 }; 361 362 core1 { 363 cpu = <&CPU1>; 364 }; 365 366 core2 { 367 cpu = <&CPU2>; 368 }; 369 370 core3 { 371 cpu = <&CPU3>; 372 }; 373 374 core4 { 375 cpu = <&CPU4>; 376 }; 377 378 core5 { 379 cpu = <&CPU5>; 380 }; 381 382 core6 { 383 cpu = <&CPU6>; 384 }; 385 386 core7 { 387 cpu = <&CPU7>; 388 }; 389 }; 390 }; 391 392 idle-states { 393 entry-method = "psci"; 394 395 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 396 compatible = "arm,idle-state"; 397 idle-state-name = "little-power-down"; 398 arm,psci-suspend-param = <0x40000003>; 399 entry-latency-us = <549>; 400 exit-latency-us = <901>; 401 min-residency-us = <1774>; 402 local-timer-stop; 403 }; 404 405 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 406 compatible = "arm,idle-state"; 407 idle-state-name = "little-rail-power-down"; 408 arm,psci-suspend-param = <0x40000004>; 409 entry-latency-us = <702>; 410 exit-latency-us = <915>; 411 min-residency-us = <4001>; 412 local-timer-stop; 413 }; 414 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 416 compatible = "arm,idle-state"; 417 idle-state-name = "big-power-down"; 418 arm,psci-suspend-param = <0x40000003>; 419 entry-latency-us = <523>; 420 exit-latency-us = <1244>; 421 min-residency-us = <2207>; 422 local-timer-stop; 423 }; 424 425 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 426 compatible = "arm,idle-state"; 427 idle-state-name = "big-rail-power-down"; 428 arm,psci-suspend-param = <0x40000004>; 429 entry-latency-us = <526>; 430 exit-latency-us = <1854>; 431 min-residency-us = <5555>; 432 local-timer-stop; 433 }; 434 435 CLUSTER_SLEEP_0: cluster-sleep-0 { 436 compatible = "arm,idle-state"; 437 idle-state-name = "cluster-power-down"; 438 arm,psci-suspend-param = <0x40003444>; 439 entry-latency-us = <3263>; 440 exit-latency-us = <6562>; 441 min-residency-us = <9926>; 442 local-timer-stop; 443 }; 444 }; 445 }; 446 447 cpu0_opp_table: opp-table-cpu0 { 448 compatible = "operating-points-v2"; 449 opp-shared; 450 451 cpu0_opp_300mhz: opp-300000000 { 452 opp-hz = /bits/ 64 <300000000>; 453 opp-peak-kBps = <800000 9600000>; 454 }; 455 456 cpu0_opp_691mhz: opp-691200000 { 457 opp-hz = /bits/ 64 <691200000>; 458 opp-peak-kBps = <800000 17817600>; 459 }; 460 461 cpu0_opp_806mhz: opp-806400000 { 462 opp-hz = /bits/ 64 <806400000>; 463 opp-peak-kBps = <800000 20889600>; 464 }; 465 466 cpu0_opp_941mhz: opp-940800000 { 467 opp-hz = /bits/ 64 <940800000>; 468 opp-peak-kBps = <1804000 24576000>; 469 }; 470 471 cpu0_opp_1152mhz: opp-1152000000 { 472 opp-hz = /bits/ 64 <1152000000>; 473 opp-peak-kBps = <2188000 27033600>; 474 }; 475 476 cpu0_opp_1325mhz: opp-1324800000 { 477 opp-hz = /bits/ 64 <1324800000>; 478 opp-peak-kBps = <2188000 33792000>; 479 }; 480 481 cpu0_opp_1517mhz: opp-1516800000 { 482 opp-hz = /bits/ 64 <1516800000>; 483 opp-peak-kBps = <3072000 38092800>; 484 }; 485 486 cpu0_opp_1651mhz: opp-1651200000 { 487 opp-hz = /bits/ 64 <1651200000>; 488 opp-peak-kBps = <3072000 41779200>; 489 }; 490 491 cpu0_opp_1805mhz: opp-1804800000 { 492 opp-hz = /bits/ 64 <1804800000>; 493 opp-peak-kBps = <4068000 48537600>; 494 }; 495 496 cpu0_opp_1958mhz: opp-1958400000 { 497 opp-hz = /bits/ 64 <1958400000>; 498 opp-peak-kBps = <4068000 48537600>; 499 }; 500 501 cpu0_opp_2016mhz: opp-2016000000 { 502 opp-hz = /bits/ 64 <2016000000>; 503 opp-peak-kBps = <6220000 48537600>; 504 }; 505 }; 506 507 cpu4_opp_table: opp-table-cpu4 { 508 compatible = "operating-points-v2"; 509 opp-shared; 510 511 cpu4_opp_691mhz: opp-691200000 { 512 opp-hz = /bits/ 64 <691200000>; 513 opp-peak-kBps = <1804000 9600000>; 514 }; 515 516 cpu4_opp_941mhz: opp-940800000 { 517 opp-hz = /bits/ 64 <940800000>; 518 opp-peak-kBps = <2188000 17817600>; 519 }; 520 521 cpu4_opp_1229mhz: opp-1228800000 { 522 opp-hz = /bits/ 64 <1228800000>; 523 opp-peak-kBps = <4068000 24576000>; 524 }; 525 526 cpu4_opp_1344mhz: opp-1344000000 { 527 opp-hz = /bits/ 64 <1344000000>; 528 opp-peak-kBps = <4068000 24576000>; 529 }; 530 531 cpu4_opp_1517mhz: opp-1516800000 { 532 opp-hz = /bits/ 64 <1516800000>; 533 opp-peak-kBps = <4068000 24576000>; 534 }; 535 536 cpu4_opp_1651mhz: opp-1651200000 { 537 opp-hz = /bits/ 64 <1651200000>; 538 opp-peak-kBps = <6220000 38092800>; 539 }; 540 541 cpu4_opp_1901mhz: opp-1900800000 { 542 opp-hz = /bits/ 64 <1900800000>; 543 opp-peak-kBps = <6220000 44851200>; 544 }; 545 546 cpu4_opp_2054mhz: opp-2054400000 { 547 opp-hz = /bits/ 64 <2054400000>; 548 opp-peak-kBps = <6220000 44851200>; 549 }; 550 551 cpu4_opp_2112mhz: opp-2112000000 { 552 opp-hz = /bits/ 64 <2112000000>; 553 opp-peak-kBps = <6220000 44851200>; 554 }; 555 556 cpu4_opp_2131mhz: opp-2131200000 { 557 opp-hz = /bits/ 64 <2131200000>; 558 opp-peak-kBps = <6220000 44851200>; 559 }; 560 561 cpu4_opp_2208mhz: opp-2208000000 { 562 opp-hz = /bits/ 64 <2208000000>; 563 opp-peak-kBps = <6220000 44851200>; 564 }; 565 566 cpu4_opp_2400mhz: opp-2400000000 { 567 opp-hz = /bits/ 64 <2400000000>; 568 opp-peak-kBps = <8532000 48537600>; 569 }; 570 571 cpu4_opp_2611mhz: opp-2611200000 { 572 opp-hz = /bits/ 64 <2611200000>; 573 opp-peak-kBps = <8532000 48537600>; 574 }; 575 }; 576 577 cpu7_opp_table: opp-table-cpu7 { 578 compatible = "operating-points-v2"; 579 opp-shared; 580 581 cpu7_opp_806mhz: opp-806400000 { 582 opp-hz = /bits/ 64 <806400000>; 583 opp-peak-kBps = <1804000 9600000>; 584 }; 585 586 cpu7_opp_1056mhz: opp-1056000000 { 587 opp-hz = /bits/ 64 <1056000000>; 588 opp-peak-kBps = <2188000 17817600>; 589 }; 590 591 cpu7_opp_1325mhz: opp-1324800000 { 592 opp-hz = /bits/ 64 <1324800000>; 593 opp-peak-kBps = <4068000 24576000>; 594 }; 595 596 cpu7_opp_1517mhz: opp-1516800000 { 597 opp-hz = /bits/ 64 <1516800000>; 598 opp-peak-kBps = <4068000 24576000>; 599 }; 600 601 cpu7_opp_1766mhz: opp-1766400000 { 602 opp-hz = /bits/ 64 <1766400000>; 603 opp-peak-kBps = <6220000 38092800>; 604 }; 605 606 cpu7_opp_1862mhz: opp-1862400000 { 607 opp-hz = /bits/ 64 <1862400000>; 608 opp-peak-kBps = <6220000 38092800>; 609 }; 610 611 cpu7_opp_2035mhz: opp-2035200000 { 612 opp-hz = /bits/ 64 <2035200000>; 613 opp-peak-kBps = <6220000 38092800>; 614 }; 615 616 cpu7_opp_2112mhz: opp-2112000000 { 617 opp-hz = /bits/ 64 <2112000000>; 618 opp-peak-kBps = <6220000 44851200>; 619 }; 620 621 cpu7_opp_2208mhz: opp-2208000000 { 622 opp-hz = /bits/ 64 <2208000000>; 623 opp-peak-kBps = <6220000 44851200>; 624 }; 625 626 cpu7_opp_2381mhz: opp-2380800000 { 627 opp-hz = /bits/ 64 <2380800000>; 628 opp-peak-kBps = <6832000 44851200>; 629 }; 630 631 cpu7_opp_2400mhz: opp-2400000000 { 632 opp-hz = /bits/ 64 <2400000000>; 633 opp-peak-kBps = <8532000 48537600>; 634 }; 635 636 cpu7_opp_2515mhz: opp-2515200000 { 637 opp-hz = /bits/ 64 <2515200000>; 638 opp-peak-kBps = <8532000 48537600>; 639 }; 640 641 cpu7_opp_2707mhz: opp-2707200000 { 642 opp-hz = /bits/ 64 <2707200000>; 643 opp-peak-kBps = <8532000 48537600>; 644 }; 645 646 cpu7_opp_3014mhz: opp-3014400000 { 647 opp-hz = /bits/ 64 <3014400000>; 648 opp-peak-kBps = <8532000 48537600>; 649 }; 650 }; 651 652 memory@80000000 { 653 device_type = "memory"; 654 /* We expect the bootloader to fill in the size */ 655 reg = <0 0x80000000 0 0>; 656 }; 657 658 firmware { 659 scm: scm { 660 compatible = "qcom,scm-sc7280", "qcom,scm"; 661 }; 662 }; 663 664 clk_virt: interconnect { 665 compatible = "qcom,sc7280-clk-virt"; 666 #interconnect-cells = <2>; 667 qcom,bcm-voters = <&apps_bcm_voter>; 668 }; 669 670 smem { 671 compatible = "qcom,smem"; 672 memory-region = <&smem_mem>; 673 hwlocks = <&tcsr_mutex 3>; 674 }; 675 676 smp2p-adsp { 677 compatible = "qcom,smp2p"; 678 qcom,smem = <443>, <429>; 679 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 680 IPCC_MPROC_SIGNAL_SMP2P 681 IRQ_TYPE_EDGE_RISING>; 682 mboxes = <&ipcc IPCC_CLIENT_LPASS 683 IPCC_MPROC_SIGNAL_SMP2P>; 684 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <2>; 687 688 adsp_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 adsp_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 smp2p-cdsp { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <94>, <432>; 703 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 704 IPCC_MPROC_SIGNAL_SMP2P 705 IRQ_TYPE_EDGE_RISING>; 706 mboxes = <&ipcc IPCC_CLIENT_CDSP 707 IPCC_MPROC_SIGNAL_SMP2P>; 708 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <5>; 711 712 cdsp_smp2p_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 cdsp_smp2p_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-mpss { 725 compatible = "qcom,smp2p"; 726 qcom,smem = <435>, <428>; 727 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 728 IPCC_MPROC_SIGNAL_SMP2P 729 IRQ_TYPE_EDGE_RISING>; 730 mboxes = <&ipcc IPCC_CLIENT_MPSS 731 IPCC_MPROC_SIGNAL_SMP2P>; 732 733 qcom,local-pid = <0>; 734 qcom,remote-pid = <1>; 735 736 modem_smp2p_out: master-kernel { 737 qcom,entry-name = "master-kernel"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 modem_smp2p_in: slave-kernel { 742 qcom,entry-name = "slave-kernel"; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 747 ipa_smp2p_out: ipa-ap-to-modem { 748 qcom,entry-name = "ipa"; 749 #qcom,smem-state-cells = <1>; 750 }; 751 752 ipa_smp2p_in: ipa-modem-to-ap { 753 qcom,entry-name = "ipa"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-wpss { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <617>, <616>; 762 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 763 IPCC_MPROC_SIGNAL_SMP2P 764 IRQ_TYPE_EDGE_RISING>; 765 mboxes = <&ipcc IPCC_CLIENT_WPSS 766 IPCC_MPROC_SIGNAL_SMP2P>; 767 768 qcom,local-pid = <0>; 769 qcom,remote-pid = <13>; 770 771 wpss_smp2p_out: master-kernel { 772 qcom,entry-name = "master-kernel"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 wpss_smp2p_in: slave-kernel { 777 qcom,entry-name = "slave-kernel"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 782 wlan_smp2p_out: wlan-ap-to-wpss { 783 qcom,entry-name = "wlan"; 784 #qcom,smem-state-cells = <1>; 785 }; 786 787 wlan_smp2p_in: wlan-wpss-to-ap { 788 qcom,entry-name = "wlan"; 789 interrupt-controller; 790 #interrupt-cells = <2>; 791 }; 792 }; 793 794 pmu { 795 compatible = "arm,armv8-pmuv3"; 796 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 797 }; 798 799 psci { 800 compatible = "arm,psci-1.0"; 801 method = "smc"; 802 }; 803 804 qspi_opp_table: opp-table-qspi { 805 compatible = "operating-points-v2"; 806 807 opp-75000000 { 808 opp-hz = /bits/ 64 <75000000>; 809 required-opps = <&rpmhpd_opp_low_svs>; 810 }; 811 812 opp-150000000 { 813 opp-hz = /bits/ 64 <150000000>; 814 required-opps = <&rpmhpd_opp_svs>; 815 }; 816 817 opp-200000000 { 818 opp-hz = /bits/ 64 <200000000>; 819 required-opps = <&rpmhpd_opp_svs_l1>; 820 }; 821 822 opp-300000000 { 823 opp-hz = /bits/ 64 <300000000>; 824 required-opps = <&rpmhpd_opp_nom>; 825 }; 826 }; 827 828 qup_opp_table: opp-table-qup { 829 compatible = "operating-points-v2"; 830 831 opp-75000000 { 832 opp-hz = /bits/ 64 <75000000>; 833 required-opps = <&rpmhpd_opp_low_svs>; 834 }; 835 836 opp-100000000 { 837 opp-hz = /bits/ 64 <100000000>; 838 required-opps = <&rpmhpd_opp_svs>; 839 }; 840 841 opp-128000000 { 842 opp-hz = /bits/ 64 <128000000>; 843 required-opps = <&rpmhpd_opp_nom>; 844 }; 845 }; 846 847 soc: soc@0 { 848 #address-cells = <2>; 849 #size-cells = <2>; 850 ranges = <0 0 0 0 0x10 0>; 851 dma-ranges = <0 0 0 0 0x10 0>; 852 compatible = "simple-bus"; 853 854 gcc: clock-controller@100000 { 855 compatible = "qcom,gcc-sc7280"; 856 reg = <0 0x00100000 0 0x1f0000>; 857 clocks = <&rpmhcc RPMH_CXO_CLK>, 858 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 859 <0>, <&pcie1_lane>, 860 <0>, <0>, <0>, 861 <&usb_1_ssphy>; 862 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 863 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 864 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 865 "ufs_phy_tx_symbol_0_clk", 866 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 867 #clock-cells = <1>; 868 #reset-cells = <1>; 869 #power-domain-cells = <1>; 870 power-domains = <&rpmhpd SC7280_CX>; 871 }; 872 873 ipcc: mailbox@408000 { 874 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 875 reg = <0 0x00408000 0 0x1000>; 876 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 877 interrupt-controller; 878 #interrupt-cells = <3>; 879 #mbox-cells = <2>; 880 }; 881 882 qfprom: efuse@784000 { 883 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 884 reg = <0 0x00784000 0 0xa20>, 885 <0 0x00780000 0 0xa20>, 886 <0 0x00782000 0 0x120>, 887 <0 0x00786000 0 0x1fff>; 888 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 889 clock-names = "core"; 890 power-domains = <&rpmhpd SC7280_MX>; 891 #address-cells = <1>; 892 #size-cells = <1>; 893 894 gpu_speed_bin: gpu_speed_bin@1e9 { 895 reg = <0x1e9 0x2>; 896 bits = <5 8>; 897 }; 898 }; 899 900 sdhc_1: mmc@7c4000 { 901 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 902 pinctrl-names = "default", "sleep"; 903 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 904 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 905 status = "disabled"; 906 907 reg = <0 0x007c4000 0 0x1000>, 908 <0 0x007c5000 0 0x1000>; 909 reg-names = "hc", "cqhci"; 910 911 iommus = <&apps_smmu 0xc0 0x0>; 912 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 914 interrupt-names = "hc_irq", "pwr_irq"; 915 916 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 917 <&gcc GCC_SDCC1_APPS_CLK>, 918 <&rpmhcc RPMH_CXO_CLK>; 919 clock-names = "iface", "core", "xo"; 920 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 922 interconnect-names = "sdhc-ddr","cpu-sdhc"; 923 power-domains = <&rpmhpd SC7280_CX>; 924 operating-points-v2 = <&sdhc1_opp_table>; 925 926 bus-width = <8>; 927 supports-cqe; 928 dma-coherent; 929 930 qcom,dll-config = <0x0007642c>; 931 qcom,ddr-config = <0x80040868>; 932 933 mmc-ddr-1_8v; 934 mmc-hs200-1_8v; 935 mmc-hs400-1_8v; 936 mmc-hs400-enhanced-strobe; 937 938 resets = <&gcc GCC_SDCC1_BCR>; 939 940 sdhc1_opp_table: opp-table { 941 compatible = "operating-points-v2"; 942 943 opp-100000000 { 944 opp-hz = /bits/ 64 <100000000>; 945 required-opps = <&rpmhpd_opp_low_svs>; 946 opp-peak-kBps = <1800000 400000>; 947 opp-avg-kBps = <100000 0>; 948 }; 949 950 opp-384000000 { 951 opp-hz = /bits/ 64 <384000000>; 952 required-opps = <&rpmhpd_opp_nom>; 953 opp-peak-kBps = <5400000 1600000>; 954 opp-avg-kBps = <390000 0>; 955 }; 956 }; 957 }; 958 959 gpi_dma0: dma-controller@900000 { 960 #dma-cells = <3>; 961 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 962 reg = <0 0x00900000 0 0x60000>; 963 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 975 dma-channels = <12>; 976 dma-channel-mask = <0x7f>; 977 iommus = <&apps_smmu 0x0136 0x0>; 978 status = "disabled"; 979 }; 980 981 qupv3_id_0: geniqup@9c0000 { 982 compatible = "qcom,geni-se-qup"; 983 reg = <0 0x009c0000 0 0x2000>; 984 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 985 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 986 clock-names = "m-ahb", "s-ahb"; 987 #address-cells = <2>; 988 #size-cells = <2>; 989 ranges; 990 iommus = <&apps_smmu 0x123 0x0>; 991 status = "disabled"; 992 993 i2c0: i2c@980000 { 994 compatible = "qcom,geni-i2c"; 995 reg = <0 0x00980000 0 0x4000>; 996 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 997 clock-names = "se"; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&qup_i2c0_data_clk>; 1000 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1004 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1005 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1006 interconnect-names = "qup-core", "qup-config", 1007 "qup-memory"; 1008 power-domains = <&rpmhpd SC7280_CX>; 1009 required-opps = <&rpmhpd_opp_low_svs>; 1010 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1011 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1012 dma-names = "tx", "rx"; 1013 status = "disabled"; 1014 }; 1015 1016 spi0: spi@980000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00980000 0 0x4000>; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1020 clock-names = "se"; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1023 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 power-domains = <&rpmhpd SC7280_CX>; 1027 operating-points-v2 = <&qup_opp_table>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1029 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1030 interconnect-names = "qup-core", "qup-config"; 1031 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1032 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1033 dma-names = "tx", "rx"; 1034 status = "disabled"; 1035 }; 1036 1037 uart0: serial@980000 { 1038 compatible = "qcom,geni-uart"; 1039 reg = <0 0x00980000 0 0x4000>; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1041 clock-names = "se"; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1044 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1045 power-domains = <&rpmhpd SC7280_CX>; 1046 operating-points-v2 = <&qup_opp_table>; 1047 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1048 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1049 interconnect-names = "qup-core", "qup-config"; 1050 status = "disabled"; 1051 }; 1052 1053 i2c1: i2c@984000 { 1054 compatible = "qcom,geni-i2c"; 1055 reg = <0 0x00984000 0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1057 clock-names = "se"; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_i2c1_data_clk>; 1060 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1064 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1065 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1066 interconnect-names = "qup-core", "qup-config", 1067 "qup-memory"; 1068 power-domains = <&rpmhpd SC7280_CX>; 1069 required-opps = <&rpmhpd_opp_low_svs>; 1070 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1071 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1072 dma-names = "tx", "rx"; 1073 status = "disabled"; 1074 }; 1075 1076 spi1: spi@984000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x00984000 0 0x4000>; 1079 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1080 clock-names = "se"; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1083 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 power-domains = <&rpmhpd SC7280_CX>; 1087 operating-points-v2 = <&qup_opp_table>; 1088 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1089 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1090 interconnect-names = "qup-core", "qup-config"; 1091 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1092 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1093 dma-names = "tx", "rx"; 1094 status = "disabled"; 1095 }; 1096 1097 uart1: serial@984000 { 1098 compatible = "qcom,geni-uart"; 1099 reg = <0 0x00984000 0 0x4000>; 1100 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1101 clock-names = "se"; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1104 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1105 power-domains = <&rpmhpd SC7280_CX>; 1106 operating-points-v2 = <&qup_opp_table>; 1107 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1108 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1109 interconnect-names = "qup-core", "qup-config"; 1110 status = "disabled"; 1111 }; 1112 1113 i2c2: i2c@988000 { 1114 compatible = "qcom,geni-i2c"; 1115 reg = <0 0x00988000 0 0x4000>; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1117 clock-names = "se"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_i2c2_data_clk>; 1120 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1124 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1125 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1126 interconnect-names = "qup-core", "qup-config", 1127 "qup-memory"; 1128 power-domains = <&rpmhpd SC7280_CX>; 1129 required-opps = <&rpmhpd_opp_low_svs>; 1130 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1131 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1132 dma-names = "tx", "rx"; 1133 status = "disabled"; 1134 }; 1135 1136 spi2: spi@988000 { 1137 compatible = "qcom,geni-spi"; 1138 reg = <0 0x00988000 0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1140 clock-names = "se"; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1143 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 power-domains = <&rpmhpd SC7280_CX>; 1147 operating-points-v2 = <&qup_opp_table>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1149 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1152 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1153 dma-names = "tx", "rx"; 1154 status = "disabled"; 1155 }; 1156 1157 uart2: serial@988000 { 1158 compatible = "qcom,geni-uart"; 1159 reg = <0 0x00988000 0 0x4000>; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1161 clock-names = "se"; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1164 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1165 power-domains = <&rpmhpd SC7280_CX>; 1166 operating-points-v2 = <&qup_opp_table>; 1167 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1168 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1169 interconnect-names = "qup-core", "qup-config"; 1170 status = "disabled"; 1171 }; 1172 1173 i2c3: i2c@98c000 { 1174 compatible = "qcom,geni-i2c"; 1175 reg = <0 0x0098c000 0 0x4000>; 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1177 clock-names = "se"; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&qup_i2c3_data_clk>; 1180 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1184 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1185 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1186 interconnect-names = "qup-core", "qup-config", 1187 "qup-memory"; 1188 power-domains = <&rpmhpd SC7280_CX>; 1189 required-opps = <&rpmhpd_opp_low_svs>; 1190 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1191 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1192 dma-names = "tx", "rx"; 1193 status = "disabled"; 1194 }; 1195 1196 spi3: spi@98c000 { 1197 compatible = "qcom,geni-spi"; 1198 reg = <0 0x0098c000 0 0x4000>; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1200 clock-names = "se"; 1201 pinctrl-names = "default"; 1202 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1203 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 power-domains = <&rpmhpd SC7280_CX>; 1207 operating-points-v2 = <&qup_opp_table>; 1208 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1209 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1210 interconnect-names = "qup-core", "qup-config"; 1211 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1212 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1213 dma-names = "tx", "rx"; 1214 status = "disabled"; 1215 }; 1216 1217 uart3: serial@98c000 { 1218 compatible = "qcom,geni-uart"; 1219 reg = <0 0x0098c000 0 0x4000>; 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1221 clock-names = "se"; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1224 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1225 power-domains = <&rpmhpd SC7280_CX>; 1226 operating-points-v2 = <&qup_opp_table>; 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1228 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1229 interconnect-names = "qup-core", "qup-config"; 1230 status = "disabled"; 1231 }; 1232 1233 i2c4: i2c@990000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0 0x00990000 0 0x4000>; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1237 clock-names = "se"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_i2c4_data_clk>; 1240 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1244 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1245 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1246 interconnect-names = "qup-core", "qup-config", 1247 "qup-memory"; 1248 power-domains = <&rpmhpd SC7280_CX>; 1249 required-opps = <&rpmhpd_opp_low_svs>; 1250 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1251 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1252 dma-names = "tx", "rx"; 1253 status = "disabled"; 1254 }; 1255 1256 spi4: spi@990000 { 1257 compatible = "qcom,geni-spi"; 1258 reg = <0 0x00990000 0 0x4000>; 1259 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1260 clock-names = "se"; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1263 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 power-domains = <&rpmhpd SC7280_CX>; 1267 operating-points-v2 = <&qup_opp_table>; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1269 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1270 interconnect-names = "qup-core", "qup-config"; 1271 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1272 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1273 dma-names = "tx", "rx"; 1274 status = "disabled"; 1275 }; 1276 1277 uart4: serial@990000 { 1278 compatible = "qcom,geni-uart"; 1279 reg = <0 0x00990000 0 0x4000>; 1280 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1281 clock-names = "se"; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1284 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1285 power-domains = <&rpmhpd SC7280_CX>; 1286 operating-points-v2 = <&qup_opp_table>; 1287 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1288 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1289 interconnect-names = "qup-core", "qup-config"; 1290 status = "disabled"; 1291 }; 1292 1293 i2c5: i2c@994000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0 0x00994000 0 0x4000>; 1296 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1297 clock-names = "se"; 1298 pinctrl-names = "default"; 1299 pinctrl-0 = <&qup_i2c5_data_clk>; 1300 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1304 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1305 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1306 interconnect-names = "qup-core", "qup-config", 1307 "qup-memory"; 1308 power-domains = <&rpmhpd SC7280_CX>; 1309 required-opps = <&rpmhpd_opp_low_svs>; 1310 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1311 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1312 dma-names = "tx", "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 spi5: spi@994000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0 0x00994000 0 0x4000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1320 clock-names = "se"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1323 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 power-domains = <&rpmhpd SC7280_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1329 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1330 interconnect-names = "qup-core", "qup-config"; 1331 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1332 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1333 dma-names = "tx", "rx"; 1334 status = "disabled"; 1335 }; 1336 1337 uart5: serial@994000 { 1338 compatible = "qcom,geni-uart"; 1339 reg = <0 0x00994000 0 0x4000>; 1340 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1341 clock-names = "se"; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1344 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmhpd SC7280_CX>; 1346 operating-points-v2 = <&qup_opp_table>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1349 interconnect-names = "qup-core", "qup-config"; 1350 status = "disabled"; 1351 }; 1352 1353 i2c6: i2c@998000 { 1354 compatible = "qcom,geni-i2c"; 1355 reg = <0 0x00998000 0 0x4000>; 1356 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1357 clock-names = "se"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_i2c6_data_clk>; 1360 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1364 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1365 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1366 interconnect-names = "qup-core", "qup-config", 1367 "qup-memory"; 1368 power-domains = <&rpmhpd SC7280_CX>; 1369 required-opps = <&rpmhpd_opp_low_svs>; 1370 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1371 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1372 dma-names = "tx", "rx"; 1373 status = "disabled"; 1374 }; 1375 1376 spi6: spi@998000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0 0x00998000 0 0x4000>; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1380 clock-names = "se"; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1383 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 power-domains = <&rpmhpd SC7280_CX>; 1387 operating-points-v2 = <&qup_opp_table>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1389 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1390 interconnect-names = "qup-core", "qup-config"; 1391 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1392 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1393 dma-names = "tx", "rx"; 1394 status = "disabled"; 1395 }; 1396 1397 uart6: serial@998000 { 1398 compatible = "qcom,geni-uart"; 1399 reg = <0 0x00998000 0 0x4000>; 1400 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1401 clock-names = "se"; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1404 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1405 power-domains = <&rpmhpd SC7280_CX>; 1406 operating-points-v2 = <&qup_opp_table>; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1408 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1409 interconnect-names = "qup-core", "qup-config"; 1410 status = "disabled"; 1411 }; 1412 1413 i2c7: i2c@99c000 { 1414 compatible = "qcom,geni-i2c"; 1415 reg = <0 0x0099c000 0 0x4000>; 1416 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1417 clock-names = "se"; 1418 pinctrl-names = "default"; 1419 pinctrl-0 = <&qup_i2c7_data_clk>; 1420 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1424 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1425 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1426 interconnect-names = "qup-core", "qup-config", 1427 "qup-memory"; 1428 power-domains = <&rpmhpd SC7280_CX>; 1429 required-opps = <&rpmhpd_opp_low_svs>; 1430 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1431 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1432 dma-names = "tx", "rx"; 1433 status = "disabled"; 1434 }; 1435 1436 spi7: spi@99c000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x0099c000 0 0x4000>; 1439 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1440 clock-names = "se"; 1441 pinctrl-names = "default"; 1442 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1443 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 power-domains = <&rpmhpd SC7280_CX>; 1447 operating-points-v2 = <&qup_opp_table>; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1449 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1450 interconnect-names = "qup-core", "qup-config"; 1451 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1452 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1453 dma-names = "tx", "rx"; 1454 status = "disabled"; 1455 }; 1456 1457 uart7: serial@99c000 { 1458 compatible = "qcom,geni-uart"; 1459 reg = <0 0x0099c000 0 0x4000>; 1460 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1461 clock-names = "se"; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1464 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1465 power-domains = <&rpmhpd SC7280_CX>; 1466 operating-points-v2 = <&qup_opp_table>; 1467 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1468 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1469 interconnect-names = "qup-core", "qup-config"; 1470 status = "disabled"; 1471 }; 1472 }; 1473 1474 gpi_dma1: dma-controller@a00000 { 1475 #dma-cells = <3>; 1476 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1477 reg = <0 0x00a00000 0 0x60000>; 1478 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1490 dma-channels = <12>; 1491 dma-channel-mask = <0x1e>; 1492 iommus = <&apps_smmu 0x56 0x0>; 1493 status = "disabled"; 1494 }; 1495 1496 qupv3_id_1: geniqup@ac0000 { 1497 compatible = "qcom,geni-se-qup"; 1498 reg = <0 0x00ac0000 0 0x2000>; 1499 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1500 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1501 clock-names = "m-ahb", "s-ahb"; 1502 #address-cells = <2>; 1503 #size-cells = <2>; 1504 ranges; 1505 iommus = <&apps_smmu 0x43 0x0>; 1506 status = "disabled"; 1507 1508 i2c8: i2c@a80000 { 1509 compatible = "qcom,geni-i2c"; 1510 reg = <0 0x00a80000 0 0x4000>; 1511 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1512 clock-names = "se"; 1513 pinctrl-names = "default"; 1514 pinctrl-0 = <&qup_i2c8_data_clk>; 1515 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1519 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1520 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1521 interconnect-names = "qup-core", "qup-config", 1522 "qup-memory"; 1523 power-domains = <&rpmhpd SC7280_CX>; 1524 required-opps = <&rpmhpd_opp_low_svs>; 1525 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1526 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1527 dma-names = "tx", "rx"; 1528 status = "disabled"; 1529 }; 1530 1531 spi8: spi@a80000 { 1532 compatible = "qcom,geni-spi"; 1533 reg = <0 0x00a80000 0 0x4000>; 1534 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1535 clock-names = "se"; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1538 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 power-domains = <&rpmhpd SC7280_CX>; 1542 operating-points-v2 = <&qup_opp_table>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1545 interconnect-names = "qup-core", "qup-config"; 1546 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1547 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1548 dma-names = "tx", "rx"; 1549 status = "disabled"; 1550 }; 1551 1552 uart8: serial@a80000 { 1553 compatible = "qcom,geni-uart"; 1554 reg = <0 0x00a80000 0 0x4000>; 1555 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1556 clock-names = "se"; 1557 pinctrl-names = "default"; 1558 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1559 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1560 power-domains = <&rpmhpd SC7280_CX>; 1561 operating-points-v2 = <&qup_opp_table>; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1563 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1564 interconnect-names = "qup-core", "qup-config"; 1565 status = "disabled"; 1566 }; 1567 1568 i2c9: i2c@a84000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0 0x00a84000 0 0x4000>; 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1572 clock-names = "se"; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c9_data_clk>; 1575 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1579 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1580 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1581 interconnect-names = "qup-core", "qup-config", 1582 "qup-memory"; 1583 power-domains = <&rpmhpd SC7280_CX>; 1584 required-opps = <&rpmhpd_opp_low_svs>; 1585 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1586 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1587 dma-names = "tx", "rx"; 1588 status = "disabled"; 1589 }; 1590 1591 spi9: spi@a84000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a84000 0 0x4000>; 1594 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1595 clock-names = "se"; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1598 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 power-domains = <&rpmhpd SC7280_CX>; 1602 operating-points-v2 = <&qup_opp_table>; 1603 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1604 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1605 interconnect-names = "qup-core", "qup-config"; 1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 status = "disabled"; 1610 }; 1611 1612 uart9: serial@a84000 { 1613 compatible = "qcom,geni-uart"; 1614 reg = <0 0x00a84000 0 0x4000>; 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1616 clock-names = "se"; 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1620 power-domains = <&rpmhpd SC7280_CX>; 1621 operating-points-v2 = <&qup_opp_table>; 1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1623 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1624 interconnect-names = "qup-core", "qup-config"; 1625 status = "disabled"; 1626 }; 1627 1628 i2c10: i2c@a88000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00a88000 0 0x4000>; 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1632 clock-names = "se"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_i2c10_data_clk>; 1635 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1639 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1640 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1641 interconnect-names = "qup-core", "qup-config", 1642 "qup-memory"; 1643 power-domains = <&rpmhpd SC7280_CX>; 1644 required-opps = <&rpmhpd_opp_low_svs>; 1645 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1646 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1647 dma-names = "tx", "rx"; 1648 status = "disabled"; 1649 }; 1650 1651 spi10: spi@a88000 { 1652 compatible = "qcom,geni-spi"; 1653 reg = <0 0x00a88000 0 0x4000>; 1654 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1655 clock-names = "se"; 1656 pinctrl-names = "default"; 1657 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1658 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 power-domains = <&rpmhpd SC7280_CX>; 1662 operating-points-v2 = <&qup_opp_table>; 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1664 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1665 interconnect-names = "qup-core", "qup-config"; 1666 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1667 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1668 dma-names = "tx", "rx"; 1669 status = "disabled"; 1670 }; 1671 1672 uart10: serial@a88000 { 1673 compatible = "qcom,geni-uart"; 1674 reg = <0 0x00a88000 0 0x4000>; 1675 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1676 clock-names = "se"; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1679 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1680 power-domains = <&rpmhpd SC7280_CX>; 1681 operating-points-v2 = <&qup_opp_table>; 1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1683 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1684 interconnect-names = "qup-core", "qup-config"; 1685 status = "disabled"; 1686 }; 1687 1688 i2c11: i2c@a8c000 { 1689 compatible = "qcom,geni-i2c"; 1690 reg = <0 0x00a8c000 0 0x4000>; 1691 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1692 clock-names = "se"; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_i2c11_data_clk>; 1695 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1699 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1700 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1701 interconnect-names = "qup-core", "qup-config", 1702 "qup-memory"; 1703 power-domains = <&rpmhpd SC7280_CX>; 1704 required-opps = <&rpmhpd_opp_low_svs>; 1705 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1706 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1707 dma-names = "tx", "rx"; 1708 status = "disabled"; 1709 }; 1710 1711 spi11: spi@a8c000 { 1712 compatible = "qcom,geni-spi"; 1713 reg = <0 0x00a8c000 0 0x4000>; 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1715 clock-names = "se"; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1718 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 power-domains = <&rpmhpd SC7280_CX>; 1722 operating-points-v2 = <&qup_opp_table>; 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1724 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1725 interconnect-names = "qup-core", "qup-config"; 1726 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1727 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1728 dma-names = "tx", "rx"; 1729 status = "disabled"; 1730 }; 1731 1732 uart11: serial@a8c000 { 1733 compatible = "qcom,geni-uart"; 1734 reg = <0 0x00a8c000 0 0x4000>; 1735 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1736 clock-names = "se"; 1737 pinctrl-names = "default"; 1738 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1739 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1740 power-domains = <&rpmhpd SC7280_CX>; 1741 operating-points-v2 = <&qup_opp_table>; 1742 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1743 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1744 interconnect-names = "qup-core", "qup-config"; 1745 status = "disabled"; 1746 }; 1747 1748 i2c12: i2c@a90000 { 1749 compatible = "qcom,geni-i2c"; 1750 reg = <0 0x00a90000 0 0x4000>; 1751 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1752 clock-names = "se"; 1753 pinctrl-names = "default"; 1754 pinctrl-0 = <&qup_i2c12_data_clk>; 1755 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1759 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1760 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1761 interconnect-names = "qup-core", "qup-config", 1762 "qup-memory"; 1763 power-domains = <&rpmhpd SC7280_CX>; 1764 required-opps = <&rpmhpd_opp_low_svs>; 1765 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1766 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1767 dma-names = "tx", "rx"; 1768 status = "disabled"; 1769 }; 1770 1771 spi12: spi@a90000 { 1772 compatible = "qcom,geni-spi"; 1773 reg = <0 0x00a90000 0 0x4000>; 1774 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1775 clock-names = "se"; 1776 pinctrl-names = "default"; 1777 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1778 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1779 #address-cells = <1>; 1780 #size-cells = <0>; 1781 power-domains = <&rpmhpd SC7280_CX>; 1782 operating-points-v2 = <&qup_opp_table>; 1783 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1784 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1785 interconnect-names = "qup-core", "qup-config"; 1786 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1787 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1788 dma-names = "tx", "rx"; 1789 status = "disabled"; 1790 }; 1791 1792 uart12: serial@a90000 { 1793 compatible = "qcom,geni-uart"; 1794 reg = <0 0x00a90000 0 0x4000>; 1795 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1796 clock-names = "se"; 1797 pinctrl-names = "default"; 1798 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1799 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1800 power-domains = <&rpmhpd SC7280_CX>; 1801 operating-points-v2 = <&qup_opp_table>; 1802 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1803 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1804 interconnect-names = "qup-core", "qup-config"; 1805 status = "disabled"; 1806 }; 1807 1808 i2c13: i2c@a94000 { 1809 compatible = "qcom,geni-i2c"; 1810 reg = <0 0x00a94000 0 0x4000>; 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1812 clock-names = "se"; 1813 pinctrl-names = "default"; 1814 pinctrl-0 = <&qup_i2c13_data_clk>; 1815 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1819 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1820 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1821 interconnect-names = "qup-core", "qup-config", 1822 "qup-memory"; 1823 power-domains = <&rpmhpd SC7280_CX>; 1824 required-opps = <&rpmhpd_opp_low_svs>; 1825 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1826 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1827 dma-names = "tx", "rx"; 1828 status = "disabled"; 1829 }; 1830 1831 spi13: spi@a94000 { 1832 compatible = "qcom,geni-spi"; 1833 reg = <0 0x00a94000 0 0x4000>; 1834 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1835 clock-names = "se"; 1836 pinctrl-names = "default"; 1837 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1838 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 power-domains = <&rpmhpd SC7280_CX>; 1842 operating-points-v2 = <&qup_opp_table>; 1843 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1844 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1845 interconnect-names = "qup-core", "qup-config"; 1846 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1847 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1848 dma-names = "tx", "rx"; 1849 status = "disabled"; 1850 }; 1851 1852 uart13: serial@a94000 { 1853 compatible = "qcom,geni-uart"; 1854 reg = <0 0x00a94000 0 0x4000>; 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1856 clock-names = "se"; 1857 pinctrl-names = "default"; 1858 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1859 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1860 power-domains = <&rpmhpd SC7280_CX>; 1861 operating-points-v2 = <&qup_opp_table>; 1862 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1863 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1864 interconnect-names = "qup-core", "qup-config"; 1865 status = "disabled"; 1866 }; 1867 1868 i2c14: i2c@a98000 { 1869 compatible = "qcom,geni-i2c"; 1870 reg = <0 0x00a98000 0 0x4000>; 1871 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1872 clock-names = "se"; 1873 pinctrl-names = "default"; 1874 pinctrl-0 = <&qup_i2c14_data_clk>; 1875 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1879 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1880 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1881 interconnect-names = "qup-core", "qup-config", 1882 "qup-memory"; 1883 power-domains = <&rpmhpd SC7280_CX>; 1884 required-opps = <&rpmhpd_opp_low_svs>; 1885 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1886 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1887 dma-names = "tx", "rx"; 1888 status = "disabled"; 1889 }; 1890 1891 spi14: spi@a98000 { 1892 compatible = "qcom,geni-spi"; 1893 reg = <0 0x00a98000 0 0x4000>; 1894 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1895 clock-names = "se"; 1896 pinctrl-names = "default"; 1897 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1898 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1899 #address-cells = <1>; 1900 #size-cells = <0>; 1901 power-domains = <&rpmhpd SC7280_CX>; 1902 operating-points-v2 = <&qup_opp_table>; 1903 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1904 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1905 interconnect-names = "qup-core", "qup-config"; 1906 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1907 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1908 dma-names = "tx", "rx"; 1909 status = "disabled"; 1910 }; 1911 1912 uart14: serial@a98000 { 1913 compatible = "qcom,geni-uart"; 1914 reg = <0 0x00a98000 0 0x4000>; 1915 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1916 clock-names = "se"; 1917 pinctrl-names = "default"; 1918 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1919 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1920 power-domains = <&rpmhpd SC7280_CX>; 1921 operating-points-v2 = <&qup_opp_table>; 1922 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1923 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1924 interconnect-names = "qup-core", "qup-config"; 1925 status = "disabled"; 1926 }; 1927 1928 i2c15: i2c@a9c000 { 1929 compatible = "qcom,geni-i2c"; 1930 reg = <0 0x00a9c000 0 0x4000>; 1931 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1932 clock-names = "se"; 1933 pinctrl-names = "default"; 1934 pinctrl-0 = <&qup_i2c15_data_clk>; 1935 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1936 #address-cells = <1>; 1937 #size-cells = <0>; 1938 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1939 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1940 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1941 interconnect-names = "qup-core", "qup-config", 1942 "qup-memory"; 1943 power-domains = <&rpmhpd SC7280_CX>; 1944 required-opps = <&rpmhpd_opp_low_svs>; 1945 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1946 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1947 dma-names = "tx", "rx"; 1948 status = "disabled"; 1949 }; 1950 1951 spi15: spi@a9c000 { 1952 compatible = "qcom,geni-spi"; 1953 reg = <0 0x00a9c000 0 0x4000>; 1954 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1955 clock-names = "se"; 1956 pinctrl-names = "default"; 1957 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1958 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 power-domains = <&rpmhpd SC7280_CX>; 1962 operating-points-v2 = <&qup_opp_table>; 1963 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1964 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1965 interconnect-names = "qup-core", "qup-config"; 1966 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1967 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1968 dma-names = "tx", "rx"; 1969 status = "disabled"; 1970 }; 1971 1972 uart15: serial@a9c000 { 1973 compatible = "qcom,geni-uart"; 1974 reg = <0 0x00a9c000 0 0x4000>; 1975 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1976 clock-names = "se"; 1977 pinctrl-names = "default"; 1978 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1979 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1980 power-domains = <&rpmhpd SC7280_CX>; 1981 operating-points-v2 = <&qup_opp_table>; 1982 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1983 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1984 interconnect-names = "qup-core", "qup-config"; 1985 status = "disabled"; 1986 }; 1987 }; 1988 1989 cnoc2: interconnect@1500000 { 1990 reg = <0 0x01500000 0 0x1000>; 1991 compatible = "qcom,sc7280-cnoc2"; 1992 #interconnect-cells = <2>; 1993 qcom,bcm-voters = <&apps_bcm_voter>; 1994 }; 1995 1996 cnoc3: interconnect@1502000 { 1997 reg = <0 0x01502000 0 0x1000>; 1998 compatible = "qcom,sc7280-cnoc3"; 1999 #interconnect-cells = <2>; 2000 qcom,bcm-voters = <&apps_bcm_voter>; 2001 }; 2002 2003 mc_virt: interconnect@1580000 { 2004 reg = <0 0x01580000 0 0x4>; 2005 compatible = "qcom,sc7280-mc-virt"; 2006 #interconnect-cells = <2>; 2007 qcom,bcm-voters = <&apps_bcm_voter>; 2008 }; 2009 2010 system_noc: interconnect@1680000 { 2011 reg = <0 0x01680000 0 0x15480>; 2012 compatible = "qcom,sc7280-system-noc"; 2013 #interconnect-cells = <2>; 2014 qcom,bcm-voters = <&apps_bcm_voter>; 2015 }; 2016 2017 aggre1_noc: interconnect@16e0000 { 2018 compatible = "qcom,sc7280-aggre1-noc"; 2019 reg = <0 0x016e0000 0 0x1c080>; 2020 #interconnect-cells = <2>; 2021 qcom,bcm-voters = <&apps_bcm_voter>; 2022 }; 2023 2024 aggre2_noc: interconnect@1700000 { 2025 reg = <0 0x01700000 0 0x2b080>; 2026 compatible = "qcom,sc7280-aggre2-noc"; 2027 #interconnect-cells = <2>; 2028 qcom,bcm-voters = <&apps_bcm_voter>; 2029 }; 2030 2031 mmss_noc: interconnect@1740000 { 2032 reg = <0 0x01740000 0 0x1e080>; 2033 compatible = "qcom,sc7280-mmss-noc"; 2034 #interconnect-cells = <2>; 2035 qcom,bcm-voters = <&apps_bcm_voter>; 2036 }; 2037 2038 wifi: wifi@17a10040 { 2039 compatible = "qcom,wcn6750-wifi"; 2040 reg = <0 0x17a10040 0 0x0>; 2041 iommus = <&apps_smmu 0x1c00 0x1>; 2042 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2047 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2048 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2049 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2050 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2051 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2052 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2066 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2067 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2068 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2069 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2070 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2071 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2072 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2073 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2074 qcom,rproc = <&remoteproc_wpss>; 2075 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2076 status = "disabled"; 2077 qcom,smem-states = <&wlan_smp2p_out 0>; 2078 qcom,smem-state-names = "wlan-smp2p-out"; 2079 }; 2080 2081 pcie1: pci@1c08000 { 2082 compatible = "qcom,pcie-sc7280"; 2083 reg = <0 0x01c08000 0 0x3000>, 2084 <0 0x40000000 0 0xf1d>, 2085 <0 0x40000f20 0 0xa8>, 2086 <0 0x40001000 0 0x1000>, 2087 <0 0x40100000 0 0x100000>; 2088 2089 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2090 device_type = "pci"; 2091 linux,pci-domain = <1>; 2092 bus-range = <0x00 0xff>; 2093 num-lanes = <2>; 2094 2095 #address-cells = <3>; 2096 #size-cells = <2>; 2097 2098 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2099 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2100 2101 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2109 interrupt-names = "msi0", "msi1", "msi2", "msi3", 2110 "msi4", "msi5", "msi6", "msi7"; 2111 #interrupt-cells = <1>; 2112 interrupt-map-mask = <0 0 0 0x7>; 2113 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2114 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2115 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2116 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2117 2118 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2119 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2120 <&pcie1_lane>, 2121 <&rpmhcc RPMH_CXO_CLK>, 2122 <&gcc GCC_PCIE_1_AUX_CLK>, 2123 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2124 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2125 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2126 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2127 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2128 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2129 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2130 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2131 2132 clock-names = "pipe", 2133 "pipe_mux", 2134 "phy_pipe", 2135 "ref", 2136 "aux", 2137 "cfg", 2138 "bus_master", 2139 "bus_slave", 2140 "slave_q2a", 2141 "tbu", 2142 "ddrss_sf_tbu", 2143 "aggre0", 2144 "aggre1"; 2145 2146 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2147 assigned-clock-rates = <19200000>; 2148 2149 resets = <&gcc GCC_PCIE_1_BCR>; 2150 reset-names = "pci"; 2151 2152 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2153 2154 phys = <&pcie1_lane>; 2155 phy-names = "pciephy"; 2156 2157 pinctrl-names = "default"; 2158 pinctrl-0 = <&pcie1_clkreq_n>; 2159 2160 dma-coherent; 2161 2162 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2163 <0x100 &apps_smmu 0x1c81 0x1>; 2164 2165 status = "disabled"; 2166 }; 2167 2168 pcie1_phy: phy@1c0e000 { 2169 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2170 reg = <0 0x01c0e000 0 0x1c0>; 2171 #address-cells = <2>; 2172 #size-cells = <2>; 2173 ranges; 2174 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2175 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2176 <&gcc GCC_PCIE_CLKREF_EN>, 2177 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2178 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2179 2180 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2181 reset-names = "phy"; 2182 2183 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2184 assigned-clock-rates = <100000000>; 2185 2186 status = "disabled"; 2187 2188 pcie1_lane: phy@1c0e200 { 2189 reg = <0 0x01c0e200 0 0x170>, 2190 <0 0x01c0e400 0 0x200>, 2191 <0 0x01c0ea00 0 0x1f0>, 2192 <0 0x01c0e600 0 0x170>, 2193 <0 0x01c0e800 0 0x200>, 2194 <0 0x01c0ee00 0 0xf4>; 2195 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2196 clock-names = "pipe0"; 2197 2198 #phy-cells = <0>; 2199 #clock-cells = <0>; 2200 clock-output-names = "pcie_1_pipe_clk"; 2201 }; 2202 }; 2203 2204 ipa: ipa@1e40000 { 2205 compatible = "qcom,sc7280-ipa"; 2206 2207 iommus = <&apps_smmu 0x480 0x0>, 2208 <&apps_smmu 0x482 0x0>; 2209 reg = <0 0x01e40000 0 0x8000>, 2210 <0 0x01e50000 0 0x4ad0>, 2211 <0 0x01e04000 0 0x23000>; 2212 reg-names = "ipa-reg", 2213 "ipa-shared", 2214 "gsi"; 2215 2216 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2217 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2218 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2219 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2220 interrupt-names = "ipa", 2221 "gsi", 2222 "ipa-clock-query", 2223 "ipa-setup-ready"; 2224 2225 clocks = <&rpmhcc RPMH_IPA_CLK>; 2226 clock-names = "core"; 2227 2228 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2229 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2230 interconnect-names = "memory", 2231 "config"; 2232 2233 qcom,qmp = <&aoss_qmp>; 2234 2235 qcom,smem-states = <&ipa_smp2p_out 0>, 2236 <&ipa_smp2p_out 1>; 2237 qcom,smem-state-names = "ipa-clock-enabled-valid", 2238 "ipa-clock-enabled"; 2239 2240 status = "disabled"; 2241 }; 2242 2243 tcsr_mutex: hwlock@1f40000 { 2244 compatible = "qcom,tcsr-mutex"; 2245 reg = <0 0x01f40000 0 0x20000>; 2246 #hwlock-cells = <1>; 2247 }; 2248 2249 tcsr_1: syscon@1f60000 { 2250 compatible = "qcom,sc7280-tcsr", "syscon"; 2251 reg = <0 0x01f60000 0 0x20000>; 2252 }; 2253 2254 tcsr_2: syscon@1fc0000 { 2255 compatible = "qcom,sc7280-tcsr", "syscon"; 2256 reg = <0 0x01fc0000 0 0x30000>; 2257 }; 2258 2259 lpasscc: lpasscc@3000000 { 2260 compatible = "qcom,sc7280-lpasscc"; 2261 reg = <0 0x03000000 0 0x40>, 2262 <0 0x03c04000 0 0x4>; 2263 reg-names = "qdsp6ss", "top_cc"; 2264 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2265 clock-names = "iface"; 2266 #clock-cells = <1>; 2267 status = "reserved"; /* Owned by ADSP firmware */ 2268 }; 2269 2270 lpass_rx_macro: codec@3200000 { 2271 compatible = "qcom,sc7280-lpass-rx-macro"; 2272 reg = <0 0x03200000 0 0x1000>; 2273 2274 pinctrl-names = "default"; 2275 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2276 2277 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2278 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2279 <&lpass_va_macro>; 2280 clock-names = "mclk", "npl", "fsgen"; 2281 2282 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2283 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2284 power-domain-names = "macro", "dcodec"; 2285 2286 #clock-cells = <0>; 2287 #sound-dai-cells = <1>; 2288 2289 status = "disabled"; 2290 }; 2291 2292 swr0: soundwire@3210000 { 2293 compatible = "qcom,soundwire-v1.6.0"; 2294 reg = <0 0x03210000 0 0x2000>; 2295 2296 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2297 clocks = <&lpass_rx_macro>; 2298 clock-names = "iface"; 2299 2300 qcom,din-ports = <0>; 2301 qcom,dout-ports = <5>; 2302 2303 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2304 reset-names = "swr_audio_cgcr"; 2305 2306 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2307 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2308 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2309 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2310 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2311 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2312 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2313 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2314 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2315 2316 #sound-dai-cells = <1>; 2317 #address-cells = <2>; 2318 #size-cells = <0>; 2319 2320 status = "disabled"; 2321 }; 2322 2323 lpass_tx_macro: codec@3220000 { 2324 compatible = "qcom,sc7280-lpass-tx-macro"; 2325 reg = <0 0x03220000 0 0x1000>; 2326 2327 pinctrl-names = "default"; 2328 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2329 2330 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2331 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2332 <&lpass_va_macro>; 2333 clock-names = "mclk", "npl", "fsgen"; 2334 2335 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2336 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2337 power-domain-names = "macro", "dcodec"; 2338 2339 #clock-cells = <0>; 2340 #sound-dai-cells = <1>; 2341 2342 status = "disabled"; 2343 }; 2344 2345 swr1: soundwire@3230000 { 2346 compatible = "qcom,soundwire-v1.6.0"; 2347 reg = <0 0x03230000 0 0x2000>; 2348 2349 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2350 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2351 clocks = <&lpass_tx_macro>; 2352 clock-names = "iface"; 2353 2354 qcom,din-ports = <3>; 2355 qcom,dout-ports = <0>; 2356 2357 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2358 reset-names = "swr_audio_cgcr"; 2359 2360 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2361 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2362 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2363 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2364 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2365 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2366 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2367 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2368 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2369 2370 #sound-dai-cells = <1>; 2371 #address-cells = <2>; 2372 #size-cells = <0>; 2373 2374 status = "disabled"; 2375 }; 2376 2377 lpass_audiocc: clock-controller@3300000 { 2378 compatible = "qcom,sc7280-lpassaudiocc"; 2379 reg = <0 0x03300000 0 0x30000>, 2380 <0 0x032a9000 0 0x1000>; 2381 clocks = <&rpmhcc RPMH_CXO_CLK>, 2382 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2383 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2384 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2385 #clock-cells = <1>; 2386 #power-domain-cells = <1>; 2387 #reset-cells = <1>; 2388 }; 2389 2390 lpass_va_macro: codec@3370000 { 2391 compatible = "qcom,sc7280-lpass-va-macro"; 2392 reg = <0 0x03370000 0 0x1000>; 2393 2394 pinctrl-names = "default"; 2395 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2396 2397 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2398 clock-names = "mclk"; 2399 2400 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2401 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2402 power-domain-names = "macro", "dcodec"; 2403 2404 #clock-cells = <0>; 2405 #sound-dai-cells = <1>; 2406 2407 status = "disabled"; 2408 }; 2409 2410 lpass_aon: clock-controller@3380000 { 2411 compatible = "qcom,sc7280-lpassaoncc"; 2412 reg = <0 0x03380000 0 0x30000>; 2413 clocks = <&rpmhcc RPMH_CXO_CLK>, 2414 <&rpmhcc RPMH_CXO_CLK_A>, 2415 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2416 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2417 #clock-cells = <1>; 2418 #power-domain-cells = <1>; 2419 status = "reserved"; /* Owned by ADSP firmware */ 2420 }; 2421 2422 lpass_core: clock-controller@3900000 { 2423 compatible = "qcom,sc7280-lpasscorecc"; 2424 reg = <0 0x03900000 0 0x50000>; 2425 clocks = <&rpmhcc RPMH_CXO_CLK>; 2426 clock-names = "bi_tcxo"; 2427 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2428 #clock-cells = <1>; 2429 #power-domain-cells = <1>; 2430 status = "reserved"; /* Owned by ADSP firmware */ 2431 }; 2432 2433 lpass_cpu: audio@3987000 { 2434 compatible = "qcom,sc7280-lpass-cpu"; 2435 2436 reg = <0 0x03987000 0 0x68000>, 2437 <0 0x03b00000 0 0x29000>, 2438 <0 0x03260000 0 0xc000>, 2439 <0 0x03280000 0 0x29000>, 2440 <0 0x03340000 0 0x29000>, 2441 <0 0x0336c000 0 0x3000>; 2442 reg-names = "lpass-hdmiif", 2443 "lpass-lpaif", 2444 "lpass-rxtx-cdc-dma-lpm", 2445 "lpass-rxtx-lpaif", 2446 "lpass-va-lpaif", 2447 "lpass-va-cdc-dma-lpm"; 2448 2449 iommus = <&apps_smmu 0x1820 0>, 2450 <&apps_smmu 0x1821 0>, 2451 <&apps_smmu 0x1832 0>; 2452 2453 power-domains = <&rpmhpd SC7280_LCX>; 2454 power-domain-names = "lcx"; 2455 required-opps = <&rpmhpd_opp_nom>; 2456 2457 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2458 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2459 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2460 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2461 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2462 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2463 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2464 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2465 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2466 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2467 clock-names = "aon_cc_audio_hm_h", 2468 "audio_cc_ext_mclk0", 2469 "core_cc_sysnoc_mport_core", 2470 "core_cc_ext_if0_ibit", 2471 "core_cc_ext_if1_ibit", 2472 "audio_cc_codec_mem", 2473 "audio_cc_codec_mem0", 2474 "audio_cc_codec_mem1", 2475 "audio_cc_codec_mem2", 2476 "aon_cc_va_mem0"; 2477 2478 #sound-dai-cells = <1>; 2479 #address-cells = <1>; 2480 #size-cells = <0>; 2481 2482 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2486 interrupt-names = "lpass-irq-lpaif", 2487 "lpass-irq-hdmi", 2488 "lpass-irq-vaif", 2489 "lpass-irq-rxtxif"; 2490 2491 status = "disabled"; 2492 }; 2493 2494 lpass_hm: clock-controller@3c00000 { 2495 compatible = "qcom,sc7280-lpasshm"; 2496 reg = <0 0x03c00000 0 0x28>; 2497 clocks = <&rpmhcc RPMH_CXO_CLK>; 2498 clock-names = "bi_tcxo"; 2499 #clock-cells = <1>; 2500 #power-domain-cells = <1>; 2501 status = "reserved"; /* Owned by ADSP firmware */ 2502 }; 2503 2504 lpass_ag_noc: interconnect@3c40000 { 2505 reg = <0 0x03c40000 0 0xf080>; 2506 compatible = "qcom,sc7280-lpass-ag-noc"; 2507 #interconnect-cells = <2>; 2508 qcom,bcm-voters = <&apps_bcm_voter>; 2509 }; 2510 2511 lpass_tlmm: pinctrl@33c0000 { 2512 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2513 reg = <0 0x033c0000 0x0 0x20000>, 2514 <0 0x03550000 0x0 0x10000>; 2515 qcom,adsp-bypass-mode; 2516 gpio-controller; 2517 #gpio-cells = <2>; 2518 gpio-ranges = <&lpass_tlmm 0 0 15>; 2519 2520 lpass_dmic01_clk: dmic01-clk-state { 2521 pins = "gpio6"; 2522 function = "dmic1_clk"; 2523 }; 2524 2525 lpass_dmic01_data: dmic01-data-state { 2526 pins = "gpio7"; 2527 function = "dmic1_data"; 2528 }; 2529 2530 lpass_dmic23_clk: dmic23-clk-state { 2531 pins = "gpio8"; 2532 function = "dmic2_clk"; 2533 }; 2534 2535 lpass_dmic23_data: dmic23-data-state { 2536 pins = "gpio9"; 2537 function = "dmic2_data"; 2538 }; 2539 2540 lpass_rx_swr_clk: rx-swr-clk-state { 2541 pins = "gpio3"; 2542 function = "swr_rx_clk"; 2543 }; 2544 2545 lpass_rx_swr_data: rx-swr-data-state { 2546 pins = "gpio4", "gpio5"; 2547 function = "swr_rx_data"; 2548 }; 2549 2550 lpass_tx_swr_clk: tx-swr-clk-state { 2551 pins = "gpio0"; 2552 function = "swr_tx_clk"; 2553 }; 2554 2555 lpass_tx_swr_data: tx-swr-data-state { 2556 pins = "gpio1", "gpio2", "gpio14"; 2557 function = "swr_tx_data"; 2558 }; 2559 }; 2560 2561 gpu: gpu@3d00000 { 2562 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2563 reg = <0 0x03d00000 0 0x40000>, 2564 <0 0x03d9e000 0 0x1000>, 2565 <0 0x03d61000 0 0x800>; 2566 reg-names = "kgsl_3d0_reg_memory", 2567 "cx_mem", 2568 "cx_dbgc"; 2569 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2570 iommus = <&adreno_smmu 0 0x400>, 2571 <&adreno_smmu 1 0x400>; 2572 operating-points-v2 = <&gpu_opp_table>; 2573 qcom,gmu = <&gmu>; 2574 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2575 interconnect-names = "gfx-mem"; 2576 #cooling-cells = <2>; 2577 2578 nvmem-cells = <&gpu_speed_bin>; 2579 nvmem-cell-names = "speed_bin"; 2580 2581 gpu_opp_table: opp-table { 2582 compatible = "operating-points-v2"; 2583 2584 opp-315000000 { 2585 opp-hz = /bits/ 64 <315000000>; 2586 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2587 opp-peak-kBps = <1804000>; 2588 opp-supported-hw = <0x03>; 2589 }; 2590 2591 opp-450000000 { 2592 opp-hz = /bits/ 64 <450000000>; 2593 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2594 opp-peak-kBps = <4068000>; 2595 opp-supported-hw = <0x03>; 2596 }; 2597 2598 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2599 opp-550000000-0 { 2600 opp-hz = /bits/ 64 <550000000>; 2601 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2602 opp-peak-kBps = <8368000>; 2603 opp-supported-hw = <0x01>; 2604 }; 2605 2606 opp-550000000-1 { 2607 opp-hz = /bits/ 64 <550000000>; 2608 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2609 opp-peak-kBps = <6832000>; 2610 opp-supported-hw = <0x02>; 2611 }; 2612 2613 opp-608000000 { 2614 opp-hz = /bits/ 64 <608000000>; 2615 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2616 opp-peak-kBps = <8368000>; 2617 opp-supported-hw = <0x02>; 2618 }; 2619 2620 opp-700000000 { 2621 opp-hz = /bits/ 64 <700000000>; 2622 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2623 opp-peak-kBps = <8532000>; 2624 opp-supported-hw = <0x02>; 2625 }; 2626 2627 opp-812000000 { 2628 opp-hz = /bits/ 64 <812000000>; 2629 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2630 opp-peak-kBps = <8532000>; 2631 opp-supported-hw = <0x02>; 2632 }; 2633 2634 opp-840000000 { 2635 opp-hz = /bits/ 64 <840000000>; 2636 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2637 opp-peak-kBps = <8532000>; 2638 opp-supported-hw = <0x02>; 2639 }; 2640 2641 opp-900000000 { 2642 opp-hz = /bits/ 64 <900000000>; 2643 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2644 opp-peak-kBps = <8532000>; 2645 opp-supported-hw = <0x02>; 2646 }; 2647 }; 2648 }; 2649 2650 gmu: gmu@3d6a000 { 2651 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2652 reg = <0 0x03d6a000 0 0x34000>, 2653 <0 0x3de0000 0 0x10000>, 2654 <0 0x0b290000 0 0x10000>; 2655 reg-names = "gmu", "rscc", "gmu_pdc"; 2656 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2657 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2658 interrupt-names = "hfi", "gmu"; 2659 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2660 <&gpucc GPU_CC_CXO_CLK>, 2661 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2662 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2663 <&gpucc GPU_CC_AHB_CLK>, 2664 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2665 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2666 clock-names = "gmu", 2667 "cxo", 2668 "axi", 2669 "memnoc", 2670 "ahb", 2671 "hub", 2672 "smmu_vote"; 2673 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2674 <&gpucc GPU_CC_GX_GDSC>; 2675 power-domain-names = "cx", 2676 "gx"; 2677 iommus = <&adreno_smmu 5 0x400>; 2678 operating-points-v2 = <&gmu_opp_table>; 2679 2680 gmu_opp_table: opp-table { 2681 compatible = "operating-points-v2"; 2682 2683 opp-200000000 { 2684 opp-hz = /bits/ 64 <200000000>; 2685 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2686 }; 2687 }; 2688 }; 2689 2690 gpucc: clock-controller@3d90000 { 2691 compatible = "qcom,sc7280-gpucc"; 2692 reg = <0 0x03d90000 0 0x9000>; 2693 clocks = <&rpmhcc RPMH_CXO_CLK>, 2694 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2695 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2696 clock-names = "bi_tcxo", 2697 "gcc_gpu_gpll0_clk_src", 2698 "gcc_gpu_gpll0_div_clk_src"; 2699 #clock-cells = <1>; 2700 #reset-cells = <1>; 2701 #power-domain-cells = <1>; 2702 }; 2703 2704 dma@117f000 { 2705 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2706 reg = <0x0 0x0117f000 0x0 0x1000>, 2707 <0x0 0x01112000 0x0 0x6000>; 2708 }; 2709 2710 adreno_smmu: iommu@3da0000 { 2711 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2712 "qcom,smmu-500", "arm,mmu-500"; 2713 reg = <0 0x03da0000 0 0x20000>; 2714 #iommu-cells = <2>; 2715 #global-interrupts = <2>; 2716 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2725 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2726 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2727 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2728 2729 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2730 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2731 <&gpucc GPU_CC_AHB_CLK>, 2732 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2733 <&gpucc GPU_CC_CX_GMU_CLK>, 2734 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2735 <&gpucc GPU_CC_HUB_AON_CLK>; 2736 clock-names = "gcc_gpu_memnoc_gfx_clk", 2737 "gcc_gpu_snoc_dvm_gfx_clk", 2738 "gpu_cc_ahb_clk", 2739 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2740 "gpu_cc_cx_gmu_clk", 2741 "gpu_cc_hub_cx_int_clk", 2742 "gpu_cc_hub_aon_clk"; 2743 2744 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2745 dma-coherent; 2746 }; 2747 2748 remoteproc_mpss: remoteproc@4080000 { 2749 compatible = "qcom,sc7280-mpss-pas"; 2750 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2751 reg-names = "qdsp6", "rmb"; 2752 2753 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2754 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2755 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2756 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2757 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2758 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2759 interrupt-names = "wdog", "fatal", "ready", "handover", 2760 "stop-ack", "shutdown-ack"; 2761 2762 clocks = <&rpmhcc RPMH_CXO_CLK>; 2763 clock-names = "xo"; 2764 2765 power-domains = <&rpmhpd SC7280_CX>, 2766 <&rpmhpd SC7280_MSS>; 2767 power-domain-names = "cx", "mss"; 2768 2769 memory-region = <&mpss_mem>; 2770 2771 qcom,qmp = <&aoss_qmp>; 2772 2773 qcom,smem-states = <&modem_smp2p_out 0>; 2774 qcom,smem-state-names = "stop"; 2775 2776 status = "disabled"; 2777 2778 glink-edge { 2779 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2780 IPCC_MPROC_SIGNAL_GLINK_QMP 2781 IRQ_TYPE_EDGE_RISING>; 2782 mboxes = <&ipcc IPCC_CLIENT_MPSS 2783 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2784 label = "modem"; 2785 qcom,remote-pid = <1>; 2786 }; 2787 }; 2788 2789 stm@6002000 { 2790 compatible = "arm,coresight-stm", "arm,primecell"; 2791 reg = <0 0x06002000 0 0x1000>, 2792 <0 0x16280000 0 0x180000>; 2793 reg-names = "stm-base", "stm-stimulus-base"; 2794 2795 clocks = <&aoss_qmp>; 2796 clock-names = "apb_pclk"; 2797 2798 out-ports { 2799 port { 2800 stm_out: endpoint { 2801 remote-endpoint = <&funnel0_in7>; 2802 }; 2803 }; 2804 }; 2805 }; 2806 2807 funnel@6041000 { 2808 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2809 reg = <0 0x06041000 0 0x1000>; 2810 2811 clocks = <&aoss_qmp>; 2812 clock-names = "apb_pclk"; 2813 2814 out-ports { 2815 port { 2816 funnel0_out: endpoint { 2817 remote-endpoint = <&merge_funnel_in0>; 2818 }; 2819 }; 2820 }; 2821 2822 in-ports { 2823 #address-cells = <1>; 2824 #size-cells = <0>; 2825 2826 port@7 { 2827 reg = <7>; 2828 funnel0_in7: endpoint { 2829 remote-endpoint = <&stm_out>; 2830 }; 2831 }; 2832 }; 2833 }; 2834 2835 funnel@6042000 { 2836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2837 reg = <0 0x06042000 0 0x1000>; 2838 2839 clocks = <&aoss_qmp>; 2840 clock-names = "apb_pclk"; 2841 2842 out-ports { 2843 port { 2844 funnel1_out: endpoint { 2845 remote-endpoint = <&merge_funnel_in1>; 2846 }; 2847 }; 2848 }; 2849 2850 in-ports { 2851 #address-cells = <1>; 2852 #size-cells = <0>; 2853 2854 port@4 { 2855 reg = <4>; 2856 funnel1_in4: endpoint { 2857 remote-endpoint = <&apss_merge_funnel_out>; 2858 }; 2859 }; 2860 }; 2861 }; 2862 2863 funnel@6045000 { 2864 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2865 reg = <0 0x06045000 0 0x1000>; 2866 2867 clocks = <&aoss_qmp>; 2868 clock-names = "apb_pclk"; 2869 2870 out-ports { 2871 port { 2872 merge_funnel_out: endpoint { 2873 remote-endpoint = <&swao_funnel_in>; 2874 }; 2875 }; 2876 }; 2877 2878 in-ports { 2879 #address-cells = <1>; 2880 #size-cells = <0>; 2881 2882 port@0 { 2883 reg = <0>; 2884 merge_funnel_in0: endpoint { 2885 remote-endpoint = <&funnel0_out>; 2886 }; 2887 }; 2888 2889 port@1 { 2890 reg = <1>; 2891 merge_funnel_in1: endpoint { 2892 remote-endpoint = <&funnel1_out>; 2893 }; 2894 }; 2895 }; 2896 }; 2897 2898 replicator@6046000 { 2899 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2900 reg = <0 0x06046000 0 0x1000>; 2901 2902 clocks = <&aoss_qmp>; 2903 clock-names = "apb_pclk"; 2904 2905 out-ports { 2906 port { 2907 replicator_out: endpoint { 2908 remote-endpoint = <&etr_in>; 2909 }; 2910 }; 2911 }; 2912 2913 in-ports { 2914 port { 2915 replicator_in: endpoint { 2916 remote-endpoint = <&swao_replicator_out>; 2917 }; 2918 }; 2919 }; 2920 }; 2921 2922 etr@6048000 { 2923 compatible = "arm,coresight-tmc", "arm,primecell"; 2924 reg = <0 0x06048000 0 0x1000>; 2925 iommus = <&apps_smmu 0x04c0 0>; 2926 2927 clocks = <&aoss_qmp>; 2928 clock-names = "apb_pclk"; 2929 arm,scatter-gather; 2930 2931 in-ports { 2932 port { 2933 etr_in: endpoint { 2934 remote-endpoint = <&replicator_out>; 2935 }; 2936 }; 2937 }; 2938 }; 2939 2940 funnel@6b04000 { 2941 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2942 reg = <0 0x06b04000 0 0x1000>; 2943 2944 clocks = <&aoss_qmp>; 2945 clock-names = "apb_pclk"; 2946 2947 out-ports { 2948 port { 2949 swao_funnel_out: endpoint { 2950 remote-endpoint = <&etf_in>; 2951 }; 2952 }; 2953 }; 2954 2955 in-ports { 2956 #address-cells = <1>; 2957 #size-cells = <0>; 2958 2959 port@7 { 2960 reg = <7>; 2961 swao_funnel_in: endpoint { 2962 remote-endpoint = <&merge_funnel_out>; 2963 }; 2964 }; 2965 }; 2966 }; 2967 2968 etf@6b05000 { 2969 compatible = "arm,coresight-tmc", "arm,primecell"; 2970 reg = <0 0x06b05000 0 0x1000>; 2971 2972 clocks = <&aoss_qmp>; 2973 clock-names = "apb_pclk"; 2974 2975 out-ports { 2976 port { 2977 etf_out: endpoint { 2978 remote-endpoint = <&swao_replicator_in>; 2979 }; 2980 }; 2981 }; 2982 2983 in-ports { 2984 port { 2985 etf_in: endpoint { 2986 remote-endpoint = <&swao_funnel_out>; 2987 }; 2988 }; 2989 }; 2990 }; 2991 2992 replicator@6b06000 { 2993 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2994 reg = <0 0x06b06000 0 0x1000>; 2995 2996 clocks = <&aoss_qmp>; 2997 clock-names = "apb_pclk"; 2998 qcom,replicator-loses-context; 2999 3000 out-ports { 3001 port { 3002 swao_replicator_out: endpoint { 3003 remote-endpoint = <&replicator_in>; 3004 }; 3005 }; 3006 }; 3007 3008 in-ports { 3009 port { 3010 swao_replicator_in: endpoint { 3011 remote-endpoint = <&etf_out>; 3012 }; 3013 }; 3014 }; 3015 }; 3016 3017 etm@7040000 { 3018 compatible = "arm,coresight-etm4x", "arm,primecell"; 3019 reg = <0 0x07040000 0 0x1000>; 3020 3021 cpu = <&CPU0>; 3022 3023 clocks = <&aoss_qmp>; 3024 clock-names = "apb_pclk"; 3025 arm,coresight-loses-context-with-cpu; 3026 qcom,skip-power-up; 3027 3028 out-ports { 3029 port { 3030 etm0_out: endpoint { 3031 remote-endpoint = <&apss_funnel_in0>; 3032 }; 3033 }; 3034 }; 3035 }; 3036 3037 etm@7140000 { 3038 compatible = "arm,coresight-etm4x", "arm,primecell"; 3039 reg = <0 0x07140000 0 0x1000>; 3040 3041 cpu = <&CPU1>; 3042 3043 clocks = <&aoss_qmp>; 3044 clock-names = "apb_pclk"; 3045 arm,coresight-loses-context-with-cpu; 3046 qcom,skip-power-up; 3047 3048 out-ports { 3049 port { 3050 etm1_out: endpoint { 3051 remote-endpoint = <&apss_funnel_in1>; 3052 }; 3053 }; 3054 }; 3055 }; 3056 3057 etm@7240000 { 3058 compatible = "arm,coresight-etm4x", "arm,primecell"; 3059 reg = <0 0x07240000 0 0x1000>; 3060 3061 cpu = <&CPU2>; 3062 3063 clocks = <&aoss_qmp>; 3064 clock-names = "apb_pclk"; 3065 arm,coresight-loses-context-with-cpu; 3066 qcom,skip-power-up; 3067 3068 out-ports { 3069 port { 3070 etm2_out: endpoint { 3071 remote-endpoint = <&apss_funnel_in2>; 3072 }; 3073 }; 3074 }; 3075 }; 3076 3077 etm@7340000 { 3078 compatible = "arm,coresight-etm4x", "arm,primecell"; 3079 reg = <0 0x07340000 0 0x1000>; 3080 3081 cpu = <&CPU3>; 3082 3083 clocks = <&aoss_qmp>; 3084 clock-names = "apb_pclk"; 3085 arm,coresight-loses-context-with-cpu; 3086 qcom,skip-power-up; 3087 3088 out-ports { 3089 port { 3090 etm3_out: endpoint { 3091 remote-endpoint = <&apss_funnel_in3>; 3092 }; 3093 }; 3094 }; 3095 }; 3096 3097 etm@7440000 { 3098 compatible = "arm,coresight-etm4x", "arm,primecell"; 3099 reg = <0 0x07440000 0 0x1000>; 3100 3101 cpu = <&CPU4>; 3102 3103 clocks = <&aoss_qmp>; 3104 clock-names = "apb_pclk"; 3105 arm,coresight-loses-context-with-cpu; 3106 qcom,skip-power-up; 3107 3108 out-ports { 3109 port { 3110 etm4_out: endpoint { 3111 remote-endpoint = <&apss_funnel_in4>; 3112 }; 3113 }; 3114 }; 3115 }; 3116 3117 etm@7540000 { 3118 compatible = "arm,coresight-etm4x", "arm,primecell"; 3119 reg = <0 0x07540000 0 0x1000>; 3120 3121 cpu = <&CPU5>; 3122 3123 clocks = <&aoss_qmp>; 3124 clock-names = "apb_pclk"; 3125 arm,coresight-loses-context-with-cpu; 3126 qcom,skip-power-up; 3127 3128 out-ports { 3129 port { 3130 etm5_out: endpoint { 3131 remote-endpoint = <&apss_funnel_in5>; 3132 }; 3133 }; 3134 }; 3135 }; 3136 3137 etm@7640000 { 3138 compatible = "arm,coresight-etm4x", "arm,primecell"; 3139 reg = <0 0x07640000 0 0x1000>; 3140 3141 cpu = <&CPU6>; 3142 3143 clocks = <&aoss_qmp>; 3144 clock-names = "apb_pclk"; 3145 arm,coresight-loses-context-with-cpu; 3146 qcom,skip-power-up; 3147 3148 out-ports { 3149 port { 3150 etm6_out: endpoint { 3151 remote-endpoint = <&apss_funnel_in6>; 3152 }; 3153 }; 3154 }; 3155 }; 3156 3157 etm@7740000 { 3158 compatible = "arm,coresight-etm4x", "arm,primecell"; 3159 reg = <0 0x07740000 0 0x1000>; 3160 3161 cpu = <&CPU7>; 3162 3163 clocks = <&aoss_qmp>; 3164 clock-names = "apb_pclk"; 3165 arm,coresight-loses-context-with-cpu; 3166 qcom,skip-power-up; 3167 3168 out-ports { 3169 port { 3170 etm7_out: endpoint { 3171 remote-endpoint = <&apss_funnel_in7>; 3172 }; 3173 }; 3174 }; 3175 }; 3176 3177 funnel@7800000 { /* APSS Funnel */ 3178 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3179 reg = <0 0x07800000 0 0x1000>; 3180 3181 clocks = <&aoss_qmp>; 3182 clock-names = "apb_pclk"; 3183 3184 out-ports { 3185 port { 3186 apss_funnel_out: endpoint { 3187 remote-endpoint = <&apss_merge_funnel_in>; 3188 }; 3189 }; 3190 }; 3191 3192 in-ports { 3193 #address-cells = <1>; 3194 #size-cells = <0>; 3195 3196 port@0 { 3197 reg = <0>; 3198 apss_funnel_in0: endpoint { 3199 remote-endpoint = <&etm0_out>; 3200 }; 3201 }; 3202 3203 port@1 { 3204 reg = <1>; 3205 apss_funnel_in1: endpoint { 3206 remote-endpoint = <&etm1_out>; 3207 }; 3208 }; 3209 3210 port@2 { 3211 reg = <2>; 3212 apss_funnel_in2: endpoint { 3213 remote-endpoint = <&etm2_out>; 3214 }; 3215 }; 3216 3217 port@3 { 3218 reg = <3>; 3219 apss_funnel_in3: endpoint { 3220 remote-endpoint = <&etm3_out>; 3221 }; 3222 }; 3223 3224 port@4 { 3225 reg = <4>; 3226 apss_funnel_in4: endpoint { 3227 remote-endpoint = <&etm4_out>; 3228 }; 3229 }; 3230 3231 port@5 { 3232 reg = <5>; 3233 apss_funnel_in5: endpoint { 3234 remote-endpoint = <&etm5_out>; 3235 }; 3236 }; 3237 3238 port@6 { 3239 reg = <6>; 3240 apss_funnel_in6: endpoint { 3241 remote-endpoint = <&etm6_out>; 3242 }; 3243 }; 3244 3245 port@7 { 3246 reg = <7>; 3247 apss_funnel_in7: endpoint { 3248 remote-endpoint = <&etm7_out>; 3249 }; 3250 }; 3251 }; 3252 }; 3253 3254 funnel@7810000 { 3255 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3256 reg = <0 0x07810000 0 0x1000>; 3257 3258 clocks = <&aoss_qmp>; 3259 clock-names = "apb_pclk"; 3260 3261 out-ports { 3262 port { 3263 apss_merge_funnel_out: endpoint { 3264 remote-endpoint = <&funnel1_in4>; 3265 }; 3266 }; 3267 }; 3268 3269 in-ports { 3270 port { 3271 apss_merge_funnel_in: endpoint { 3272 remote-endpoint = <&apss_funnel_out>; 3273 }; 3274 }; 3275 }; 3276 }; 3277 3278 sdhc_2: mmc@8804000 { 3279 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3280 pinctrl-names = "default", "sleep"; 3281 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3282 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3283 status = "disabled"; 3284 3285 reg = <0 0x08804000 0 0x1000>; 3286 3287 iommus = <&apps_smmu 0x100 0x0>; 3288 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3290 interrupt-names = "hc_irq", "pwr_irq"; 3291 3292 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3293 <&gcc GCC_SDCC2_APPS_CLK>, 3294 <&rpmhcc RPMH_CXO_CLK>; 3295 clock-names = "iface", "core", "xo"; 3296 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3297 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3298 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3299 power-domains = <&rpmhpd SC7280_CX>; 3300 operating-points-v2 = <&sdhc2_opp_table>; 3301 3302 bus-width = <4>; 3303 dma-coherent; 3304 3305 qcom,dll-config = <0x0007642c>; 3306 3307 resets = <&gcc GCC_SDCC2_BCR>; 3308 3309 sdhc2_opp_table: opp-table { 3310 compatible = "operating-points-v2"; 3311 3312 opp-100000000 { 3313 opp-hz = /bits/ 64 <100000000>; 3314 required-opps = <&rpmhpd_opp_low_svs>; 3315 opp-peak-kBps = <1800000 400000>; 3316 opp-avg-kBps = <100000 0>; 3317 }; 3318 3319 opp-202000000 { 3320 opp-hz = /bits/ 64 <202000000>; 3321 required-opps = <&rpmhpd_opp_nom>; 3322 opp-peak-kBps = <5400000 1600000>; 3323 opp-avg-kBps = <200000 0>; 3324 }; 3325 }; 3326 }; 3327 3328 usb_1_hsphy: phy@88e3000 { 3329 compatible = "qcom,sc7280-usb-hs-phy", 3330 "qcom,usb-snps-hs-7nm-phy"; 3331 reg = <0 0x088e3000 0 0x400>; 3332 status = "disabled"; 3333 #phy-cells = <0>; 3334 3335 clocks = <&rpmhcc RPMH_CXO_CLK>; 3336 clock-names = "ref"; 3337 3338 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3339 }; 3340 3341 usb_2_hsphy: phy@88e4000 { 3342 compatible = "qcom,sc7280-usb-hs-phy", 3343 "qcom,usb-snps-hs-7nm-phy"; 3344 reg = <0 0x088e4000 0 0x400>; 3345 status = "disabled"; 3346 #phy-cells = <0>; 3347 3348 clocks = <&rpmhcc RPMH_CXO_CLK>; 3349 clock-names = "ref"; 3350 3351 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3352 }; 3353 3354 usb_1_qmpphy: phy-wrapper@88e9000 { 3355 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3356 "qcom,sm8250-qmp-usb3-dp-phy"; 3357 reg = <0 0x088e9000 0 0x200>, 3358 <0 0x088e8000 0 0x40>, 3359 <0 0x088ea000 0 0x200>; 3360 status = "disabled"; 3361 #address-cells = <2>; 3362 #size-cells = <2>; 3363 ranges; 3364 3365 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3366 <&rpmhcc RPMH_CXO_CLK>, 3367 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3368 clock-names = "aux", "ref_clk_src", "com_aux"; 3369 3370 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3371 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3372 reset-names = "phy", "common"; 3373 3374 usb_1_ssphy: usb3-phy@88e9200 { 3375 reg = <0 0x088e9200 0 0x200>, 3376 <0 0x088e9400 0 0x200>, 3377 <0 0x088e9c00 0 0x400>, 3378 <0 0x088e9600 0 0x200>, 3379 <0 0x088e9800 0 0x200>, 3380 <0 0x088e9a00 0 0x100>; 3381 #clock-cells = <0>; 3382 #phy-cells = <0>; 3383 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3384 clock-names = "pipe0"; 3385 clock-output-names = "usb3_phy_pipe_clk_src"; 3386 }; 3387 3388 dp_phy: dp-phy@88ea200 { 3389 reg = <0 0x088ea200 0 0x200>, 3390 <0 0x088ea400 0 0x200>, 3391 <0 0x088eaa00 0 0x200>, 3392 <0 0x088ea600 0 0x200>, 3393 <0 0x088ea800 0 0x200>; 3394 #phy-cells = <0>; 3395 #clock-cells = <1>; 3396 }; 3397 }; 3398 3399 usb_2: usb@8cf8800 { 3400 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3401 reg = <0 0x08cf8800 0 0x400>; 3402 status = "disabled"; 3403 #address-cells = <2>; 3404 #size-cells = <2>; 3405 ranges; 3406 dma-ranges; 3407 3408 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3409 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3410 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3411 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3412 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3413 clock-names = "cfg_noc", 3414 "core", 3415 "iface", 3416 "sleep", 3417 "mock_utmi"; 3418 3419 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3420 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3421 assigned-clock-rates = <19200000>, <200000000>; 3422 3423 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3424 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3425 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3426 interrupt-names = "hs_phy_irq", 3427 "dp_hs_phy_irq", 3428 "dm_hs_phy_irq"; 3429 3430 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3431 required-opps = <&rpmhpd_opp_nom>; 3432 3433 resets = <&gcc GCC_USB30_SEC_BCR>; 3434 3435 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3436 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3437 interconnect-names = "usb-ddr", "apps-usb"; 3438 3439 usb_2_dwc3: usb@8c00000 { 3440 compatible = "snps,dwc3"; 3441 reg = <0 0x08c00000 0 0xe000>; 3442 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3443 iommus = <&apps_smmu 0xa0 0x0>; 3444 snps,dis_u2_susphy_quirk; 3445 snps,dis_enblslpm_quirk; 3446 phys = <&usb_2_hsphy>; 3447 phy-names = "usb2-phy"; 3448 maximum-speed = "high-speed"; 3449 usb-role-switch; 3450 3451 port { 3452 usb2_role_switch: endpoint { 3453 remote-endpoint = <&eud_ep>; 3454 }; 3455 }; 3456 }; 3457 }; 3458 3459 qspi: spi@88dc000 { 3460 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3461 reg = <0 0x088dc000 0 0x1000>; 3462 iommus = <&apps_smmu 0x20 0x0>; 3463 #address-cells = <1>; 3464 #size-cells = <0>; 3465 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3466 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3467 <&gcc GCC_QSPI_CORE_CLK>; 3468 clock-names = "iface", "core"; 3469 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3470 &cnoc2 SLAVE_QSPI_0 0>; 3471 interconnect-names = "qspi-config"; 3472 power-domains = <&rpmhpd SC7280_CX>; 3473 operating-points-v2 = <&qspi_opp_table>; 3474 status = "disabled"; 3475 }; 3476 3477 remoteproc_wpss: remoteproc@8a00000 { 3478 compatible = "qcom,sc7280-wpss-pil"; 3479 reg = <0 0x08a00000 0 0x10000>; 3480 3481 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3482 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3483 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3484 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3485 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3486 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3487 interrupt-names = "wdog", "fatal", "ready", "handover", 3488 "stop-ack", "shutdown-ack"; 3489 3490 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3491 <&gcc GCC_WPSS_AHB_CLK>, 3492 <&gcc GCC_WPSS_RSCP_CLK>, 3493 <&rpmhcc RPMH_CXO_CLK>; 3494 clock-names = "ahb_bdg", "ahb", 3495 "rscp", "xo"; 3496 3497 power-domains = <&rpmhpd SC7280_CX>, 3498 <&rpmhpd SC7280_MX>; 3499 power-domain-names = "cx", "mx"; 3500 3501 memory-region = <&wpss_mem>; 3502 3503 qcom,qmp = <&aoss_qmp>; 3504 3505 qcom,smem-states = <&wpss_smp2p_out 0>; 3506 qcom,smem-state-names = "stop"; 3507 3508 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3509 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3510 reset-names = "restart", "pdc_sync"; 3511 3512 qcom,halt-regs = <&tcsr_1 0x17000>; 3513 3514 status = "disabled"; 3515 3516 glink-edge { 3517 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3518 IPCC_MPROC_SIGNAL_GLINK_QMP 3519 IRQ_TYPE_EDGE_RISING>; 3520 mboxes = <&ipcc IPCC_CLIENT_WPSS 3521 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3522 3523 label = "wpss"; 3524 qcom,remote-pid = <13>; 3525 }; 3526 }; 3527 3528 pmu@9091000 { 3529 compatible = "qcom,sc7280-llcc-bwmon"; 3530 reg = <0 0x09091000 0 0x1000>; 3531 3532 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3533 3534 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3535 3536 operating-points-v2 = <&llcc_bwmon_opp_table>; 3537 3538 llcc_bwmon_opp_table: opp-table { 3539 compatible = "operating-points-v2"; 3540 3541 opp-0 { 3542 opp-peak-kBps = <800000>; 3543 }; 3544 opp-1 { 3545 opp-peak-kBps = <1804000>; 3546 }; 3547 opp-2 { 3548 opp-peak-kBps = <2188000>; 3549 }; 3550 opp-3 { 3551 opp-peak-kBps = <3072000>; 3552 }; 3553 opp-4 { 3554 opp-peak-kBps = <4068000>; 3555 }; 3556 opp-5 { 3557 opp-peak-kBps = <6220000>; 3558 }; 3559 opp-6 { 3560 opp-peak-kBps = <6832000>; 3561 }; 3562 opp-7 { 3563 opp-peak-kBps = <8532000>; 3564 }; 3565 }; 3566 }; 3567 3568 pmu@90b6400 { 3569 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3570 reg = <0 0x090b6400 0 0x600>; 3571 3572 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3573 3574 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3575 operating-points-v2 = <&cpu_bwmon_opp_table>; 3576 3577 cpu_bwmon_opp_table: opp-table { 3578 compatible = "operating-points-v2"; 3579 3580 opp-0 { 3581 opp-peak-kBps = <2400000>; 3582 }; 3583 opp-1 { 3584 opp-peak-kBps = <4800000>; 3585 }; 3586 opp-2 { 3587 opp-peak-kBps = <7456000>; 3588 }; 3589 opp-3 { 3590 opp-peak-kBps = <9600000>; 3591 }; 3592 opp-4 { 3593 opp-peak-kBps = <12896000>; 3594 }; 3595 opp-5 { 3596 opp-peak-kBps = <14928000>; 3597 }; 3598 opp-6 { 3599 opp-peak-kBps = <17056000>; 3600 }; 3601 }; 3602 }; 3603 3604 dc_noc: interconnect@90e0000 { 3605 reg = <0 0x090e0000 0 0x5080>; 3606 compatible = "qcom,sc7280-dc-noc"; 3607 #interconnect-cells = <2>; 3608 qcom,bcm-voters = <&apps_bcm_voter>; 3609 }; 3610 3611 gem_noc: interconnect@9100000 { 3612 reg = <0 0x09100000 0 0xe2200>; 3613 compatible = "qcom,sc7280-gem-noc"; 3614 #interconnect-cells = <2>; 3615 qcom,bcm-voters = <&apps_bcm_voter>; 3616 }; 3617 3618 system-cache-controller@9200000 { 3619 compatible = "qcom,sc7280-llcc"; 3620 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3621 <0 0x09600000 0 0x58000>; 3622 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3623 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3624 }; 3625 3626 eud: eud@88e0000 { 3627 compatible = "qcom,sc7280-eud", "qcom,eud"; 3628 reg = <0 0x88e0000 0 0x2000>, 3629 <0 0x88e2000 0 0x1000>; 3630 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3631 3632 status = "disabled"; 3633 3634 ports { 3635 #address-cells = <1>; 3636 #size-cells = <0>; 3637 3638 port@0 { 3639 reg = <0>; 3640 eud_ep: endpoint { 3641 remote-endpoint = <&usb2_role_switch>; 3642 }; 3643 }; 3644 }; 3645 }; 3646 3647 nsp_noc: interconnect@a0c0000 { 3648 reg = <0 0x0a0c0000 0 0x10000>; 3649 compatible = "qcom,sc7280-nsp-noc"; 3650 #interconnect-cells = <2>; 3651 qcom,bcm-voters = <&apps_bcm_voter>; 3652 }; 3653 3654 usb_1: usb@a6f8800 { 3655 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3656 reg = <0 0x0a6f8800 0 0x400>; 3657 status = "disabled"; 3658 #address-cells = <2>; 3659 #size-cells = <2>; 3660 ranges; 3661 dma-ranges; 3662 3663 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3664 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3665 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3666 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3667 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3668 clock-names = "cfg_noc", 3669 "core", 3670 "iface", 3671 "sleep", 3672 "mock_utmi"; 3673 3674 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3675 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3676 assigned-clock-rates = <19200000>, <200000000>; 3677 3678 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3679 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3680 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3681 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3682 interrupt-names = "hs_phy_irq", 3683 "dp_hs_phy_irq", 3684 "dm_hs_phy_irq", 3685 "ss_phy_irq"; 3686 3687 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3688 required-opps = <&rpmhpd_opp_nom>; 3689 3690 resets = <&gcc GCC_USB30_PRIM_BCR>; 3691 3692 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3694 interconnect-names = "usb-ddr", "apps-usb"; 3695 3696 wakeup-source; 3697 3698 usb_1_dwc3: usb@a600000 { 3699 compatible = "snps,dwc3"; 3700 reg = <0 0x0a600000 0 0xe000>; 3701 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3702 iommus = <&apps_smmu 0xe0 0x0>; 3703 snps,dis_u2_susphy_quirk; 3704 snps,dis_enblslpm_quirk; 3705 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3706 phy-names = "usb2-phy", "usb3-phy"; 3707 maximum-speed = "super-speed"; 3708 }; 3709 }; 3710 3711 venus: video-codec@aa00000 { 3712 compatible = "qcom,sc7280-venus"; 3713 reg = <0 0x0aa00000 0 0xd0600>; 3714 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3715 3716 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3717 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3718 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3719 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3720 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3721 clock-names = "core", "bus", "iface", 3722 "vcodec_core", "vcodec_bus"; 3723 3724 power-domains = <&videocc MVSC_GDSC>, 3725 <&videocc MVS0_GDSC>, 3726 <&rpmhpd SC7280_CX>; 3727 power-domain-names = "venus", "vcodec0", "cx"; 3728 operating-points-v2 = <&venus_opp_table>; 3729 3730 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3731 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3732 interconnect-names = "cpu-cfg", "video-mem"; 3733 3734 iommus = <&apps_smmu 0x2180 0x20>, 3735 <&apps_smmu 0x2184 0x20>; 3736 memory-region = <&video_mem>; 3737 3738 video-decoder { 3739 compatible = "venus-decoder"; 3740 }; 3741 3742 video-encoder { 3743 compatible = "venus-encoder"; 3744 }; 3745 3746 video-firmware { 3747 iommus = <&apps_smmu 0x21a2 0x0>; 3748 }; 3749 3750 venus_opp_table: opp-table { 3751 compatible = "operating-points-v2"; 3752 3753 opp-133330000 { 3754 opp-hz = /bits/ 64 <133330000>; 3755 required-opps = <&rpmhpd_opp_low_svs>; 3756 }; 3757 3758 opp-240000000 { 3759 opp-hz = /bits/ 64 <240000000>; 3760 required-opps = <&rpmhpd_opp_svs>; 3761 }; 3762 3763 opp-335000000 { 3764 opp-hz = /bits/ 64 <335000000>; 3765 required-opps = <&rpmhpd_opp_svs_l1>; 3766 }; 3767 3768 opp-424000000 { 3769 opp-hz = /bits/ 64 <424000000>; 3770 required-opps = <&rpmhpd_opp_nom>; 3771 }; 3772 3773 opp-460000048 { 3774 opp-hz = /bits/ 64 <460000048>; 3775 required-opps = <&rpmhpd_opp_turbo>; 3776 }; 3777 }; 3778 }; 3779 3780 videocc: clock-controller@aaf0000 { 3781 compatible = "qcom,sc7280-videocc"; 3782 reg = <0 0x0aaf0000 0 0x10000>; 3783 clocks = <&rpmhcc RPMH_CXO_CLK>, 3784 <&rpmhcc RPMH_CXO_CLK_A>; 3785 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3786 #clock-cells = <1>; 3787 #reset-cells = <1>; 3788 #power-domain-cells = <1>; 3789 }; 3790 3791 camcc: clock-controller@ad00000 { 3792 compatible = "qcom,sc7280-camcc"; 3793 reg = <0 0x0ad00000 0 0x10000>; 3794 clocks = <&rpmhcc RPMH_CXO_CLK>, 3795 <&rpmhcc RPMH_CXO_CLK_A>, 3796 <&sleep_clk>; 3797 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3798 #clock-cells = <1>; 3799 #reset-cells = <1>; 3800 #power-domain-cells = <1>; 3801 }; 3802 3803 dispcc: clock-controller@af00000 { 3804 compatible = "qcom,sc7280-dispcc"; 3805 reg = <0 0x0af00000 0 0x20000>; 3806 clocks = <&rpmhcc RPMH_CXO_CLK>, 3807 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3808 <&mdss_dsi_phy 0>, 3809 <&mdss_dsi_phy 1>, 3810 <&dp_phy 0>, 3811 <&dp_phy 1>, 3812 <&mdss_edp_phy 0>, 3813 <&mdss_edp_phy 1>; 3814 clock-names = "bi_tcxo", 3815 "gcc_disp_gpll0_clk", 3816 "dsi0_phy_pll_out_byteclk", 3817 "dsi0_phy_pll_out_dsiclk", 3818 "dp_phy_pll_link_clk", 3819 "dp_phy_pll_vco_div_clk", 3820 "edp_phy_pll_link_clk", 3821 "edp_phy_pll_vco_div_clk"; 3822 #clock-cells = <1>; 3823 #reset-cells = <1>; 3824 #power-domain-cells = <1>; 3825 }; 3826 3827 mdss: display-subsystem@ae00000 { 3828 compatible = "qcom,sc7280-mdss"; 3829 reg = <0 0x0ae00000 0 0x1000>; 3830 reg-names = "mdss"; 3831 3832 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3833 3834 clocks = <&gcc GCC_DISP_AHB_CLK>, 3835 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3836 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3837 clock-names = "iface", 3838 "ahb", 3839 "core"; 3840 3841 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3842 interrupt-controller; 3843 #interrupt-cells = <1>; 3844 3845 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3846 interconnect-names = "mdp0-mem"; 3847 3848 iommus = <&apps_smmu 0x900 0x402>; 3849 3850 #address-cells = <2>; 3851 #size-cells = <2>; 3852 ranges; 3853 3854 status = "disabled"; 3855 3856 mdss_mdp: display-controller@ae01000 { 3857 compatible = "qcom,sc7280-dpu"; 3858 reg = <0 0x0ae01000 0 0x8f030>, 3859 <0 0x0aeb0000 0 0x2008>; 3860 reg-names = "mdp", "vbif"; 3861 3862 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3863 <&gcc GCC_DISP_SF_AXI_CLK>, 3864 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3865 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3866 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3867 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3868 clock-names = "bus", 3869 "nrt_bus", 3870 "iface", 3871 "lut", 3872 "core", 3873 "vsync"; 3874 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3875 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3876 assigned-clock-rates = <19200000>, 3877 <19200000>; 3878 operating-points-v2 = <&mdp_opp_table>; 3879 power-domains = <&rpmhpd SC7280_CX>; 3880 3881 interrupt-parent = <&mdss>; 3882 interrupts = <0>; 3883 3884 ports { 3885 #address-cells = <1>; 3886 #size-cells = <0>; 3887 3888 port@0 { 3889 reg = <0>; 3890 dpu_intf1_out: endpoint { 3891 remote-endpoint = <&mdss_dsi0_in>; 3892 }; 3893 }; 3894 3895 port@1 { 3896 reg = <1>; 3897 dpu_intf5_out: endpoint { 3898 remote-endpoint = <&edp_in>; 3899 }; 3900 }; 3901 3902 port@2 { 3903 reg = <2>; 3904 dpu_intf0_out: endpoint { 3905 remote-endpoint = <&dp_in>; 3906 }; 3907 }; 3908 }; 3909 3910 mdp_opp_table: opp-table { 3911 compatible = "operating-points-v2"; 3912 3913 opp-200000000 { 3914 opp-hz = /bits/ 64 <200000000>; 3915 required-opps = <&rpmhpd_opp_low_svs>; 3916 }; 3917 3918 opp-300000000 { 3919 opp-hz = /bits/ 64 <300000000>; 3920 required-opps = <&rpmhpd_opp_svs>; 3921 }; 3922 3923 opp-380000000 { 3924 opp-hz = /bits/ 64 <380000000>; 3925 required-opps = <&rpmhpd_opp_svs_l1>; 3926 }; 3927 3928 opp-506666667 { 3929 opp-hz = /bits/ 64 <506666667>; 3930 required-opps = <&rpmhpd_opp_nom>; 3931 }; 3932 }; 3933 }; 3934 3935 mdss_dsi: dsi@ae94000 { 3936 compatible = "qcom,sc7280-dsi-ctrl", 3937 "qcom,mdss-dsi-ctrl"; 3938 reg = <0 0x0ae94000 0 0x400>; 3939 reg-names = "dsi_ctrl"; 3940 3941 interrupt-parent = <&mdss>; 3942 interrupts = <4>; 3943 3944 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3945 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3946 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3947 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3948 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3949 <&gcc GCC_DISP_HF_AXI_CLK>; 3950 clock-names = "byte", 3951 "byte_intf", 3952 "pixel", 3953 "core", 3954 "iface", 3955 "bus"; 3956 3957 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3958 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3959 3960 operating-points-v2 = <&dsi_opp_table>; 3961 power-domains = <&rpmhpd SC7280_CX>; 3962 3963 phys = <&mdss_dsi_phy>; 3964 3965 #address-cells = <1>; 3966 #size-cells = <0>; 3967 3968 status = "disabled"; 3969 3970 ports { 3971 #address-cells = <1>; 3972 #size-cells = <0>; 3973 3974 port@0 { 3975 reg = <0>; 3976 mdss_dsi0_in: endpoint { 3977 remote-endpoint = <&dpu_intf1_out>; 3978 }; 3979 }; 3980 3981 port@1 { 3982 reg = <1>; 3983 mdss_dsi0_out: endpoint { 3984 }; 3985 }; 3986 }; 3987 3988 dsi_opp_table: opp-table { 3989 compatible = "operating-points-v2"; 3990 3991 opp-187500000 { 3992 opp-hz = /bits/ 64 <187500000>; 3993 required-opps = <&rpmhpd_opp_low_svs>; 3994 }; 3995 3996 opp-300000000 { 3997 opp-hz = /bits/ 64 <300000000>; 3998 required-opps = <&rpmhpd_opp_svs>; 3999 }; 4000 4001 opp-358000000 { 4002 opp-hz = /bits/ 64 <358000000>; 4003 required-opps = <&rpmhpd_opp_svs_l1>; 4004 }; 4005 }; 4006 }; 4007 4008 mdss_dsi_phy: phy@ae94400 { 4009 compatible = "qcom,sc7280-dsi-phy-7nm"; 4010 reg = <0 0x0ae94400 0 0x200>, 4011 <0 0x0ae94600 0 0x280>, 4012 <0 0x0ae94900 0 0x280>; 4013 reg-names = "dsi_phy", 4014 "dsi_phy_lane", 4015 "dsi_pll"; 4016 4017 #clock-cells = <1>; 4018 #phy-cells = <0>; 4019 4020 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4021 <&rpmhcc RPMH_CXO_CLK>; 4022 clock-names = "iface", "ref"; 4023 4024 status = "disabled"; 4025 }; 4026 4027 mdss_edp: edp@aea0000 { 4028 compatible = "qcom,sc7280-edp"; 4029 pinctrl-names = "default"; 4030 pinctrl-0 = <&edp_hot_plug_det>; 4031 4032 reg = <0 0x0aea0000 0 0x200>, 4033 <0 0x0aea0200 0 0x200>, 4034 <0 0x0aea0400 0 0xc00>, 4035 <0 0x0aea1000 0 0x400>; 4036 4037 interrupt-parent = <&mdss>; 4038 interrupts = <14>; 4039 4040 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4041 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4042 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4043 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4044 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4045 clock-names = "core_iface", 4046 "core_aux", 4047 "ctrl_link", 4048 "ctrl_link_iface", 4049 "stream_pixel"; 4050 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4051 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4052 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4053 4054 phys = <&mdss_edp_phy>; 4055 phy-names = "dp"; 4056 4057 operating-points-v2 = <&edp_opp_table>; 4058 power-domains = <&rpmhpd SC7280_CX>; 4059 4060 status = "disabled"; 4061 4062 ports { 4063 #address-cells = <1>; 4064 #size-cells = <0>; 4065 4066 port@0 { 4067 reg = <0>; 4068 edp_in: endpoint { 4069 remote-endpoint = <&dpu_intf5_out>; 4070 }; 4071 }; 4072 4073 port@1 { 4074 reg = <1>; 4075 mdss_edp_out: endpoint { }; 4076 }; 4077 }; 4078 4079 edp_opp_table: opp-table { 4080 compatible = "operating-points-v2"; 4081 4082 opp-160000000 { 4083 opp-hz = /bits/ 64 <160000000>; 4084 required-opps = <&rpmhpd_opp_low_svs>; 4085 }; 4086 4087 opp-270000000 { 4088 opp-hz = /bits/ 64 <270000000>; 4089 required-opps = <&rpmhpd_opp_svs>; 4090 }; 4091 4092 opp-540000000 { 4093 opp-hz = /bits/ 64 <540000000>; 4094 required-opps = <&rpmhpd_opp_nom>; 4095 }; 4096 4097 opp-810000000 { 4098 opp-hz = /bits/ 64 <810000000>; 4099 required-opps = <&rpmhpd_opp_nom>; 4100 }; 4101 }; 4102 }; 4103 4104 mdss_edp_phy: phy@aec2a00 { 4105 compatible = "qcom,sc7280-edp-phy"; 4106 4107 reg = <0 0x0aec2a00 0 0x19c>, 4108 <0 0x0aec2200 0 0xa0>, 4109 <0 0x0aec2600 0 0xa0>, 4110 <0 0x0aec2000 0 0x1c0>; 4111 4112 clocks = <&rpmhcc RPMH_CXO_CLK>, 4113 <&gcc GCC_EDP_CLKREF_EN>; 4114 clock-names = "aux", 4115 "cfg_ahb"; 4116 4117 #clock-cells = <1>; 4118 #phy-cells = <0>; 4119 4120 status = "disabled"; 4121 }; 4122 4123 mdss_dp: displayport-controller@ae90000 { 4124 compatible = "qcom,sc7280-dp"; 4125 4126 reg = <0 0x0ae90000 0 0x200>, 4127 <0 0x0ae90200 0 0x200>, 4128 <0 0x0ae90400 0 0xc00>, 4129 <0 0x0ae91000 0 0x400>, 4130 <0 0x0ae91400 0 0x400>; 4131 4132 interrupt-parent = <&mdss>; 4133 interrupts = <12>; 4134 4135 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4136 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4137 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4138 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4139 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4140 clock-names = "core_iface", 4141 "core_aux", 4142 "ctrl_link", 4143 "ctrl_link_iface", 4144 "stream_pixel"; 4145 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4146 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4147 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4148 phys = <&dp_phy>; 4149 phy-names = "dp"; 4150 4151 operating-points-v2 = <&dp_opp_table>; 4152 power-domains = <&rpmhpd SC7280_CX>; 4153 4154 #sound-dai-cells = <0>; 4155 4156 status = "disabled"; 4157 4158 ports { 4159 #address-cells = <1>; 4160 #size-cells = <0>; 4161 4162 port@0 { 4163 reg = <0>; 4164 dp_in: endpoint { 4165 remote-endpoint = <&dpu_intf0_out>; 4166 }; 4167 }; 4168 4169 port@1 { 4170 reg = <1>; 4171 mdss_dp_out: endpoint { }; 4172 }; 4173 }; 4174 4175 dp_opp_table: opp-table { 4176 compatible = "operating-points-v2"; 4177 4178 opp-160000000 { 4179 opp-hz = /bits/ 64 <160000000>; 4180 required-opps = <&rpmhpd_opp_low_svs>; 4181 }; 4182 4183 opp-270000000 { 4184 opp-hz = /bits/ 64 <270000000>; 4185 required-opps = <&rpmhpd_opp_svs>; 4186 }; 4187 4188 opp-540000000 { 4189 opp-hz = /bits/ 64 <540000000>; 4190 required-opps = <&rpmhpd_opp_svs_l1>; 4191 }; 4192 4193 opp-810000000 { 4194 opp-hz = /bits/ 64 <810000000>; 4195 required-opps = <&rpmhpd_opp_nom>; 4196 }; 4197 }; 4198 }; 4199 }; 4200 4201 pdc: interrupt-controller@b220000 { 4202 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4203 reg = <0 0x0b220000 0 0x30000>; 4204 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4205 <55 306 4>, <59 312 3>, <62 374 2>, 4206 <64 434 2>, <66 438 3>, <69 86 1>, 4207 <70 520 54>, <124 609 31>, <155 63 1>, 4208 <156 716 12>; 4209 #interrupt-cells = <2>; 4210 interrupt-parent = <&intc>; 4211 interrupt-controller; 4212 }; 4213 4214 pdc_reset: reset-controller@b5e0000 { 4215 compatible = "qcom,sc7280-pdc-global"; 4216 reg = <0 0x0b5e0000 0 0x20000>; 4217 #reset-cells = <1>; 4218 status = "reserved"; /* Owned by firmware */ 4219 }; 4220 4221 tsens0: thermal-sensor@c263000 { 4222 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4223 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4224 <0 0x0c222000 0 0x1ff>; /* SROT */ 4225 #qcom,sensors = <15>; 4226 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4228 interrupt-names = "uplow","critical"; 4229 #thermal-sensor-cells = <1>; 4230 }; 4231 4232 tsens1: thermal-sensor@c265000 { 4233 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4234 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4235 <0 0x0c223000 0 0x1ff>; /* SROT */ 4236 #qcom,sensors = <12>; 4237 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4239 interrupt-names = "uplow","critical"; 4240 #thermal-sensor-cells = <1>; 4241 }; 4242 4243 aoss_reset: reset-controller@c2a0000 { 4244 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4245 reg = <0 0x0c2a0000 0 0x31000>; 4246 #reset-cells = <1>; 4247 }; 4248 4249 aoss_qmp: power-management@c300000 { 4250 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4251 reg = <0 0x0c300000 0 0x400>; 4252 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4253 IPCC_MPROC_SIGNAL_GLINK_QMP 4254 IRQ_TYPE_EDGE_RISING>; 4255 mboxes = <&ipcc IPCC_CLIENT_AOP 4256 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4257 4258 #clock-cells = <0>; 4259 }; 4260 4261 sram@c3f0000 { 4262 compatible = "qcom,rpmh-stats"; 4263 reg = <0 0x0c3f0000 0 0x400>; 4264 }; 4265 4266 spmi_bus: spmi@c440000 { 4267 compatible = "qcom,spmi-pmic-arb"; 4268 reg = <0 0x0c440000 0 0x1100>, 4269 <0 0x0c600000 0 0x2000000>, 4270 <0 0x0e600000 0 0x100000>, 4271 <0 0x0e700000 0 0xa0000>, 4272 <0 0x0c40a000 0 0x26000>; 4273 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4274 interrupt-names = "periph_irq"; 4275 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4276 qcom,ee = <0>; 4277 qcom,channel = <0>; 4278 #address-cells = <2>; 4279 #size-cells = <0>; 4280 interrupt-controller; 4281 #interrupt-cells = <4>; 4282 }; 4283 4284 tlmm: pinctrl@f100000 { 4285 compatible = "qcom,sc7280-pinctrl"; 4286 reg = <0 0x0f100000 0 0x300000>; 4287 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4288 gpio-controller; 4289 #gpio-cells = <2>; 4290 interrupt-controller; 4291 #interrupt-cells = <2>; 4292 gpio-ranges = <&tlmm 0 0 175>; 4293 wakeup-parent = <&pdc>; 4294 4295 dp_hot_plug_det: dp-hot-plug-det-state { 4296 pins = "gpio47"; 4297 function = "dp_hot"; 4298 }; 4299 4300 edp_hot_plug_det: edp-hot-plug-det-state { 4301 pins = "gpio60"; 4302 function = "edp_hot"; 4303 }; 4304 4305 mi2s0_data0: mi2s0-data0-state { 4306 pins = "gpio98"; 4307 function = "mi2s0_data0"; 4308 }; 4309 4310 mi2s0_data1: mi2s0-data1-state { 4311 pins = "gpio99"; 4312 function = "mi2s0_data1"; 4313 }; 4314 4315 mi2s0_mclk: mi2s0-mclk-state { 4316 pins = "gpio96"; 4317 function = "pri_mi2s"; 4318 }; 4319 4320 mi2s0_sclk: mi2s0-sclk-state { 4321 pins = "gpio97"; 4322 function = "mi2s0_sck"; 4323 }; 4324 4325 mi2s0_ws: mi2s0-ws-state { 4326 pins = "gpio100"; 4327 function = "mi2s0_ws"; 4328 }; 4329 4330 mi2s1_data0: mi2s1-data0-state { 4331 pins = "gpio107"; 4332 function = "mi2s1_data0"; 4333 }; 4334 4335 mi2s1_sclk: mi2s1-sclk-state { 4336 pins = "gpio106"; 4337 function = "mi2s1_sck"; 4338 }; 4339 4340 mi2s1_ws: mi2s1-ws-state { 4341 pins = "gpio108"; 4342 function = "mi2s1_ws"; 4343 }; 4344 4345 pcie1_clkreq_n: pcie1-clkreq-n-state { 4346 pins = "gpio79"; 4347 function = "pcie1_clkreqn"; 4348 }; 4349 4350 qspi_clk: qspi-clk-state { 4351 pins = "gpio14"; 4352 function = "qspi_clk"; 4353 }; 4354 4355 qspi_cs0: qspi-cs0-state { 4356 pins = "gpio15"; 4357 function = "qspi_cs"; 4358 }; 4359 4360 qspi_cs1: qspi-cs1-state { 4361 pins = "gpio19"; 4362 function = "qspi_cs"; 4363 }; 4364 4365 qspi_data0: qspi-data0-state { 4366 pins = "gpio12"; 4367 function = "qspi_data"; 4368 }; 4369 4370 qspi_data1: qspi-data1-state { 4371 pins = "gpio13"; 4372 function = "qspi_data"; 4373 }; 4374 4375 qspi_data23: qspi-data23-state { 4376 pins = "gpio16", "gpio17"; 4377 function = "qspi_data"; 4378 }; 4379 4380 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4381 pins = "gpio0", "gpio1"; 4382 function = "qup00"; 4383 }; 4384 4385 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4386 pins = "gpio4", "gpio5"; 4387 function = "qup01"; 4388 }; 4389 4390 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4391 pins = "gpio8", "gpio9"; 4392 function = "qup02"; 4393 }; 4394 4395 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4396 pins = "gpio12", "gpio13"; 4397 function = "qup03"; 4398 }; 4399 4400 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4401 pins = "gpio16", "gpio17"; 4402 function = "qup04"; 4403 }; 4404 4405 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4406 pins = "gpio20", "gpio21"; 4407 function = "qup05"; 4408 }; 4409 4410 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4411 pins = "gpio24", "gpio25"; 4412 function = "qup06"; 4413 }; 4414 4415 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4416 pins = "gpio28", "gpio29"; 4417 function = "qup07"; 4418 }; 4419 4420 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4421 pins = "gpio32", "gpio33"; 4422 function = "qup10"; 4423 }; 4424 4425 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4426 pins = "gpio36", "gpio37"; 4427 function = "qup11"; 4428 }; 4429 4430 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4431 pins = "gpio40", "gpio41"; 4432 function = "qup12"; 4433 }; 4434 4435 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4436 pins = "gpio44", "gpio45"; 4437 function = "qup13"; 4438 }; 4439 4440 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4441 pins = "gpio48", "gpio49"; 4442 function = "qup14"; 4443 }; 4444 4445 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4446 pins = "gpio52", "gpio53"; 4447 function = "qup15"; 4448 }; 4449 4450 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4451 pins = "gpio56", "gpio57"; 4452 function = "qup16"; 4453 }; 4454 4455 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4456 pins = "gpio60", "gpio61"; 4457 function = "qup17"; 4458 }; 4459 4460 qup_spi0_data_clk: qup-spi0-data-clk-state { 4461 pins = "gpio0", "gpio1", "gpio2"; 4462 function = "qup00"; 4463 }; 4464 4465 qup_spi0_cs: qup-spi0-cs-state { 4466 pins = "gpio3"; 4467 function = "qup00"; 4468 }; 4469 4470 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4471 pins = "gpio3"; 4472 function = "gpio"; 4473 }; 4474 4475 qup_spi1_data_clk: qup-spi1-data-clk-state { 4476 pins = "gpio4", "gpio5", "gpio6"; 4477 function = "qup01"; 4478 }; 4479 4480 qup_spi1_cs: qup-spi1-cs-state { 4481 pins = "gpio7"; 4482 function = "qup01"; 4483 }; 4484 4485 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4486 pins = "gpio7"; 4487 function = "gpio"; 4488 }; 4489 4490 qup_spi2_data_clk: qup-spi2-data-clk-state { 4491 pins = "gpio8", "gpio9", "gpio10"; 4492 function = "qup02"; 4493 }; 4494 4495 qup_spi2_cs: qup-spi2-cs-state { 4496 pins = "gpio11"; 4497 function = "qup02"; 4498 }; 4499 4500 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4501 pins = "gpio11"; 4502 function = "gpio"; 4503 }; 4504 4505 qup_spi3_data_clk: qup-spi3-data-clk-state { 4506 pins = "gpio12", "gpio13", "gpio14"; 4507 function = "qup03"; 4508 }; 4509 4510 qup_spi3_cs: qup-spi3-cs-state { 4511 pins = "gpio15"; 4512 function = "qup03"; 4513 }; 4514 4515 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4516 pins = "gpio15"; 4517 function = "gpio"; 4518 }; 4519 4520 qup_spi4_data_clk: qup-spi4-data-clk-state { 4521 pins = "gpio16", "gpio17", "gpio18"; 4522 function = "qup04"; 4523 }; 4524 4525 qup_spi4_cs: qup-spi4-cs-state { 4526 pins = "gpio19"; 4527 function = "qup04"; 4528 }; 4529 4530 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4531 pins = "gpio19"; 4532 function = "gpio"; 4533 }; 4534 4535 qup_spi5_data_clk: qup-spi5-data-clk-state { 4536 pins = "gpio20", "gpio21", "gpio22"; 4537 function = "qup05"; 4538 }; 4539 4540 qup_spi5_cs: qup-spi5-cs-state { 4541 pins = "gpio23"; 4542 function = "qup05"; 4543 }; 4544 4545 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4546 pins = "gpio23"; 4547 function = "gpio"; 4548 }; 4549 4550 qup_spi6_data_clk: qup-spi6-data-clk-state { 4551 pins = "gpio24", "gpio25", "gpio26"; 4552 function = "qup06"; 4553 }; 4554 4555 qup_spi6_cs: qup-spi6-cs-state { 4556 pins = "gpio27"; 4557 function = "qup06"; 4558 }; 4559 4560 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4561 pins = "gpio27"; 4562 function = "gpio"; 4563 }; 4564 4565 qup_spi7_data_clk: qup-spi7-data-clk-state { 4566 pins = "gpio28", "gpio29", "gpio30"; 4567 function = "qup07"; 4568 }; 4569 4570 qup_spi7_cs: qup-spi7-cs-state { 4571 pins = "gpio31"; 4572 function = "qup07"; 4573 }; 4574 4575 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4576 pins = "gpio31"; 4577 function = "gpio"; 4578 }; 4579 4580 qup_spi8_data_clk: qup-spi8-data-clk-state { 4581 pins = "gpio32", "gpio33", "gpio34"; 4582 function = "qup10"; 4583 }; 4584 4585 qup_spi8_cs: qup-spi8-cs-state { 4586 pins = "gpio35"; 4587 function = "qup10"; 4588 }; 4589 4590 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4591 pins = "gpio35"; 4592 function = "gpio"; 4593 }; 4594 4595 qup_spi9_data_clk: qup-spi9-data-clk-state { 4596 pins = "gpio36", "gpio37", "gpio38"; 4597 function = "qup11"; 4598 }; 4599 4600 qup_spi9_cs: qup-spi9-cs-state { 4601 pins = "gpio39"; 4602 function = "qup11"; 4603 }; 4604 4605 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4606 pins = "gpio39"; 4607 function = "gpio"; 4608 }; 4609 4610 qup_spi10_data_clk: qup-spi10-data-clk-state { 4611 pins = "gpio40", "gpio41", "gpio42"; 4612 function = "qup12"; 4613 }; 4614 4615 qup_spi10_cs: qup-spi10-cs-state { 4616 pins = "gpio43"; 4617 function = "qup12"; 4618 }; 4619 4620 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4621 pins = "gpio43"; 4622 function = "gpio"; 4623 }; 4624 4625 qup_spi11_data_clk: qup-spi11-data-clk-state { 4626 pins = "gpio44", "gpio45", "gpio46"; 4627 function = "qup13"; 4628 }; 4629 4630 qup_spi11_cs: qup-spi11-cs-state { 4631 pins = "gpio47"; 4632 function = "qup13"; 4633 }; 4634 4635 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4636 pins = "gpio47"; 4637 function = "gpio"; 4638 }; 4639 4640 qup_spi12_data_clk: qup-spi12-data-clk-state { 4641 pins = "gpio48", "gpio49", "gpio50"; 4642 function = "qup14"; 4643 }; 4644 4645 qup_spi12_cs: qup-spi12-cs-state { 4646 pins = "gpio51"; 4647 function = "qup14"; 4648 }; 4649 4650 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4651 pins = "gpio51"; 4652 function = "gpio"; 4653 }; 4654 4655 qup_spi13_data_clk: qup-spi13-data-clk-state { 4656 pins = "gpio52", "gpio53", "gpio54"; 4657 function = "qup15"; 4658 }; 4659 4660 qup_spi13_cs: qup-spi13-cs-state { 4661 pins = "gpio55"; 4662 function = "qup15"; 4663 }; 4664 4665 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4666 pins = "gpio55"; 4667 function = "gpio"; 4668 }; 4669 4670 qup_spi14_data_clk: qup-spi14-data-clk-state { 4671 pins = "gpio56", "gpio57", "gpio58"; 4672 function = "qup16"; 4673 }; 4674 4675 qup_spi14_cs: qup-spi14-cs-state { 4676 pins = "gpio59"; 4677 function = "qup16"; 4678 }; 4679 4680 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4681 pins = "gpio59"; 4682 function = "gpio"; 4683 }; 4684 4685 qup_spi15_data_clk: qup-spi15-data-clk-state { 4686 pins = "gpio60", "gpio61", "gpio62"; 4687 function = "qup17"; 4688 }; 4689 4690 qup_spi15_cs: qup-spi15-cs-state { 4691 pins = "gpio63"; 4692 function = "qup17"; 4693 }; 4694 4695 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4696 pins = "gpio63"; 4697 function = "gpio"; 4698 }; 4699 4700 qup_uart0_cts: qup-uart0-cts-state { 4701 pins = "gpio0"; 4702 function = "qup00"; 4703 }; 4704 4705 qup_uart0_rts: qup-uart0-rts-state { 4706 pins = "gpio1"; 4707 function = "qup00"; 4708 }; 4709 4710 qup_uart0_tx: qup-uart0-tx-state { 4711 pins = "gpio2"; 4712 function = "qup00"; 4713 }; 4714 4715 qup_uart0_rx: qup-uart0-rx-state { 4716 pins = "gpio3"; 4717 function = "qup00"; 4718 }; 4719 4720 qup_uart1_cts: qup-uart1-cts-state { 4721 pins = "gpio4"; 4722 function = "qup01"; 4723 }; 4724 4725 qup_uart1_rts: qup-uart1-rts-state { 4726 pins = "gpio5"; 4727 function = "qup01"; 4728 }; 4729 4730 qup_uart1_tx: qup-uart1-tx-state { 4731 pins = "gpio6"; 4732 function = "qup01"; 4733 }; 4734 4735 qup_uart1_rx: qup-uart1-rx-state { 4736 pins = "gpio7"; 4737 function = "qup01"; 4738 }; 4739 4740 qup_uart2_cts: qup-uart2-cts-state { 4741 pins = "gpio8"; 4742 function = "qup02"; 4743 }; 4744 4745 qup_uart2_rts: qup-uart2-rts-state { 4746 pins = "gpio9"; 4747 function = "qup02"; 4748 }; 4749 4750 qup_uart2_tx: qup-uart2-tx-state { 4751 pins = "gpio10"; 4752 function = "qup02"; 4753 }; 4754 4755 qup_uart2_rx: qup-uart2-rx-state { 4756 pins = "gpio11"; 4757 function = "qup02"; 4758 }; 4759 4760 qup_uart3_cts: qup-uart3-cts-state { 4761 pins = "gpio12"; 4762 function = "qup03"; 4763 }; 4764 4765 qup_uart3_rts: qup-uart3-rts-state { 4766 pins = "gpio13"; 4767 function = "qup03"; 4768 }; 4769 4770 qup_uart3_tx: qup-uart3-tx-state { 4771 pins = "gpio14"; 4772 function = "qup03"; 4773 }; 4774 4775 qup_uart3_rx: qup-uart3-rx-state { 4776 pins = "gpio15"; 4777 function = "qup03"; 4778 }; 4779 4780 qup_uart4_cts: qup-uart4-cts-state { 4781 pins = "gpio16"; 4782 function = "qup04"; 4783 }; 4784 4785 qup_uart4_rts: qup-uart4-rts-state { 4786 pins = "gpio17"; 4787 function = "qup04"; 4788 }; 4789 4790 qup_uart4_tx: qup-uart4-tx-state { 4791 pins = "gpio18"; 4792 function = "qup04"; 4793 }; 4794 4795 qup_uart4_rx: qup-uart4-rx-state { 4796 pins = "gpio19"; 4797 function = "qup04"; 4798 }; 4799 4800 qup_uart5_cts: qup-uart5-cts-state { 4801 pins = "gpio20"; 4802 function = "qup05"; 4803 }; 4804 4805 qup_uart5_rts: qup-uart5-rts-state { 4806 pins = "gpio21"; 4807 function = "qup05"; 4808 }; 4809 4810 qup_uart5_tx: qup-uart5-tx-state { 4811 pins = "gpio22"; 4812 function = "qup05"; 4813 }; 4814 4815 qup_uart5_rx: qup-uart5-rx-state { 4816 pins = "gpio23"; 4817 function = "qup05"; 4818 }; 4819 4820 qup_uart6_cts: qup-uart6-cts-state { 4821 pins = "gpio24"; 4822 function = "qup06"; 4823 }; 4824 4825 qup_uart6_rts: qup-uart6-rts-state { 4826 pins = "gpio25"; 4827 function = "qup06"; 4828 }; 4829 4830 qup_uart6_tx: qup-uart6-tx-state { 4831 pins = "gpio26"; 4832 function = "qup06"; 4833 }; 4834 4835 qup_uart6_rx: qup-uart6-rx-state { 4836 pins = "gpio27"; 4837 function = "qup06"; 4838 }; 4839 4840 qup_uart7_cts: qup-uart7-cts-state { 4841 pins = "gpio28"; 4842 function = "qup07"; 4843 }; 4844 4845 qup_uart7_rts: qup-uart7-rts-state { 4846 pins = "gpio29"; 4847 function = "qup07"; 4848 }; 4849 4850 qup_uart7_tx: qup-uart7-tx-state { 4851 pins = "gpio30"; 4852 function = "qup07"; 4853 }; 4854 4855 qup_uart7_rx: qup-uart7-rx-state { 4856 pins = "gpio31"; 4857 function = "qup07"; 4858 }; 4859 4860 qup_uart8_cts: qup-uart8-cts-state { 4861 pins = "gpio32"; 4862 function = "qup10"; 4863 }; 4864 4865 qup_uart8_rts: qup-uart8-rts-state { 4866 pins = "gpio33"; 4867 function = "qup10"; 4868 }; 4869 4870 qup_uart8_tx: qup-uart8-tx-state { 4871 pins = "gpio34"; 4872 function = "qup10"; 4873 }; 4874 4875 qup_uart8_rx: qup-uart8-rx-state { 4876 pins = "gpio35"; 4877 function = "qup10"; 4878 }; 4879 4880 qup_uart9_cts: qup-uart9-cts-state { 4881 pins = "gpio36"; 4882 function = "qup11"; 4883 }; 4884 4885 qup_uart9_rts: qup-uart9-rts-state { 4886 pins = "gpio37"; 4887 function = "qup11"; 4888 }; 4889 4890 qup_uart9_tx: qup-uart9-tx-state { 4891 pins = "gpio38"; 4892 function = "qup11"; 4893 }; 4894 4895 qup_uart9_rx: qup-uart9-rx-state { 4896 pins = "gpio39"; 4897 function = "qup11"; 4898 }; 4899 4900 qup_uart10_cts: qup-uart10-cts-state { 4901 pins = "gpio40"; 4902 function = "qup12"; 4903 }; 4904 4905 qup_uart10_rts: qup-uart10-rts-state { 4906 pins = "gpio41"; 4907 function = "qup12"; 4908 }; 4909 4910 qup_uart10_tx: qup-uart10-tx-state { 4911 pins = "gpio42"; 4912 function = "qup12"; 4913 }; 4914 4915 qup_uart10_rx: qup-uart10-rx-state { 4916 pins = "gpio43"; 4917 function = "qup12"; 4918 }; 4919 4920 qup_uart11_cts: qup-uart11-cts-state { 4921 pins = "gpio44"; 4922 function = "qup13"; 4923 }; 4924 4925 qup_uart11_rts: qup-uart11-rts-state { 4926 pins = "gpio45"; 4927 function = "qup13"; 4928 }; 4929 4930 qup_uart11_tx: qup-uart11-tx-state { 4931 pins = "gpio46"; 4932 function = "qup13"; 4933 }; 4934 4935 qup_uart11_rx: qup-uart11-rx-state { 4936 pins = "gpio47"; 4937 function = "qup13"; 4938 }; 4939 4940 qup_uart12_cts: qup-uart12-cts-state { 4941 pins = "gpio48"; 4942 function = "qup14"; 4943 }; 4944 4945 qup_uart12_rts: qup-uart12-rts-state { 4946 pins = "gpio49"; 4947 function = "qup14"; 4948 }; 4949 4950 qup_uart12_tx: qup-uart12-tx-state { 4951 pins = "gpio50"; 4952 function = "qup14"; 4953 }; 4954 4955 qup_uart12_rx: qup-uart12-rx-state { 4956 pins = "gpio51"; 4957 function = "qup14"; 4958 }; 4959 4960 qup_uart13_cts: qup-uart13-cts-state { 4961 pins = "gpio52"; 4962 function = "qup15"; 4963 }; 4964 4965 qup_uart13_rts: qup-uart13-rts-state { 4966 pins = "gpio53"; 4967 function = "qup15"; 4968 }; 4969 4970 qup_uart13_tx: qup-uart13-tx-state { 4971 pins = "gpio54"; 4972 function = "qup15"; 4973 }; 4974 4975 qup_uart13_rx: qup-uart13-rx-state { 4976 pins = "gpio55"; 4977 function = "qup15"; 4978 }; 4979 4980 qup_uart14_cts: qup-uart14-cts-state { 4981 pins = "gpio56"; 4982 function = "qup16"; 4983 }; 4984 4985 qup_uart14_rts: qup-uart14-rts-state { 4986 pins = "gpio57"; 4987 function = "qup16"; 4988 }; 4989 4990 qup_uart14_tx: qup-uart14-tx-state { 4991 pins = "gpio58"; 4992 function = "qup16"; 4993 }; 4994 4995 qup_uart14_rx: qup-uart14-rx-state { 4996 pins = "gpio59"; 4997 function = "qup16"; 4998 }; 4999 5000 qup_uart15_cts: qup-uart15-cts-state { 5001 pins = "gpio60"; 5002 function = "qup17"; 5003 }; 5004 5005 qup_uart15_rts: qup-uart15-rts-state { 5006 pins = "gpio61"; 5007 function = "qup17"; 5008 }; 5009 5010 qup_uart15_tx: qup-uart15-tx-state { 5011 pins = "gpio62"; 5012 function = "qup17"; 5013 }; 5014 5015 qup_uart15_rx: qup-uart15-rx-state { 5016 pins = "gpio63"; 5017 function = "qup17"; 5018 }; 5019 5020 sdc1_clk: sdc1-clk-state { 5021 pins = "sdc1_clk"; 5022 }; 5023 5024 sdc1_cmd: sdc1-cmd-state { 5025 pins = "sdc1_cmd"; 5026 }; 5027 5028 sdc1_data: sdc1-data-state { 5029 pins = "sdc1_data"; 5030 }; 5031 5032 sdc1_rclk: sdc1-rclk-state { 5033 pins = "sdc1_rclk"; 5034 }; 5035 5036 sdc1_clk_sleep: sdc1-clk-sleep-state { 5037 pins = "sdc1_clk"; 5038 drive-strength = <2>; 5039 bias-bus-hold; 5040 }; 5041 5042 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5043 pins = "sdc1_cmd"; 5044 drive-strength = <2>; 5045 bias-bus-hold; 5046 }; 5047 5048 sdc1_data_sleep: sdc1-data-sleep-state { 5049 pins = "sdc1_data"; 5050 drive-strength = <2>; 5051 bias-bus-hold; 5052 }; 5053 5054 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5055 pins = "sdc1_rclk"; 5056 drive-strength = <2>; 5057 bias-bus-hold; 5058 }; 5059 5060 sdc2_clk: sdc2-clk-state { 5061 pins = "sdc2_clk"; 5062 }; 5063 5064 sdc2_cmd: sdc2-cmd-state { 5065 pins = "sdc2_cmd"; 5066 }; 5067 5068 sdc2_data: sdc2-data-state { 5069 pins = "sdc2_data"; 5070 }; 5071 5072 sdc2_clk_sleep: sdc2-clk-sleep-state { 5073 pins = "sdc2_clk"; 5074 drive-strength = <2>; 5075 bias-bus-hold; 5076 }; 5077 5078 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5079 pins = "sdc2_cmd"; 5080 drive-strength = <2>; 5081 bias-bus-hold; 5082 }; 5083 5084 sdc2_data_sleep: sdc2-data-sleep-state { 5085 pins = "sdc2_data"; 5086 drive-strength = <2>; 5087 bias-bus-hold; 5088 }; 5089 }; 5090 5091 sram@146a5000 { 5092 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5093 reg = <0 0x146a5000 0 0x6000>; 5094 5095 #address-cells = <1>; 5096 #size-cells = <1>; 5097 5098 ranges = <0 0 0x146a5000 0x6000>; 5099 5100 pil-reloc@594c { 5101 compatible = "qcom,pil-reloc-info"; 5102 reg = <0x594c 0xc8>; 5103 }; 5104 }; 5105 5106 apps_smmu: iommu@15000000 { 5107 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5108 reg = <0 0x15000000 0 0x100000>; 5109 #iommu-cells = <2>; 5110 #global-interrupts = <1>; 5111 dma-coherent; 5112 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5193 }; 5194 5195 intc: interrupt-controller@17a00000 { 5196 compatible = "arm,gic-v3"; 5197 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5198 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5199 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5200 #interrupt-cells = <3>; 5201 interrupt-controller; 5202 #address-cells = <2>; 5203 #size-cells = <2>; 5204 ranges; 5205 5206 msi-controller@17a40000 { 5207 compatible = "arm,gic-v3-its"; 5208 reg = <0 0x17a40000 0 0x20000>; 5209 msi-controller; 5210 #msi-cells = <1>; 5211 status = "disabled"; 5212 }; 5213 }; 5214 5215 watchdog: watchdog@17c10000 { 5216 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5217 reg = <0 0x17c10000 0 0x1000>; 5218 clocks = <&sleep_clk>; 5219 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5220 status = "reserved"; /* Owned by Gunyah hyp */ 5221 }; 5222 5223 timer@17c20000 { 5224 #address-cells = <1>; 5225 #size-cells = <1>; 5226 ranges = <0 0 0 0x20000000>; 5227 compatible = "arm,armv7-timer-mem"; 5228 reg = <0 0x17c20000 0 0x1000>; 5229 5230 frame@17c21000 { 5231 frame-number = <0>; 5232 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5233 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5234 reg = <0x17c21000 0x1000>, 5235 <0x17c22000 0x1000>; 5236 }; 5237 5238 frame@17c23000 { 5239 frame-number = <1>; 5240 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5241 reg = <0x17c23000 0x1000>; 5242 status = "disabled"; 5243 }; 5244 5245 frame@17c25000 { 5246 frame-number = <2>; 5247 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5248 reg = <0x17c25000 0x1000>; 5249 status = "disabled"; 5250 }; 5251 5252 frame@17c27000 { 5253 frame-number = <3>; 5254 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5255 reg = <0x17c27000 0x1000>; 5256 status = "disabled"; 5257 }; 5258 5259 frame@17c29000 { 5260 frame-number = <4>; 5261 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5262 reg = <0x17c29000 0x1000>; 5263 status = "disabled"; 5264 }; 5265 5266 frame@17c2b000 { 5267 frame-number = <5>; 5268 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5269 reg = <0x17c2b000 0x1000>; 5270 status = "disabled"; 5271 }; 5272 5273 frame@17c2d000 { 5274 frame-number = <6>; 5275 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5276 reg = <0x17c2d000 0x1000>; 5277 status = "disabled"; 5278 }; 5279 }; 5280 5281 apps_rsc: rsc@18200000 { 5282 compatible = "qcom,rpmh-rsc"; 5283 reg = <0 0x18200000 0 0x10000>, 5284 <0 0x18210000 0 0x10000>, 5285 <0 0x18220000 0 0x10000>; 5286 reg-names = "drv-0", "drv-1", "drv-2"; 5287 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5288 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5289 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5290 qcom,tcs-offset = <0xd00>; 5291 qcom,drv-id = <2>; 5292 qcom,tcs-config = <ACTIVE_TCS 2>, 5293 <SLEEP_TCS 3>, 5294 <WAKE_TCS 3>, 5295 <CONTROL_TCS 1>; 5296 5297 apps_bcm_voter: bcm-voter { 5298 compatible = "qcom,bcm-voter"; 5299 }; 5300 5301 rpmhpd: power-controller { 5302 compatible = "qcom,sc7280-rpmhpd"; 5303 #power-domain-cells = <1>; 5304 operating-points-v2 = <&rpmhpd_opp_table>; 5305 5306 rpmhpd_opp_table: opp-table { 5307 compatible = "operating-points-v2"; 5308 5309 rpmhpd_opp_ret: opp1 { 5310 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5311 }; 5312 5313 rpmhpd_opp_low_svs: opp2 { 5314 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5315 }; 5316 5317 rpmhpd_opp_svs: opp3 { 5318 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5319 }; 5320 5321 rpmhpd_opp_svs_l1: opp4 { 5322 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5323 }; 5324 5325 rpmhpd_opp_svs_l2: opp5 { 5326 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5327 }; 5328 5329 rpmhpd_opp_nom: opp6 { 5330 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5331 }; 5332 5333 rpmhpd_opp_nom_l1: opp7 { 5334 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5335 }; 5336 5337 rpmhpd_opp_turbo: opp8 { 5338 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5339 }; 5340 5341 rpmhpd_opp_turbo_l1: opp9 { 5342 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5343 }; 5344 }; 5345 }; 5346 5347 rpmhcc: clock-controller { 5348 compatible = "qcom,sc7280-rpmh-clk"; 5349 clocks = <&xo_board>; 5350 clock-names = "xo"; 5351 #clock-cells = <1>; 5352 }; 5353 }; 5354 5355 epss_l3: interconnect@18590000 { 5356 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5357 reg = <0 0x18590000 0 0x1000>; 5358 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5359 clock-names = "xo", "alternate"; 5360 #interconnect-cells = <1>; 5361 }; 5362 5363 cpufreq_hw: cpufreq@18591000 { 5364 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5365 reg = <0 0x18591000 0 0x1000>, 5366 <0 0x18592000 0 0x1000>, 5367 <0 0x18593000 0 0x1000>; 5368 5369 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5370 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5371 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5372 interrupt-names = "dcvsh-irq-0", 5373 "dcvsh-irq-1", 5374 "dcvsh-irq-2"; 5375 5376 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5377 clock-names = "xo", "alternate"; 5378 #freq-domain-cells = <1>; 5379 #clock-cells = <1>; 5380 }; 5381 }; 5382 5383 thermal_zones: thermal-zones { 5384 cpu0-thermal { 5385 polling-delay-passive = <250>; 5386 polling-delay = <0>; 5387 5388 thermal-sensors = <&tsens0 1>; 5389 5390 trips { 5391 cpu0_alert0: trip-point0 { 5392 temperature = <90000>; 5393 hysteresis = <2000>; 5394 type = "passive"; 5395 }; 5396 5397 cpu0_alert1: trip-point1 { 5398 temperature = <95000>; 5399 hysteresis = <2000>; 5400 type = "passive"; 5401 }; 5402 5403 cpu0_crit: cpu-crit { 5404 temperature = <110000>; 5405 hysteresis = <0>; 5406 type = "critical"; 5407 }; 5408 }; 5409 5410 cooling-maps { 5411 map0 { 5412 trip = <&cpu0_alert0>; 5413 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5414 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5415 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5416 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5417 }; 5418 map1 { 5419 trip = <&cpu0_alert1>; 5420 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5421 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5422 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5423 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5424 }; 5425 }; 5426 }; 5427 5428 cpu1-thermal { 5429 polling-delay-passive = <250>; 5430 polling-delay = <0>; 5431 5432 thermal-sensors = <&tsens0 2>; 5433 5434 trips { 5435 cpu1_alert0: trip-point0 { 5436 temperature = <90000>; 5437 hysteresis = <2000>; 5438 type = "passive"; 5439 }; 5440 5441 cpu1_alert1: trip-point1 { 5442 temperature = <95000>; 5443 hysteresis = <2000>; 5444 type = "passive"; 5445 }; 5446 5447 cpu1_crit: cpu-crit { 5448 temperature = <110000>; 5449 hysteresis = <0>; 5450 type = "critical"; 5451 }; 5452 }; 5453 5454 cooling-maps { 5455 map0 { 5456 trip = <&cpu1_alert0>; 5457 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5458 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5459 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5460 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5461 }; 5462 map1 { 5463 trip = <&cpu1_alert1>; 5464 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5465 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5466 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5467 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5468 }; 5469 }; 5470 }; 5471 5472 cpu2-thermal { 5473 polling-delay-passive = <250>; 5474 polling-delay = <0>; 5475 5476 thermal-sensors = <&tsens0 3>; 5477 5478 trips { 5479 cpu2_alert0: trip-point0 { 5480 temperature = <90000>; 5481 hysteresis = <2000>; 5482 type = "passive"; 5483 }; 5484 5485 cpu2_alert1: trip-point1 { 5486 temperature = <95000>; 5487 hysteresis = <2000>; 5488 type = "passive"; 5489 }; 5490 5491 cpu2_crit: cpu-crit { 5492 temperature = <110000>; 5493 hysteresis = <0>; 5494 type = "critical"; 5495 }; 5496 }; 5497 5498 cooling-maps { 5499 map0 { 5500 trip = <&cpu2_alert0>; 5501 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5502 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5503 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5504 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5505 }; 5506 map1 { 5507 trip = <&cpu2_alert1>; 5508 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5509 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5510 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5511 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5512 }; 5513 }; 5514 }; 5515 5516 cpu3-thermal { 5517 polling-delay-passive = <250>; 5518 polling-delay = <0>; 5519 5520 thermal-sensors = <&tsens0 4>; 5521 5522 trips { 5523 cpu3_alert0: trip-point0 { 5524 temperature = <90000>; 5525 hysteresis = <2000>; 5526 type = "passive"; 5527 }; 5528 5529 cpu3_alert1: trip-point1 { 5530 temperature = <95000>; 5531 hysteresis = <2000>; 5532 type = "passive"; 5533 }; 5534 5535 cpu3_crit: cpu-crit { 5536 temperature = <110000>; 5537 hysteresis = <0>; 5538 type = "critical"; 5539 }; 5540 }; 5541 5542 cooling-maps { 5543 map0 { 5544 trip = <&cpu3_alert0>; 5545 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5546 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5547 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5548 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5549 }; 5550 map1 { 5551 trip = <&cpu3_alert1>; 5552 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5553 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5554 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5555 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5556 }; 5557 }; 5558 }; 5559 5560 cpu4-thermal { 5561 polling-delay-passive = <250>; 5562 polling-delay = <0>; 5563 5564 thermal-sensors = <&tsens0 7>; 5565 5566 trips { 5567 cpu4_alert0: trip-point0 { 5568 temperature = <90000>; 5569 hysteresis = <2000>; 5570 type = "passive"; 5571 }; 5572 5573 cpu4_alert1: trip-point1 { 5574 temperature = <95000>; 5575 hysteresis = <2000>; 5576 type = "passive"; 5577 }; 5578 5579 cpu4_crit: cpu-crit { 5580 temperature = <110000>; 5581 hysteresis = <0>; 5582 type = "critical"; 5583 }; 5584 }; 5585 5586 cooling-maps { 5587 map0 { 5588 trip = <&cpu4_alert0>; 5589 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5590 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5591 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5592 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5593 }; 5594 map1 { 5595 trip = <&cpu4_alert1>; 5596 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5597 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5598 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5599 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5600 }; 5601 }; 5602 }; 5603 5604 cpu5-thermal { 5605 polling-delay-passive = <250>; 5606 polling-delay = <0>; 5607 5608 thermal-sensors = <&tsens0 8>; 5609 5610 trips { 5611 cpu5_alert0: trip-point0 { 5612 temperature = <90000>; 5613 hysteresis = <2000>; 5614 type = "passive"; 5615 }; 5616 5617 cpu5_alert1: trip-point1 { 5618 temperature = <95000>; 5619 hysteresis = <2000>; 5620 type = "passive"; 5621 }; 5622 5623 cpu5_crit: cpu-crit { 5624 temperature = <110000>; 5625 hysteresis = <0>; 5626 type = "critical"; 5627 }; 5628 }; 5629 5630 cooling-maps { 5631 map0 { 5632 trip = <&cpu5_alert0>; 5633 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5634 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5635 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5636 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5637 }; 5638 map1 { 5639 trip = <&cpu5_alert1>; 5640 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5641 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5642 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5643 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5644 }; 5645 }; 5646 }; 5647 5648 cpu6-thermal { 5649 polling-delay-passive = <250>; 5650 polling-delay = <0>; 5651 5652 thermal-sensors = <&tsens0 9>; 5653 5654 trips { 5655 cpu6_alert0: trip-point0 { 5656 temperature = <90000>; 5657 hysteresis = <2000>; 5658 type = "passive"; 5659 }; 5660 5661 cpu6_alert1: trip-point1 { 5662 temperature = <95000>; 5663 hysteresis = <2000>; 5664 type = "passive"; 5665 }; 5666 5667 cpu6_crit: cpu-crit { 5668 temperature = <110000>; 5669 hysteresis = <0>; 5670 type = "critical"; 5671 }; 5672 }; 5673 5674 cooling-maps { 5675 map0 { 5676 trip = <&cpu6_alert0>; 5677 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5678 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5679 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5680 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5681 }; 5682 map1 { 5683 trip = <&cpu6_alert1>; 5684 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5685 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5686 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5687 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5688 }; 5689 }; 5690 }; 5691 5692 cpu7-thermal { 5693 polling-delay-passive = <250>; 5694 polling-delay = <0>; 5695 5696 thermal-sensors = <&tsens0 10>; 5697 5698 trips { 5699 cpu7_alert0: trip-point0 { 5700 temperature = <90000>; 5701 hysteresis = <2000>; 5702 type = "passive"; 5703 }; 5704 5705 cpu7_alert1: trip-point1 { 5706 temperature = <95000>; 5707 hysteresis = <2000>; 5708 type = "passive"; 5709 }; 5710 5711 cpu7_crit: cpu-crit { 5712 temperature = <110000>; 5713 hysteresis = <0>; 5714 type = "critical"; 5715 }; 5716 }; 5717 5718 cooling-maps { 5719 map0 { 5720 trip = <&cpu7_alert0>; 5721 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5722 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5723 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5724 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5725 }; 5726 map1 { 5727 trip = <&cpu7_alert1>; 5728 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5730 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5731 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5732 }; 5733 }; 5734 }; 5735 5736 cpu8-thermal { 5737 polling-delay-passive = <250>; 5738 polling-delay = <0>; 5739 5740 thermal-sensors = <&tsens0 11>; 5741 5742 trips { 5743 cpu8_alert0: trip-point0 { 5744 temperature = <90000>; 5745 hysteresis = <2000>; 5746 type = "passive"; 5747 }; 5748 5749 cpu8_alert1: trip-point1 { 5750 temperature = <95000>; 5751 hysteresis = <2000>; 5752 type = "passive"; 5753 }; 5754 5755 cpu8_crit: cpu-crit { 5756 temperature = <110000>; 5757 hysteresis = <0>; 5758 type = "critical"; 5759 }; 5760 }; 5761 5762 cooling-maps { 5763 map0 { 5764 trip = <&cpu8_alert0>; 5765 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5766 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5767 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5768 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5769 }; 5770 map1 { 5771 trip = <&cpu8_alert1>; 5772 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5773 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5774 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5775 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5776 }; 5777 }; 5778 }; 5779 5780 cpu9-thermal { 5781 polling-delay-passive = <250>; 5782 polling-delay = <0>; 5783 5784 thermal-sensors = <&tsens0 12>; 5785 5786 trips { 5787 cpu9_alert0: trip-point0 { 5788 temperature = <90000>; 5789 hysteresis = <2000>; 5790 type = "passive"; 5791 }; 5792 5793 cpu9_alert1: trip-point1 { 5794 temperature = <95000>; 5795 hysteresis = <2000>; 5796 type = "passive"; 5797 }; 5798 5799 cpu9_crit: cpu-crit { 5800 temperature = <110000>; 5801 hysteresis = <0>; 5802 type = "critical"; 5803 }; 5804 }; 5805 5806 cooling-maps { 5807 map0 { 5808 trip = <&cpu9_alert0>; 5809 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5811 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5812 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5813 }; 5814 map1 { 5815 trip = <&cpu9_alert1>; 5816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5820 }; 5821 }; 5822 }; 5823 5824 cpu10-thermal { 5825 polling-delay-passive = <250>; 5826 polling-delay = <0>; 5827 5828 thermal-sensors = <&tsens0 13>; 5829 5830 trips { 5831 cpu10_alert0: trip-point0 { 5832 temperature = <90000>; 5833 hysteresis = <2000>; 5834 type = "passive"; 5835 }; 5836 5837 cpu10_alert1: trip-point1 { 5838 temperature = <95000>; 5839 hysteresis = <2000>; 5840 type = "passive"; 5841 }; 5842 5843 cpu10_crit: cpu-crit { 5844 temperature = <110000>; 5845 hysteresis = <0>; 5846 type = "critical"; 5847 }; 5848 }; 5849 5850 cooling-maps { 5851 map0 { 5852 trip = <&cpu10_alert0>; 5853 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5855 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5856 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5857 }; 5858 map1 { 5859 trip = <&cpu10_alert1>; 5860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5861 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5862 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5863 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5864 }; 5865 }; 5866 }; 5867 5868 cpu11-thermal { 5869 polling-delay-passive = <250>; 5870 polling-delay = <0>; 5871 5872 thermal-sensors = <&tsens0 14>; 5873 5874 trips { 5875 cpu11_alert0: trip-point0 { 5876 temperature = <90000>; 5877 hysteresis = <2000>; 5878 type = "passive"; 5879 }; 5880 5881 cpu11_alert1: trip-point1 { 5882 temperature = <95000>; 5883 hysteresis = <2000>; 5884 type = "passive"; 5885 }; 5886 5887 cpu11_crit: cpu-crit { 5888 temperature = <110000>; 5889 hysteresis = <0>; 5890 type = "critical"; 5891 }; 5892 }; 5893 5894 cooling-maps { 5895 map0 { 5896 trip = <&cpu11_alert0>; 5897 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5898 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5899 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5900 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5901 }; 5902 map1 { 5903 trip = <&cpu11_alert1>; 5904 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5906 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5907 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5908 }; 5909 }; 5910 }; 5911 5912 aoss0-thermal { 5913 polling-delay-passive = <0>; 5914 polling-delay = <0>; 5915 5916 thermal-sensors = <&tsens0 0>; 5917 5918 trips { 5919 aoss0_alert0: trip-point0 { 5920 temperature = <90000>; 5921 hysteresis = <2000>; 5922 type = "hot"; 5923 }; 5924 5925 aoss0_crit: aoss0-crit { 5926 temperature = <110000>; 5927 hysteresis = <0>; 5928 type = "critical"; 5929 }; 5930 }; 5931 }; 5932 5933 aoss1-thermal { 5934 polling-delay-passive = <0>; 5935 polling-delay = <0>; 5936 5937 thermal-sensors = <&tsens1 0>; 5938 5939 trips { 5940 aoss1_alert0: trip-point0 { 5941 temperature = <90000>; 5942 hysteresis = <2000>; 5943 type = "hot"; 5944 }; 5945 5946 aoss1_crit: aoss1-crit { 5947 temperature = <110000>; 5948 hysteresis = <0>; 5949 type = "critical"; 5950 }; 5951 }; 5952 }; 5953 5954 cpuss0-thermal { 5955 polling-delay-passive = <0>; 5956 polling-delay = <0>; 5957 5958 thermal-sensors = <&tsens0 5>; 5959 5960 trips { 5961 cpuss0_alert0: trip-point0 { 5962 temperature = <90000>; 5963 hysteresis = <2000>; 5964 type = "hot"; 5965 }; 5966 cpuss0_crit: cluster0-crit { 5967 temperature = <110000>; 5968 hysteresis = <0>; 5969 type = "critical"; 5970 }; 5971 }; 5972 }; 5973 5974 cpuss1-thermal { 5975 polling-delay-passive = <0>; 5976 polling-delay = <0>; 5977 5978 thermal-sensors = <&tsens0 6>; 5979 5980 trips { 5981 cpuss1_alert0: trip-point0 { 5982 temperature = <90000>; 5983 hysteresis = <2000>; 5984 type = "hot"; 5985 }; 5986 cpuss1_crit: cluster0-crit { 5987 temperature = <110000>; 5988 hysteresis = <0>; 5989 type = "critical"; 5990 }; 5991 }; 5992 }; 5993 5994 gpuss0-thermal { 5995 polling-delay-passive = <100>; 5996 polling-delay = <0>; 5997 5998 thermal-sensors = <&tsens1 1>; 5999 6000 trips { 6001 gpuss0_alert0: trip-point0 { 6002 temperature = <95000>; 6003 hysteresis = <2000>; 6004 type = "passive"; 6005 }; 6006 6007 gpuss0_crit: gpuss0-crit { 6008 temperature = <110000>; 6009 hysteresis = <0>; 6010 type = "critical"; 6011 }; 6012 }; 6013 6014 cooling-maps { 6015 map0 { 6016 trip = <&gpuss0_alert0>; 6017 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6018 }; 6019 }; 6020 }; 6021 6022 gpuss1-thermal { 6023 polling-delay-passive = <100>; 6024 polling-delay = <0>; 6025 6026 thermal-sensors = <&tsens1 2>; 6027 6028 trips { 6029 gpuss1_alert0: trip-point0 { 6030 temperature = <95000>; 6031 hysteresis = <2000>; 6032 type = "passive"; 6033 }; 6034 6035 gpuss1_crit: gpuss1-crit { 6036 temperature = <110000>; 6037 hysteresis = <0>; 6038 type = "critical"; 6039 }; 6040 }; 6041 6042 cooling-maps { 6043 map0 { 6044 trip = <&gpuss1_alert0>; 6045 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6046 }; 6047 }; 6048 }; 6049 6050 nspss0-thermal { 6051 polling-delay-passive = <0>; 6052 polling-delay = <0>; 6053 6054 thermal-sensors = <&tsens1 3>; 6055 6056 trips { 6057 nspss0_alert0: trip-point0 { 6058 temperature = <90000>; 6059 hysteresis = <2000>; 6060 type = "hot"; 6061 }; 6062 6063 nspss0_crit: nspss0-crit { 6064 temperature = <110000>; 6065 hysteresis = <0>; 6066 type = "critical"; 6067 }; 6068 }; 6069 }; 6070 6071 nspss1-thermal { 6072 polling-delay-passive = <0>; 6073 polling-delay = <0>; 6074 6075 thermal-sensors = <&tsens1 4>; 6076 6077 trips { 6078 nspss1_alert0: trip-point0 { 6079 temperature = <90000>; 6080 hysteresis = <2000>; 6081 type = "hot"; 6082 }; 6083 6084 nspss1_crit: nspss1-crit { 6085 temperature = <110000>; 6086 hysteresis = <0>; 6087 type = "critical"; 6088 }; 6089 }; 6090 }; 6091 6092 video-thermal { 6093 polling-delay-passive = <0>; 6094 polling-delay = <0>; 6095 6096 thermal-sensors = <&tsens1 5>; 6097 6098 trips { 6099 video_alert0: trip-point0 { 6100 temperature = <90000>; 6101 hysteresis = <2000>; 6102 type = "hot"; 6103 }; 6104 6105 video_crit: video-crit { 6106 temperature = <110000>; 6107 hysteresis = <0>; 6108 type = "critical"; 6109 }; 6110 }; 6111 }; 6112 6113 ddr-thermal { 6114 polling-delay-passive = <0>; 6115 polling-delay = <0>; 6116 6117 thermal-sensors = <&tsens1 6>; 6118 6119 trips { 6120 ddr_alert0: trip-point0 { 6121 temperature = <90000>; 6122 hysteresis = <2000>; 6123 type = "hot"; 6124 }; 6125 6126 ddr_crit: ddr-crit { 6127 temperature = <110000>; 6128 hysteresis = <0>; 6129 type = "critical"; 6130 }; 6131 }; 6132 }; 6133 6134 mdmss0-thermal { 6135 polling-delay-passive = <0>; 6136 polling-delay = <0>; 6137 6138 thermal-sensors = <&tsens1 7>; 6139 6140 trips { 6141 mdmss0_alert0: trip-point0 { 6142 temperature = <90000>; 6143 hysteresis = <2000>; 6144 type = "hot"; 6145 }; 6146 6147 mdmss0_crit: mdmss0-crit { 6148 temperature = <110000>; 6149 hysteresis = <0>; 6150 type = "critical"; 6151 }; 6152 }; 6153 }; 6154 6155 mdmss1-thermal { 6156 polling-delay-passive = <0>; 6157 polling-delay = <0>; 6158 6159 thermal-sensors = <&tsens1 8>; 6160 6161 trips { 6162 mdmss1_alert0: trip-point0 { 6163 temperature = <90000>; 6164 hysteresis = <2000>; 6165 type = "hot"; 6166 }; 6167 6168 mdmss1_crit: mdmss1-crit { 6169 temperature = <110000>; 6170 hysteresis = <0>; 6171 type = "critical"; 6172 }; 6173 }; 6174 }; 6175 6176 mdmss2-thermal { 6177 polling-delay-passive = <0>; 6178 polling-delay = <0>; 6179 6180 thermal-sensors = <&tsens1 9>; 6181 6182 trips { 6183 mdmss2_alert0: trip-point0 { 6184 temperature = <90000>; 6185 hysteresis = <2000>; 6186 type = "hot"; 6187 }; 6188 6189 mdmss2_crit: mdmss2-crit { 6190 temperature = <110000>; 6191 hysteresis = <0>; 6192 type = "critical"; 6193 }; 6194 }; 6195 }; 6196 6197 mdmss3-thermal { 6198 polling-delay-passive = <0>; 6199 polling-delay = <0>; 6200 6201 thermal-sensors = <&tsens1 10>; 6202 6203 trips { 6204 mdmss3_alert0: trip-point0 { 6205 temperature = <90000>; 6206 hysteresis = <2000>; 6207 type = "hot"; 6208 }; 6209 6210 mdmss3_crit: mdmss3-crit { 6211 temperature = <110000>; 6212 hysteresis = <0>; 6213 type = "critical"; 6214 }; 6215 }; 6216 }; 6217 6218 camera0-thermal { 6219 polling-delay-passive = <0>; 6220 polling-delay = <0>; 6221 6222 thermal-sensors = <&tsens1 11>; 6223 6224 trips { 6225 camera0_alert0: trip-point0 { 6226 temperature = <90000>; 6227 hysteresis = <2000>; 6228 type = "hot"; 6229 }; 6230 6231 camera0_crit: camera0-crit { 6232 temperature = <110000>; 6233 hysteresis = <0>; 6234 type = "critical"; 6235 }; 6236 }; 6237 }; 6238 }; 6239 6240 timer { 6241 compatible = "arm,armv8-timer"; 6242 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6243 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6244 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6245 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6246 }; 6247}; 6248