// SPDX-License-Identifier: BSD-3-Clause /* * sc7280 SoC device tree source * * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include / { interrupt-parent = <&intc>; #address-cells = <2>; #size-cells = <2>; chosen { }; aliases { i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; i2c7 = &i2c7; i2c8 = &i2c8; i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; i2c12 = &i2c12; i2c13 = &i2c13; i2c14 = &i2c14; i2c15 = &i2c15; mmc1 = &sdhc_1; mmc2 = &sdhc_2; spi0 = &spi0; spi1 = &spi1; spi2 = &spi2; spi3 = &spi3; spi4 = &spi4; spi5 = &spi5; spi6 = &spi6; spi7 = &spi7; spi8 = &spi8; spi9 = &spi9; spi10 = &spi10; spi11 = &spi11; spi12 = &spi12; spi13 = &spi13; spi14 = &spi14; spi15 = &spi15; }; clocks { xo_board: xo-board { compatible = "fixed-clock"; clock-frequency = <76800000>; #clock-cells = <0>; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; clock-frequency = <32000>; #clock-cells = <0>; }; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; wlan_ce_mem: memory@4cd000 { no-map; reg = <0x0 0x004cd000 0x0 0x1000>; }; hyp_mem: memory@80000000 { reg = <0x0 0x80000000 0x0 0x600000>; no-map; }; xbl_mem: memory@80600000 { reg = <0x0 0x80600000 0x0 0x200000>; no-map; }; aop_mem: memory@80800000 { reg = <0x0 0x80800000 0x0 0x60000>; no-map; }; aop_cmd_db_mem: memory@80860000 { reg = <0x0 0x80860000 0x0 0x20000>; compatible = "qcom,cmd-db"; no-map; }; reserved_xbl_uefi_log: memory@80880000 { reg = <0x0 0x80884000 0x0 0x10000>; no-map; }; sec_apps_mem: memory@808ff000 { reg = <0x0 0x808ff000 0x0 0x1000>; no-map; }; smem_mem: memory@80900000 { reg = <0x0 0x80900000 0x0 0x200000>; no-map; }; cpucp_mem: memory@80b00000 { no-map; reg = <0x0 0x80b00000 0x0 0x100000>; }; wlan_fw_mem: memory@80c00000 { reg = <0x0 0x80c00000 0x0 0xc00000>; no-map; }; video_mem: memory@8b200000 { reg = <0x0 0x8b200000 0x0 0x500000>; no-map; }; ipa_fw_mem: memory@8b700000 { reg = <0 0x8b700000 0 0x10000>; no-map; }; rmtfs_mem: memory@9c900000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0x9c900000 0x0 0x280000>; no-map; qcom,client-id = <1>; qcom,vmid = <15>; }; }; cpus { #address-cells = <2>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; }; }; }; CPU1: cpu@100 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU2: cpu@200 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU3: cpu@300 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU4: cpu@400 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU5: cpu@500 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU6: cpu@600 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; CPU7: cpu@700 { device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; clocks = <&cpufreq_hw 2>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; operating-points-v2 = <&cpu7_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; next-level-cache = <&L3_0>; }; }; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; core4 { cpu = <&CPU4>; }; core5 { cpu = <&CPU5>; }; core6 { cpu = <&CPU6>; }; core7 { cpu = <&CPU7>; }; }; }; idle-states { entry-method = "psci"; LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "little-power-down"; arm,psci-suspend-param = <0x40000003>; entry-latency-us = <549>; exit-latency-us = <901>; min-residency-us = <1774>; local-timer-stop; }; LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "little-rail-power-down"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <702>; exit-latency-us = <915>; min-residency-us = <4001>; local-timer-stop; }; BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "big-power-down"; arm,psci-suspend-param = <0x40000003>; entry-latency-us = <523>; exit-latency-us = <1244>; min-residency-us = <2207>; local-timer-stop; }; BIG_CPU_SLEEP_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "big-rail-power-down"; arm,psci-suspend-param = <0x40000004>; entry-latency-us = <526>; exit-latency-us = <1854>; min-residency-us = <5555>; local-timer-stop; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; idle-state-name = "cluster-power-down"; arm,psci-suspend-param = <0x40003444>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9926>; local-timer-stop; }; }; }; cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; cpu0_opp_300mhz: opp-300000000 { opp-hz = /bits/ 64 <300000000>; opp-peak-kBps = <800000 9600000>; }; cpu0_opp_691mhz: opp-691200000 { opp-hz = /bits/ 64 <691200000>; opp-peak-kBps = <800000 17817600>; }; cpu0_opp_806mhz: opp-806400000 { opp-hz = /bits/ 64 <806400000>; opp-peak-kBps = <800000 20889600>; }; cpu0_opp_941mhz: opp-940800000 { opp-hz = /bits/ 64 <940800000>; opp-peak-kBps = <1804000 24576000>; }; cpu0_opp_1152mhz: opp-1152000000 { opp-hz = /bits/ 64 <1152000000>; opp-peak-kBps = <2188000 27033600>; }; cpu0_opp_1325mhz: opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; opp-peak-kBps = <2188000 33792000>; }; cpu0_opp_1517mhz: opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-peak-kBps = <3072000 38092800>; }; cpu0_opp_1651mhz: opp-1651200000 { opp-hz = /bits/ 64 <1651200000>; opp-peak-kBps = <3072000 41779200>; }; cpu0_opp_1805mhz: opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-peak-kBps = <4068000 48537600>; }; cpu0_opp_1958mhz: opp-1958400000 { opp-hz = /bits/ 64 <1958400000>; opp-peak-kBps = <4068000 48537600>; }; cpu0_opp_2016mhz: opp-2016000000 { opp-hz = /bits/ 64 <2016000000>; opp-peak-kBps = <6220000 48537600>; }; }; cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; cpu4_opp_691mhz: opp-691200000 { opp-hz = /bits/ 64 <691200000>; opp-peak-kBps = <1804000 9600000>; }; cpu4_opp_941mhz: opp-940800000 { opp-hz = /bits/ 64 <940800000>; opp-peak-kBps = <2188000 17817600>; }; cpu4_opp_1229mhz: opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; opp-peak-kBps = <4068000 24576000>; }; cpu4_opp_1344mhz: opp-1344000000 { opp-hz = /bits/ 64 <1344000000>; opp-peak-kBps = <4068000 24576000>; }; cpu4_opp_1517mhz: opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-peak-kBps = <4068000 24576000>; }; cpu4_opp_1651mhz: opp-1651200000 { opp-hz = /bits/ 64 <1651200000>; opp-peak-kBps = <6220000 38092800>; }; cpu4_opp_1901mhz: opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-peak-kBps = <6220000 44851200>; }; cpu4_opp_2054mhz: opp-2054400000 { opp-hz = /bits/ 64 <2054400000>; opp-peak-kBps = <6220000 44851200>; }; cpu4_opp_2112mhz: opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; opp-peak-kBps = <6220000 44851200>; }; cpu4_opp_2131mhz: opp-2131200000 { opp-hz = /bits/ 64 <2131200000>; opp-peak-kBps = <6220000 44851200>; }; cpu4_opp_2208mhz: opp-2208000000 { opp-hz = /bits/ 64 <2208000000>; opp-peak-kBps = <6220000 44851200>; }; cpu4_opp_2400mhz: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-peak-kBps = <8532000 48537600>; }; cpu4_opp_2611mhz: opp-2611200000 { opp-hz = /bits/ 64 <2611200000>; opp-peak-kBps = <8532000 48537600>; }; }; cpu7_opp_table: opp-table-cpu7 { compatible = "operating-points-v2"; opp-shared; cpu7_opp_806mhz: opp-806400000 { opp-hz = /bits/ 64 <806400000>; opp-peak-kBps = <1804000 9600000>; }; cpu7_opp_1056mhz: opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-peak-kBps = <2188000 17817600>; }; cpu7_opp_1325mhz: opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; opp-peak-kBps = <4068000 24576000>; }; cpu7_opp_1517mhz: opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; opp-peak-kBps = <4068000 24576000>; }; cpu7_opp_1766mhz: opp-1766400000 { opp-hz = /bits/ 64 <1766400000>; opp-peak-kBps = <6220000 38092800>; }; cpu7_opp_1862mhz: opp-1862400000 { opp-hz = /bits/ 64 <1862400000>; opp-peak-kBps = <6220000 38092800>; }; cpu7_opp_2035mhz: opp-2035200000 { opp-hz = /bits/ 64 <2035200000>; opp-peak-kBps = <6220000 38092800>; }; cpu7_opp_2112mhz: opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; opp-peak-kBps = <6220000 44851200>; }; cpu7_opp_2208mhz: opp-2208000000 { opp-hz = /bits/ 64 <2208000000>; opp-peak-kBps = <6220000 44851200>; }; cpu7_opp_2381mhz: opp-2380800000 { opp-hz = /bits/ 64 <2380800000>; opp-peak-kBps = <6832000 44851200>; }; cpu7_opp_2400mhz: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-peak-kBps = <8532000 48537600>; }; cpu7_opp_2515mhz: opp-2515200000 { opp-hz = /bits/ 64 <2515200000>; opp-peak-kBps = <8532000 48537600>; }; cpu7_opp_2707mhz: opp-2707200000 { opp-hz = /bits/ 64 <2707200000>; opp-peak-kBps = <8532000 48537600>; }; cpu7_opp_3014mhz: opp-3014400000 { opp-hz = /bits/ 64 <3014400000>; opp-peak-kBps = <8532000 48537600>; }; }; memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ reg = <0 0x80000000 0 0>; }; firmware { scm: scm { compatible = "qcom,scm-sc7280", "qcom,scm"; }; }; clk_virt: interconnect { compatible = "qcom,sc7280-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupts-extended = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <1>; modem_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; ipa_smp2p_out: ipa-ap-to-modem { qcom,entry-name = "ipa"; #qcom,smem-state-cells = <1>; }; ipa_smp2p_in: ipa-modem-to-ap { qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; }; smp2p-wpss { compatible = "qcom,smp2p"; qcom,smem = <617>, <616>; interrupts-extended = <&ipcc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <13>; wpss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; wpss_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; wlan_smp2p_out: wlan-ap-to-wpss { qcom,entry-name = "wlan"; #qcom,smem-state-cells = <1>; }; wlan_smp2p_in: wlan-wpss-to-ap { qcom,entry-name = "wlan"; interrupt-controller; #interrupt-cells = <2>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; qspi_opp_table: opp-table-qspi { compatible = "operating-points-v2"; opp-75000000 { opp-hz = /bits/ 64 <75000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-150000000 { opp-hz = /bits/ 64 <150000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_nom>; }; }; qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; opp-75000000 { opp-hz = /bits/ 64 <75000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-128000000 { opp-hz = /bits/ 64 <128000000>; required-opps = <&rpmhpd_opp_nom>; }; }; soc: soc@0 { #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0 0x10 0>; dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; gcc: clock-controller@100000 { compatible = "qcom,gcc-sc7280"; reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, <0>, <&pcie1_lane>, <0>, <0>, <0>, <&usb_1_ssphy>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; power-domains = <&rpmhpd SC7280_CX>; }; ipcc: mailbox@408000 { compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; reg = <0 0x00408000 0 0x1000>; interrupts = ; interrupt-controller; #interrupt-cells = <3>; #mbox-cells = <2>; }; qfprom: efuse@784000 { compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0xa20>, <0 0x00780000 0 0xa20>, <0 0x00782000 0 0x120>, <0 0x00786000 0 0x1fff>; clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; clock-names = "core"; power-domains = <&rpmhpd SC7280_MX>; #address-cells = <1>; #size-cells = <1>; gpu_speed_bin: gpu_speed_bin@1e9 { reg = <0x1e9 0x2>; bits = <5 8>; }; }; sdhc_1: mmc@7c4000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; status = "disabled"; reg = <0 0x007c4000 0 0x1000>, <0 0x007c5000 0 0x1000>; reg-names = "hc", "cqhci"; iommus = <&apps_smmu 0xc0 0x0>; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&sdhc1_opp_table>; bus-width = <8>; supports-cqe; dma-coherent; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; resets = <&gcc GCC_SDCC1_BCR>; sdhc1_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1800000 400000>; opp-avg-kBps = <100000 0>; }; opp-384000000 { opp-hz = /bits/ 64 <384000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 1600000>; opp-avg-kBps = <390000 0>; }; }; }; gpi_dma0: dma-controller@900000 { #dma-cells = <3>; compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00900000 0 0x60000>; interrupts = , , , , , , , , , , , ; dma-channels = <12>; dma-channel-mask = <0x7f>; iommus = <&apps_smmu 0x0136 0x0>; status = "disabled"; }; qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; #address-cells = <2>; #size-cells = <2>; ranges; iommus = <&apps_smmu 0x123 0x0>; status = "disabled"; i2c0: i2c@980000 { compatible = "qcom,geni-i2c"; reg = <0 0x00980000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi0: spi@980000 { compatible = "qcom,geni-spi"; reg = <0 0x00980000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart0: serial@980000 { compatible = "qcom,geni-uart"; reg = <0 0x00980000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c1: i2c@984000 { compatible = "qcom,geni-i2c"; reg = <0 0x00984000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi1: spi@984000 { compatible = "qcom,geni-spi"; reg = <0 0x00984000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart1: serial@984000 { compatible = "qcom,geni-uart"; reg = <0 0x00984000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c2: i2c@988000 { compatible = "qcom,geni-i2c"; reg = <0 0x00988000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi2: spi@988000 { compatible = "qcom,geni-spi"; reg = <0 0x00988000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart2: serial@988000 { compatible = "qcom,geni-uart"; reg = <0 0x00988000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0098c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi3: spi@98c000 { compatible = "qcom,geni-spi"; reg = <0 0x0098c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart3: serial@98c000 { compatible = "qcom,geni-uart"; reg = <0 0x0098c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0 0x00990000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi4: spi@990000 { compatible = "qcom,geni-spi"; reg = <0 0x00990000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart4: serial@990000 { compatible = "qcom,geni-uart"; reg = <0 0x00990000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c5: i2c@994000 { compatible = "qcom,geni-i2c"; reg = <0 0x00994000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi5: spi@994000 { compatible = "qcom,geni-spi"; reg = <0 0x00994000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart5: serial@994000 { compatible = "qcom,geni-uart"; reg = <0 0x00994000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c6: i2c@998000 { compatible = "qcom,geni-i2c"; reg = <0 0x00998000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi6: spi@998000 { compatible = "qcom,geni-spi"; reg = <0 0x00998000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart6: serial@998000 { compatible = "qcom,geni-uart"; reg = <0 0x00998000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c7: i2c@99c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0099c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi7: spi@99c000 { compatible = "qcom,geni-spi"; reg = <0 0x0099c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart7: serial@99c000 { compatible = "qcom,geni-uart"; reg = <0 0x0099c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; gpi_dma1: dma-controller@a00000 { #dma-cells = <3>; compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; interrupts = , , , , , , , , , , , ; dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0x56 0x0>; status = "disabled"; }; qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x2000>; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; #address-cells = <2>; #size-cells = <2>; ranges; iommus = <&apps_smmu 0x43 0x0>; status = "disabled"; i2c8: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a80000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi8: spi@a80000 { compatible = "qcom,geni-spi"; reg = <0 0x00a80000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart8: serial@a80000 { compatible = "qcom,geni-uart"; reg = <0 0x00a80000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi9: spi@a84000 { compatible = "qcom,geni-spi"; reg = <0 0x00a84000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart9: serial@a84000 { compatible = "qcom,geni-uart"; reg = <0 0x00a84000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi10: spi@a88000 { compatible = "qcom,geni-spi"; reg = <0 0x00a88000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart10: serial@a88000 { compatible = "qcom,geni-uart"; reg = <0 0x00a88000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi11: spi@a8c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a8c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart11: serial@a8c000 { compatible = "qcom,geni-uart"; reg = <0 0x00a8c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c12: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi12: spi@a90000 { compatible = "qcom,geni-spi"; reg = <0 0x00a90000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart12: serial@a90000 { compatible = "qcom,geni-uart"; reg = <0 0x00a90000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi13: spi@a94000 { compatible = "qcom,geni-spi"; reg = <0 0x00a94000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart13: serial@a94000 { compatible = "qcom,geni-uart"; reg = <0 0x00a94000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c14: i2c@a98000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a98000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi14: spi@a98000 { compatible = "qcom,geni-spi"; reg = <0 0x00a98000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, <&gpi_dma1 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart14: serial@a98000 { compatible = "qcom,geni-uart"; reg = <0 0x00a98000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; i2c15: i2c@a9c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a9c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_data_clk>; interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; power-domains = <&rpmhpd SC7280_CX>; required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; status = "disabled"; }; spi15: spi@a9c000 { compatible = "qcom,geni-spi"; reg = <0 0x00a9c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; interrupts = ; #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, <&gpi_dma1 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; status = "disabled"; }; uart15: serial@a9c000 { compatible = "qcom,geni-uart"; reg = <0 0x00a9c000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; interrupts = ; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; cnoc2: interconnect@1500000 { reg = <0 0x01500000 0 0x1000>; compatible = "qcom,sc7280-cnoc2"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; cnoc3: interconnect@1502000 { reg = <0 0x01502000 0 0x1000>; compatible = "qcom,sc7280-cnoc3"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@1580000 { reg = <0 0x01580000 0 0x4>; compatible = "qcom,sc7280-mc-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1680000 { reg = <0 0x01680000 0 0x15480>; compatible = "qcom,sc7280-system-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sc7280-aggre1-noc"; reg = <0 0x016e0000 0 0x1c080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { reg = <0 0x01700000 0 0x2b080>; compatible = "qcom,sc7280-aggre2-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { reg = <0 0x01740000 0 0x1e080>; compatible = "qcom,sc7280-mmss-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; wifi: wifi@17a10040 { compatible = "qcom,wcn6750-wifi"; reg = <0 0x17a10040 0 0x0>; iommus = <&apps_smmu 0x1c00 0x1>; interrupts = , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; qcom,rproc = <&remoteproc_wpss>; memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; status = "disabled"; qcom,smem-states = <&wlan_smp2p_out 0>; qcom,smem-state-names = "wlan-smp2p-out"; }; pcie1: pci@1c08000 { compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, <0 0x40001000 0 0x1000>, <0 0x40100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; device_type = "pci"; linux,pci-domain = <1>; bus-range = <0x00 0xff>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = , , , , , , , ; interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, <&pcie1_lane>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, <&gcc GCC_DDRSS_PCIE_SF_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; clock-names = "pipe", "pipe_mux", "phy_pipe", "ref", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "tbu", "ddrss_sf_tbu", "aggre0", "aggre1"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; power-domains = <&gcc GCC_PCIE_1_GDSC>; phys = <&pcie1_lane>; phy-names = "pciephy"; pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; dma-coherent; iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; status = "disabled"; }; pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; reg = <0 0x01c0e000 0 0x1c0>; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; clock-names = "aux", "cfg_ahb", "ref", "refgen"; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; status = "disabled"; pcie1_lane: phy@1c0e200 { reg = <0 0x01c0e200 0 0x170>, <0 0x01c0e400 0 0x200>, <0 0x01c0ea00 0 0x1f0>, <0 0x01c0e600 0 0x170>, <0 0x01c0e800 0 0x200>, <0 0x01c0ee00 0 0xf4>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe0"; #phy-cells = <0>; #clock-cells = <0>; clock-output-names = "pcie_1_pipe_clk"; }; }; ipa: ipa@1e40000 { compatible = "qcom,sc7280-ipa"; iommus = <&apps_smmu 0x480 0x0>, <&apps_smmu 0x482 0x0>; reg = <0 0x01e40000 0 0x8000>, <0 0x01e50000 0 0x4ad0>, <0 0x01e04000 0 0x23000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", "gsi", "ipa-clock-query", "ipa-setup-ready"; clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; interconnect-names = "memory", "config"; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; status = "disabled"; }; tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; #hwlock-cells = <1>; }; tcsr_1: syscon@1f60000 { compatible = "qcom,sc7280-tcsr", "syscon"; reg = <0 0x01f60000 0 0x20000>; }; tcsr_2: syscon@1fc0000 { compatible = "qcom,sc7280-tcsr", "syscon"; reg = <0 0x01fc0000 0 0x30000>; }; lpasscc: lpasscc@3000000 { compatible = "qcom,sc7280-lpasscc"; reg = <0 0x03000000 0 0x40>, <0 0x03c04000 0 0x4>; reg-names = "qdsp6ss", "top_cc"; clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names = "iface"; #clock-cells = <1>; status = "reserved"; /* Owned by ADSP firmware */ }; lpass_rx_macro: codec@3200000 { compatible = "qcom,sc7280-lpass-rx-macro"; reg = <0 0x03200000 0 0x1000>; pinctrl-names = "default"; pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, <&lpass_va_macro>; clock-names = "mclk", "npl", "fsgen"; power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; power-domain-names = "macro", "dcodec"; #clock-cells = <0>; #sound-dai-cells = <1>; status = "disabled"; }; swr0: soundwire@3210000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03210000 0 0x2000>; interrupts = ; clocks = <&lpass_rx_macro>; clock-names = "iface"; qcom,din-ports = <0>; qcom,dout-ports = <5>; resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; reset-names = "swr_audio_cgcr"; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; status = "disabled"; }; lpass_tx_macro: codec@3220000 { compatible = "qcom,sc7280-lpass-tx-macro"; reg = <0 0x03220000 0 0x1000>; pinctrl-names = "default"; pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, <&lpass_va_macro>; clock-names = "mclk", "npl", "fsgen"; power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; power-domain-names = "macro", "dcodec"; #clock-cells = <0>; #sound-dai-cells = <1>; status = "disabled"; }; swr1: soundwire@3230000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03230000 0 0x2000>; interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; clocks = <&lpass_tx_macro>; clock-names = "iface"; qcom,din-ports = <3>; qcom,dout-ports = <0>; resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; reset-names = "swr_audio_cgcr"; qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; status = "disabled"; }; lpass_audiocc: clock-controller@3300000 { compatible = "qcom,sc7280-lpassaudiocc"; reg = <0 0x03300000 0 0x30000>, <0 0x032a9000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; }; lpass_va_macro: codec@3370000 { compatible = "qcom,sc7280-lpass-va-macro"; reg = <0 0x03370000 0 0x1000>; pinctrl-names = "default"; pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; clock-names = "mclk"; power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; power-domain-names = "macro", "dcodec"; #clock-cells = <0>; #sound-dai-cells = <1>; status = "disabled"; }; lpass_aon: clock-controller@3380000 { compatible = "qcom,sc7280-lpassaoncc"; reg = <0 0x03380000 0 0x30000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&lpass_core LPASS_CORE_CC_CORE_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; #clock-cells = <1>; #power-domain-cells = <1>; status = "reserved"; /* Owned by ADSP firmware */ }; lpass_core: clock-controller@3900000 { compatible = "qcom,sc7280-lpasscorecc"; reg = <0 0x03900000 0 0x50000>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; #clock-cells = <1>; #power-domain-cells = <1>; status = "reserved"; /* Owned by ADSP firmware */ }; lpass_cpu: audio@3987000 { compatible = "qcom,sc7280-lpass-cpu"; reg = <0 0x03987000 0 0x68000>, <0 0x03b00000 0 0x29000>, <0 0x03260000 0 0xc000>, <0 0x03280000 0 0x29000>, <0 0x03340000 0 0x29000>, <0 0x0336c000 0 0x3000>; reg-names = "lpass-hdmiif", "lpass-lpaif", "lpass-rxtx-cdc-dma-lpm", "lpass-rxtx-lpaif", "lpass-va-lpaif", "lpass-va-cdc-dma-lpm"; iommus = <&apps_smmu 0x1820 0>, <&apps_smmu 0x1821 0>, <&apps_smmu 0x1832 0>; power-domains = <&rpmhpd SC7280_LCX>; power-domain-names = "lcx"; required-opps = <&rpmhpd_opp_nom>; clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; clock-names = "aon_cc_audio_hm_h", "audio_cc_ext_mclk0", "core_cc_sysnoc_mport_core", "core_cc_ext_if0_ibit", "core_cc_ext_if1_ibit", "audio_cc_codec_mem", "audio_cc_codec_mem0", "audio_cc_codec_mem1", "audio_cc_codec_mem2", "aon_cc_va_mem0"; #sound-dai-cells = <1>; #address-cells = <1>; #size-cells = <0>; interrupts = , , , ; interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi", "lpass-irq-vaif", "lpass-irq-rxtxif"; status = "disabled"; }; lpass_hm: clock-controller@3c00000 { compatible = "qcom,sc7280-lpasshm"; reg = <0 0x03c00000 0 0x28>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; #clock-cells = <1>; #power-domain-cells = <1>; status = "reserved"; /* Owned by ADSP firmware */ }; lpass_ag_noc: interconnect@3c40000 { reg = <0 0x03c40000 0 0xf080>; compatible = "qcom,sc7280-lpass-ag-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; lpass_tlmm: pinctrl@33c0000 { compatible = "qcom,sc7280-lpass-lpi-pinctrl"; reg = <0 0x033c0000 0x0 0x20000>, <0 0x03550000 0x0 0x10000>; qcom,adsp-bypass-mode; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 15>; lpass_dmic01_clk: dmic01-clk-state { pins = "gpio6"; function = "dmic1_clk"; }; lpass_dmic01_data: dmic01-data-state { pins = "gpio7"; function = "dmic1_data"; }; lpass_dmic23_clk: dmic23-clk-state { pins = "gpio8"; function = "dmic2_clk"; }; lpass_dmic23_data: dmic23-data-state { pins = "gpio9"; function = "dmic2_data"; }; lpass_rx_swr_clk: rx-swr-clk-state { pins = "gpio3"; function = "swr_rx_clk"; }; lpass_rx_swr_data: rx-swr-data-state { pins = "gpio4", "gpio5"; function = "swr_rx_data"; }; lpass_tx_swr_clk: tx-swr-clk-state { pins = "gpio0"; function = "swr_tx_clk"; }; lpass_tx_swr_data: tx-swr-data-state { pins = "gpio1", "gpio2", "gpio14"; function = "swr_tx_data"; }; }; gpu: gpu@3d00000 { compatible = "qcom,adreno-635.0", "qcom,adreno"; reg = <0 0x03d00000 0 0x40000>, <0 0x03d9e000 0 0x1000>, <0 0x03d61000 0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; interrupts = ; iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; #cooling-cells = <2>; nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-315000000 { opp-hz = /bits/ 64 <315000000>; opp-level = ; opp-peak-kBps = <1804000>; opp-supported-hw = <0x03>; }; opp-450000000 { opp-hz = /bits/ 64 <450000000>; opp-level = ; opp-peak-kBps = <4068000>; opp-supported-hw = <0x03>; }; /* Only applicable for SKUs which has 550Mhz as Fmax */ opp-550000000-0 { opp-hz = /bits/ 64 <550000000>; opp-level = ; opp-peak-kBps = <8368000>; opp-supported-hw = <0x01>; }; opp-550000000-1 { opp-hz = /bits/ 64 <550000000>; opp-level = ; opp-peak-kBps = <6832000>; opp-supported-hw = <0x02>; }; opp-608000000 { opp-hz = /bits/ 64 <608000000>; opp-level = ; opp-peak-kBps = <8368000>; opp-supported-hw = <0x02>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; opp-level = ; opp-peak-kBps = <8532000>; opp-supported-hw = <0x02>; }; opp-812000000 { opp-hz = /bits/ 64 <812000000>; opp-level = ; opp-peak-kBps = <8532000>; opp-supported-hw = <0x02>; }; opp-840000000 { opp-hz = /bits/ 64 <840000000>; opp-level = ; opp-peak-kBps = <8532000>; opp-supported-hw = <0x02>; }; opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-level = ; opp-peak-kBps = <8532000>; opp-supported-hw = <0x02>; }; }; }; gmu: gmu@3d6a000 { compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; reg = <0 0x03d6a000 0 0x34000>, <0 0x3de0000 0 0x10000>, <0 0x0b290000 0 0x10000>; reg-names = "gmu", "rscc", "gmu_pdc"; interrupts = , ; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_CXO_CLK>, <&gcc GCC_DDRSS_GPU_AXI_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; clock-names = "gmu", "cxo", "axi", "memnoc", "ahb", "hub", "smmu_vote"; power-domains = <&gpucc GPU_CC_CX_GDSC>, <&gpucc GPU_CC_GX_GDSC>; power-domain-names = "cx", "gx"; iommus = <&adreno_smmu 5 0x400>; operating-points-v2 = <&gmu_opp_table>; gmu_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-level = ; }; }; }; gpucc: clock-controller@3d90000 { compatible = "qcom,sc7280-gpucc"; reg = <0 0x03d90000 0 0x9000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; dma@117f000 { compatible = "qcom,sc7280-dcc", "qcom,dcc"; reg = <0x0 0x0117f000 0x0 0x1000>, <0x0 0x01112000 0x0 0x6000>; }; adreno_smmu: iommu@3da0000 { compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x20000>; #iommu-cells = <2>; #global-interrupts = <2>; interrupts = , , , , , , , , , , , ; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>, <&gpucc GPU_CC_HUB_AON_CLK>; clock-names = "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", "gpu_cc_ahb_clk", "gpu_cc_hlos1_vote_gpu_smmu_clk", "gpu_cc_cx_gmu_clk", "gpu_cc_hub_cx_int_clk", "gpu_cc_hub_aon_clk"; power-domains = <&gpucc GPU_CC_CX_GDSC>; dma-coherent; }; remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sc7280-mpss-pas"; reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; reg-names = "qdsp6", "rmb"; interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; power-domains = <&rpmhpd SC7280_CX>, <&rpmhpd SC7280_MSS>; power-domain-names = "cx", "mss"; memory-region = <&mpss_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "modem"; qcom,remote-pid = <1>; }; }; stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { stm_out: endpoint { remote-endpoint = <&funnel0_in7>; }; }; }; }; funnel@6041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06041000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { funnel0_out: endpoint { remote-endpoint = <&merge_funnel_in0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@7 { reg = <7>; funnel0_in7: endpoint { remote-endpoint = <&stm_out>; }; }; }; }; funnel@6042000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06042000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { funnel1_out: endpoint { remote-endpoint = <&merge_funnel_in1>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@4 { reg = <4>; funnel1_in4: endpoint { remote-endpoint = <&apss_merge_funnel_out>; }; }; }; }; funnel@6045000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06045000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { merge_funnel_out: endpoint { remote-endpoint = <&swao_funnel_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; merge_funnel_in0: endpoint { remote-endpoint = <&funnel0_out>; }; }; port@1 { reg = <1>; merge_funnel_in1: endpoint { remote-endpoint = <&funnel1_out>; }; }; }; }; replicator@6046000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0 0x06046000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { replicator_out: endpoint { remote-endpoint = <&etr_in>; }; }; }; in-ports { port { replicator_in: endpoint { remote-endpoint = <&swao_replicator_out>; }; }; }; }; etr@6048000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06048000 0 0x1000>; iommus = <&apps_smmu 0x04c0 0>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,scatter-gather; in-ports { port { etr_in: endpoint { remote-endpoint = <&replicator_out>; }; }; }; }; funnel@6b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06b04000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { swao_funnel_out: endpoint { remote-endpoint = <&etf_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@7 { reg = <7>; swao_funnel_in: endpoint { remote-endpoint = <&merge_funnel_out>; }; }; }; }; etf@6b05000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x06b05000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { etf_out: endpoint { remote-endpoint = <&swao_replicator_in>; }; }; }; in-ports { port { etf_in: endpoint { remote-endpoint = <&swao_funnel_out>; }; }; }; }; replicator@6b06000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0 0x06b06000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; qcom,replicator-loses-context; out-ports { port { swao_replicator_out: endpoint { remote-endpoint = <&replicator_in>; }; }; }; in-ports { port { swao_replicator_in: endpoint { remote-endpoint = <&etf_out>; }; }; }; }; etm@7040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07040000 0 0x1000>; cpu = <&CPU0>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm0_out: endpoint { remote-endpoint = <&apss_funnel_in0>; }; }; }; }; etm@7140000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07140000 0 0x1000>; cpu = <&CPU1>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm1_out: endpoint { remote-endpoint = <&apss_funnel_in1>; }; }; }; }; etm@7240000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07240000 0 0x1000>; cpu = <&CPU2>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm2_out: endpoint { remote-endpoint = <&apss_funnel_in2>; }; }; }; }; etm@7340000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07340000 0 0x1000>; cpu = <&CPU3>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm3_out: endpoint { remote-endpoint = <&apss_funnel_in3>; }; }; }; }; etm@7440000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07440000 0 0x1000>; cpu = <&CPU4>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm4_out: endpoint { remote-endpoint = <&apss_funnel_in4>; }; }; }; }; etm@7540000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07540000 0 0x1000>; cpu = <&CPU5>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm5_out: endpoint { remote-endpoint = <&apss_funnel_in5>; }; }; }; }; etm@7640000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07640000 0 0x1000>; cpu = <&CPU6>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm6_out: endpoint { remote-endpoint = <&apss_funnel_in6>; }; }; }; }; etm@7740000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07740000 0 0x1000>; cpu = <&CPU7>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; arm,coresight-loses-context-with-cpu; qcom,skip-power-up; out-ports { port { etm7_out: endpoint { remote-endpoint = <&apss_funnel_in7>; }; }; }; }; funnel@7800000 { /* APSS Funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x07800000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { apss_funnel_out: endpoint { remote-endpoint = <&apss_merge_funnel_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; apss_funnel_in0: endpoint { remote-endpoint = <&etm0_out>; }; }; port@1 { reg = <1>; apss_funnel_in1: endpoint { remote-endpoint = <&etm1_out>; }; }; port@2 { reg = <2>; apss_funnel_in2: endpoint { remote-endpoint = <&etm2_out>; }; }; port@3 { reg = <3>; apss_funnel_in3: endpoint { remote-endpoint = <&etm3_out>; }; }; port@4 { reg = <4>; apss_funnel_in4: endpoint { remote-endpoint = <&etm4_out>; }; }; port@5 { reg = <5>; apss_funnel_in5: endpoint { remote-endpoint = <&etm5_out>; }; }; port@6 { reg = <6>; apss_funnel_in6: endpoint { remote-endpoint = <&etm6_out>; }; }; port@7 { reg = <7>; apss_funnel_in7: endpoint { remote-endpoint = <&etm7_out>; }; }; }; }; funnel@7810000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x07810000 0 0x1000>; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; out-ports { port { apss_merge_funnel_out: endpoint { remote-endpoint = <&funnel1_in4>; }; }; }; in-ports { port { apss_merge_funnel_in: endpoint { remote-endpoint = <&apss_funnel_out>; }; }; }; }; sdhc_2: mmc@8804000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; status = "disabled"; reg = <0 0x08804000 0 0x1000>; iommus = <&apps_smmu 0x100 0x0>; interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; dma-coherent; qcom,dll-config = <0x0007642c>; resets = <&gcc GCC_SDCC2_BCR>; sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { opp-hz = /bits/ 64 <100000000>; required-opps = <&rpmhpd_opp_low_svs>; opp-peak-kBps = <1800000 400000>; opp-avg-kBps = <100000 0>; }; opp-202000000 { opp-hz = /bits/ 64 <202000000>; required-opps = <&rpmhpd_opp_nom>; opp-peak-kBps = <5400000 1600000>; opp-avg-kBps = <200000 0>; }; }; }; usb_1_hsphy: phy@88e3000 { compatible = "qcom,sc7280-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; usb_2_hsphy: phy@88e4000 { compatible = "qcom,sc7280-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; reg = <0 0x088e4000 0 0x400>; status = "disabled"; #phy-cells = <0>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; usb_1_qmpphy: phy-wrapper@88e9000 { compatible = "qcom,sc7280-qmp-usb3-dp-phy", "qcom,sm8250-qmp-usb3-dp-phy"; reg = <0 0x088e9000 0 0x200>, <0 0x088e8000 0 0x40>, <0 0x088ea000 0 0x200>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; clock-names = "aux", "ref_clk_src", "com_aux"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; usb_1_ssphy: usb3-phy@88e9200 { reg = <0 0x088e9200 0 0x200>, <0 0x088e9400 0 0x200>, <0 0x088e9c00 0 0x400>, <0 0x088e9600 0 0x200>, <0 0x088e9800 0 0x200>, <0 0x088e9a00 0 0x100>; #clock-cells = <0>; #phy-cells = <0>; clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; }; dp_phy: dp-phy@88ea200 { reg = <0 0x088ea200 0 0x200>, <0 0x088ea400 0 0x200>, <0 0x088eaa00 0 0x200>, <0 0x088ea600 0 0x200>, <0 0x088ea800 0 0x200>; #phy-cells = <0>; #clock-cells = <1>; }; }; usb_2: usb@8cf8800 { compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; reg = <0 0x08cf8800 0 0x400>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_SLEEP_CLK>, <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; power-domains = <&gcc GCC_USB30_SEC_GDSC>; required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_SEC_BCR>; interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; interconnect-names = "usb-ddr", "apps-usb"; usb_2_dwc3: usb@8c00000 { compatible = "snps,dwc3"; reg = <0 0x08c00000 0 0xe000>; interrupts = ; iommus = <&apps_smmu 0xa0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_2_hsphy>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; usb-role-switch; port { usb2_role_switch: endpoint { remote-endpoint = <&eud_ep>; }; }; }; }; qspi: spi@88dc000 { compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x1000>; iommus = <&apps_smmu 0x20 0x0>; #address-cells = <1>; #size-cells = <0>; interrupts = ; clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <&gcc GCC_QSPI_CORE_CLK>; clock-names = "iface", "core"; interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QSPI_0 0>; interconnect-names = "qspi-config"; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qspi_opp_table>; status = "disabled"; }; remoteproc_wpss: remoteproc@8a00000 { compatible = "qcom,sc7280-wpss-pil"; reg = <0 0x08a00000 0 0x10000>; interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, <&gcc GCC_WPSS_AHB_CLK>, <&gcc GCC_WPSS_RSCP_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "ahb_bdg", "ahb", "rscp", "xo"; power-domains = <&rpmhpd SC7280_CX>, <&rpmhpd SC7280_MX>; power-domain-names = "cx", "mx"; memory-region = <&wpss_mem>; qcom,qmp = <&aoss_qmp>; qcom,smem-states = <&wpss_smp2p_out 0>; qcom,smem-state-names = "stop"; resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, <&pdc_reset PDC_WPSS_SYNC_RESET>; reset-names = "restart", "pdc_sync"; qcom,halt-regs = <&tcsr_1 0x17000>; status = "disabled"; glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; label = "wpss"; qcom,remote-pid = <13>; }; }; pmu@9091000 { compatible = "qcom,sc7280-llcc-bwmon"; reg = <0 0x09091000 0 0x1000>; interrupts = ; interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; operating-points-v2 = <&llcc_bwmon_opp_table>; llcc_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; opp-0 { opp-peak-kBps = <800000>; }; opp-1 { opp-peak-kBps = <1804000>; }; opp-2 { opp-peak-kBps = <2188000>; }; opp-3 { opp-peak-kBps = <3072000>; }; opp-4 { opp-peak-kBps = <4068000>; }; opp-5 { opp-peak-kBps = <6220000>; }; opp-6 { opp-peak-kBps = <6832000>; }; opp-7 { opp-peak-kBps = <8532000>; }; }; }; pmu@90b6400 { compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x090b6400 0 0x600>; interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; operating-points-v2 = <&cpu_bwmon_opp_table>; cpu_bwmon_opp_table: opp-table { compatible = "operating-points-v2"; opp-0 { opp-peak-kBps = <2400000>; }; opp-1 { opp-peak-kBps = <4800000>; }; opp-2 { opp-peak-kBps = <7456000>; }; opp-3 { opp-peak-kBps = <9600000>; }; opp-4 { opp-peak-kBps = <12896000>; }; opp-5 { opp-peak-kBps = <14928000>; }; opp-6 { opp-peak-kBps = <17056000>; }; }; }; dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; gem_noc: interconnect@9100000 { reg = <0 0x09100000 0 0xe2200>; compatible = "qcom,sc7280-gem-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, <0 0x09600000 0 0x58000>; reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts = ; }; eud: eud@88e0000 { compatible = "qcom,sc7280-eud", "qcom,eud"; reg = <0 0x88e0000 0 0x2000>, <0 0x88e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; eud_ep: endpoint { remote-endpoint = <&usb2_role_switch>; }; }; }; }; nsp_noc: interconnect@a0c0000 { reg = <0 0x0a0c0000 0 0x10000>; compatible = "qcom,sc7280-nsp-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; usb_1: usb@a6f8800 { compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; status = "disabled"; #address-cells = <2>; #size-cells = <2>; ranges; dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; power-domains = <&gcc GCC_USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; interconnect-names = "usb-ddr", "apps-usb"; wakeup-source; usb_1_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xe000>; interrupts = ; iommus = <&apps_smmu 0xe0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; }; }; venus: video-codec@aa00000 { compatible = "qcom,sc7280-venus"; reg = <0 0x0aa00000 0 0xd0600>; interrupts = ; clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, <&videocc VIDEO_CC_MVS0_CORE_CLK>, <&videocc VIDEO_CC_MVS0_AXI_CLK>; clock-names = "core", "bus", "iface", "vcodec_core", "vcodec_bus"; power-domains = <&videocc MVSC_GDSC>, <&videocc MVS0_GDSC>, <&rpmhpd SC7280_CX>; power-domain-names = "venus", "vcodec0", "cx"; operating-points-v2 = <&venus_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "cpu-cfg", "video-mem"; iommus = <&apps_smmu 0x2180 0x20>, <&apps_smmu 0x2184 0x20>; memory-region = <&video_mem>; video-decoder { compatible = "venus-decoder"; }; video-encoder { compatible = "venus-encoder"; }; video-firmware { iommus = <&apps_smmu 0x21a2 0x0>; }; venus_opp_table: opp-table { compatible = "operating-points-v2"; opp-133330000 { opp-hz = /bits/ 64 <133330000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-240000000 { opp-hz = /bits/ 64 <240000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-335000000 { opp-hz = /bits/ 64 <335000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-424000000 { opp-hz = /bits/ 64 <424000000>; required-opps = <&rpmhpd_opp_nom>; }; opp-460000048 { opp-hz = /bits/ 64 <460000048>; required-opps = <&rpmhpd_opp_turbo>; }; }; }; videocc: clock-controller@aaf0000 { compatible = "qcom,sc7280-videocc"; reg = <0 0x0aaf0000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; clock-names = "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; camcc: clock-controller@ad00000 { compatible = "qcom,sc7280-camcc"; reg = <0 0x0ad00000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; dispcc: clock-controller@af00000 { compatible = "qcom,sc7280-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>, <&dp_phy 0>, <&dp_phy 1>, <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk", "edp_phy_pll_link_clk", "edp_phy_pll_vco_div_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; mdss: display-subsystem@ae00000 { compatible = "qcom,sc7280-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; clocks = <&gcc GCC_DISP_AHB_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "iface", "ahb", "core"; interrupts = ; interrupt-controller; #interrupt-cells = <1>; interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "mdp0-mem"; iommus = <&apps_smmu 0x900 0x402>; #address-cells = <2>; #size-cells = <2>; ranges; status = "disabled"; mdss_mdp: display-controller@ae01000 { compatible = "qcom,sc7280-dpu"; reg = <0 0x0ae01000 0 0x8f030>, <0 0x0aeb0000 0 0x2008>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&gcc GCC_DISP_SF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>; clock-names = "bus", "nrt_bus", "iface", "lut", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; assigned-clock-rates = <19200000>, <19200000>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmhpd SC7280_CX>; interrupt-parent = <&mdss>; interrupts = <0>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dpu_intf1_out: endpoint { remote-endpoint = <&mdss_dsi0_in>; }; }; port@1 { reg = <1>; dpu_intf5_out: endpoint { remote-endpoint = <&edp_in>; }; }; port@2 { reg = <2>; dpu_intf0_out: endpoint { remote-endpoint = <&dp_in>; }; }; }; mdp_opp_table: opp-table { compatible = "operating-points-v2"; opp-200000000 { opp-hz = /bits/ 64 <200000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-380000000 { opp-hz = /bits/ 64 <380000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-506666667 { opp-hz = /bits/ 64 <506666667>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss_dsi: dsi@ae94000 { compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, <&gcc GCC_DISP_HF_AXI_CLK>; clock-names = "byte", "byte_intf", "pixel", "core", "iface", "bus"; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7280_CX>; phys = <&mdss_dsi_phy>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; mdss_dsi0_out: endpoint { }; }; }; dsi_opp_table: opp-table { compatible = "operating-points-v2"; opp-187500000 { opp-hz = /bits/ 64 <187500000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-358000000 { opp-hz = /bits/ 64 <358000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; }; }; mdss_dsi_phy: phy@ae94400 { compatible = "qcom,sc7280-dsi-phy-7nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94900 0 0x280>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; #clock-cells = <1>; #phy-cells = <0>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "ref"; status = "disabled"; }; mdss_edp: edp@aea0000 { compatible = "qcom,sc7280-edp"; pinctrl-names = "default"; pinctrl-0 = <&edp_hot_plug_det>; reg = <0 0x0aea0000 0 0x200>, <0 0x0aea0200 0 0x200>, <0 0x0aea0400 0 0xc00>, <0 0x0aea1000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; phys = <&mdss_edp_phy>; phy-names = "dp"; operating-points-v2 = <&edp_opp_table>; power-domains = <&rpmhpd SC7280_CX>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; edp_in: endpoint { remote-endpoint = <&dpu_intf5_out>; }; }; port@1 { reg = <1>; mdss_edp_out: endpoint { }; }; }; edp_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_nom>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; mdss_edp_phy: phy@aec2a00 { compatible = "qcom,sc7280-edp-phy"; reg = <0 0x0aec2a00 0 0x19c>, <0 0x0aec2200 0 0xa0>, <0 0x0aec2600 0 0xa0>, <0 0x0aec2000 0 0x1c0>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_EDP_CLKREF_EN>; clock-names = "aux", "cfg_ahb"; #clock-cells = <1>; #phy-cells = <0>; status = "disabled"; }; mdss_dp: displayport-controller@ae90000 { compatible = "qcom,sc7280-dp"; reg = <0 0x0ae90000 0 0x200>, <0 0x0ae90200 0 0x200>, <0 0x0ae90400 0 0xc00>, <0 0x0ae91000 0 0x400>, <0 0x0ae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; phys = <&dp_phy>; phy-names = "dp"; operating-points-v2 = <&dp_opp_table>; power-domains = <&rpmhpd SC7280_CX>; #sound-dai-cells = <0>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dp_in: endpoint { remote-endpoint = <&dpu_intf0_out>; }; }; port@1 { reg = <1>; mdss_dp_out: endpoint { }; }; }; dp_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { opp-hz = /bits/ 64 <160000000>; required-opps = <&rpmhpd_opp_low_svs>; }; opp-270000000 { opp-hz = /bits/ 64 <270000000>; required-opps = <&rpmhpd_opp_svs>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; required-opps = <&rpmhpd_opp_svs_l1>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; required-opps = <&rpmhpd_opp_nom>; }; }; }; }; pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, <156 716 12>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; }; pdc_reset: reset-controller@b5e0000 { compatible = "qcom,sc7280-pdc-global"; reg = <0 0x0b5e0000 0 0x20000>; #reset-cells = <1>; status = "reserved"; /* Owned by firmware */ }; tsens0: thermal-sensor@c263000 { compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; reg = <0 0x0c263000 0 0x1ff>, /* TM */ <0 0x0c222000 0 0x1ff>; /* SROT */ #qcom,sensors = <15>; interrupts = , ; interrupt-names = "uplow","critical"; #thermal-sensor-cells = <1>; }; tsens1: thermal-sensor@c265000 { compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ <0 0x0c223000 0 0x1ff>; /* SROT */ #qcom,sensors = <12>; interrupts = , ; interrupt-names = "uplow","critical"; #thermal-sensor-cells = <1>; }; aoss_reset: reset-controller@c2a0000 { compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; reg = <0 0x0c2a0000 0 0x31000>; #reset-cells = <1>; }; aoss_qmp: power-management@c300000 { compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; }; sram@c3f0000 { compatible = "qcom,rpmh-stats"; reg = <0 0x0c3f0000 0 0x400>; }; spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, <0 0x0c600000 0 0x2000000>, <0 0x0e600000 0 0x100000>, <0 0x0e700000 0 0xa0000>, <0 0x0c40a000 0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; tlmm: pinctrl@f100000 { compatible = "qcom,sc7280-pinctrl"; reg = <0 0x0f100000 0 0x300000>; interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; dp_hot_plug_det: dp-hot-plug-det-state { pins = "gpio47"; function = "dp_hot"; }; edp_hot_plug_det: edp-hot-plug-det-state { pins = "gpio60"; function = "edp_hot"; }; mi2s0_data0: mi2s0-data0-state { pins = "gpio98"; function = "mi2s0_data0"; }; mi2s0_data1: mi2s0-data1-state { pins = "gpio99"; function = "mi2s0_data1"; }; mi2s0_mclk: mi2s0-mclk-state { pins = "gpio96"; function = "pri_mi2s"; }; mi2s0_sclk: mi2s0-sclk-state { pins = "gpio97"; function = "mi2s0_sck"; }; mi2s0_ws: mi2s0-ws-state { pins = "gpio100"; function = "mi2s0_ws"; }; mi2s1_data0: mi2s1-data0-state { pins = "gpio107"; function = "mi2s1_data0"; }; mi2s1_sclk: mi2s1-sclk-state { pins = "gpio106"; function = "mi2s1_sck"; }; mi2s1_ws: mi2s1-ws-state { pins = "gpio108"; function = "mi2s1_ws"; }; pcie1_clkreq_n: pcie1-clkreq-n-state { pins = "gpio79"; function = "pcie1_clkreqn"; }; qspi_clk: qspi-clk-state { pins = "gpio14"; function = "qspi_clk"; }; qspi_cs0: qspi-cs0-state { pins = "gpio15"; function = "qspi_cs"; }; qspi_cs1: qspi-cs1-state { pins = "gpio19"; function = "qspi_cs"; }; qspi_data0: qspi-data0-state { pins = "gpio12"; function = "qspi_data"; }; qspi_data1: qspi-data1-state { pins = "gpio13"; function = "qspi_data"; }; qspi_data23: qspi-data23-state { pins = "gpio16", "gpio17"; function = "qspi_data"; }; qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins = "gpio0", "gpio1"; function = "qup00"; }; qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup01"; }; qup_i2c2_data_clk: qup-i2c2-data-clk-state { pins = "gpio8", "gpio9"; function = "qup02"; }; qup_i2c3_data_clk: qup-i2c3-data-clk-state { pins = "gpio12", "gpio13"; function = "qup03"; }; qup_i2c4_data_clk: qup-i2c4-data-clk-state { pins = "gpio16", "gpio17"; function = "qup04"; }; qup_i2c5_data_clk: qup-i2c5-data-clk-state { pins = "gpio20", "gpio21"; function = "qup05"; }; qup_i2c6_data_clk: qup-i2c6-data-clk-state { pins = "gpio24", "gpio25"; function = "qup06"; }; qup_i2c7_data_clk: qup-i2c7-data-clk-state { pins = "gpio28", "gpio29"; function = "qup07"; }; qup_i2c8_data_clk: qup-i2c8-data-clk-state { pins = "gpio32", "gpio33"; function = "qup10"; }; qup_i2c9_data_clk: qup-i2c9-data-clk-state { pins = "gpio36", "gpio37"; function = "qup11"; }; qup_i2c10_data_clk: qup-i2c10-data-clk-state { pins = "gpio40", "gpio41"; function = "qup12"; }; qup_i2c11_data_clk: qup-i2c11-data-clk-state { pins = "gpio44", "gpio45"; function = "qup13"; }; qup_i2c12_data_clk: qup-i2c12-data-clk-state { pins = "gpio48", "gpio49"; function = "qup14"; }; qup_i2c13_data_clk: qup-i2c13-data-clk-state { pins = "gpio52", "gpio53"; function = "qup15"; }; qup_i2c14_data_clk: qup-i2c14-data-clk-state { pins = "gpio56", "gpio57"; function = "qup16"; }; qup_i2c15_data_clk: qup-i2c15-data-clk-state { pins = "gpio60", "gpio61"; function = "qup17"; }; qup_spi0_data_clk: qup-spi0-data-clk-state { pins = "gpio0", "gpio1", "gpio2"; function = "qup00"; }; qup_spi0_cs: qup-spi0-cs-state { pins = "gpio3"; function = "qup00"; }; qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { pins = "gpio3"; function = "gpio"; }; qup_spi1_data_clk: qup-spi1-data-clk-state { pins = "gpio4", "gpio5", "gpio6"; function = "qup01"; }; qup_spi1_cs: qup-spi1-cs-state { pins = "gpio7"; function = "qup01"; }; qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { pins = "gpio7"; function = "gpio"; }; qup_spi2_data_clk: qup-spi2-data-clk-state { pins = "gpio8", "gpio9", "gpio10"; function = "qup02"; }; qup_spi2_cs: qup-spi2-cs-state { pins = "gpio11"; function = "qup02"; }; qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { pins = "gpio11"; function = "gpio"; }; qup_spi3_data_clk: qup-spi3-data-clk-state { pins = "gpio12", "gpio13", "gpio14"; function = "qup03"; }; qup_spi3_cs: qup-spi3-cs-state { pins = "gpio15"; function = "qup03"; }; qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { pins = "gpio15"; function = "gpio"; }; qup_spi4_data_clk: qup-spi4-data-clk-state { pins = "gpio16", "gpio17", "gpio18"; function = "qup04"; }; qup_spi4_cs: qup-spi4-cs-state { pins = "gpio19"; function = "qup04"; }; qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { pins = "gpio19"; function = "gpio"; }; qup_spi5_data_clk: qup-spi5-data-clk-state { pins = "gpio20", "gpio21", "gpio22"; function = "qup05"; }; qup_spi5_cs: qup-spi5-cs-state { pins = "gpio23"; function = "qup05"; }; qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { pins = "gpio23"; function = "gpio"; }; qup_spi6_data_clk: qup-spi6-data-clk-state { pins = "gpio24", "gpio25", "gpio26"; function = "qup06"; }; qup_spi6_cs: qup-spi6-cs-state { pins = "gpio27"; function = "qup06"; }; qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { pins = "gpio27"; function = "gpio"; }; qup_spi7_data_clk: qup-spi7-data-clk-state { pins = "gpio28", "gpio29", "gpio30"; function = "qup07"; }; qup_spi7_cs: qup-spi7-cs-state { pins = "gpio31"; function = "qup07"; }; qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { pins = "gpio31"; function = "gpio"; }; qup_spi8_data_clk: qup-spi8-data-clk-state { pins = "gpio32", "gpio33", "gpio34"; function = "qup10"; }; qup_spi8_cs: qup-spi8-cs-state { pins = "gpio35"; function = "qup10"; }; qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { pins = "gpio35"; function = "gpio"; }; qup_spi9_data_clk: qup-spi9-data-clk-state { pins = "gpio36", "gpio37", "gpio38"; function = "qup11"; }; qup_spi9_cs: qup-spi9-cs-state { pins = "gpio39"; function = "qup11"; }; qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { pins = "gpio39"; function = "gpio"; }; qup_spi10_data_clk: qup-spi10-data-clk-state { pins = "gpio40", "gpio41", "gpio42"; function = "qup12"; }; qup_spi10_cs: qup-spi10-cs-state { pins = "gpio43"; function = "qup12"; }; qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { pins = "gpio43"; function = "gpio"; }; qup_spi11_data_clk: qup-spi11-data-clk-state { pins = "gpio44", "gpio45", "gpio46"; function = "qup13"; }; qup_spi11_cs: qup-spi11-cs-state { pins = "gpio47"; function = "qup13"; }; qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { pins = "gpio47"; function = "gpio"; }; qup_spi12_data_clk: qup-spi12-data-clk-state { pins = "gpio48", "gpio49", "gpio50"; function = "qup14"; }; qup_spi12_cs: qup-spi12-cs-state { pins = "gpio51"; function = "qup14"; }; qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { pins = "gpio51"; function = "gpio"; }; qup_spi13_data_clk: qup-spi13-data-clk-state { pins = "gpio52", "gpio53", "gpio54"; function = "qup15"; }; qup_spi13_cs: qup-spi13-cs-state { pins = "gpio55"; function = "qup15"; }; qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { pins = "gpio55"; function = "gpio"; }; qup_spi14_data_clk: qup-spi14-data-clk-state { pins = "gpio56", "gpio57", "gpio58"; function = "qup16"; }; qup_spi14_cs: qup-spi14-cs-state { pins = "gpio59"; function = "qup16"; }; qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { pins = "gpio59"; function = "gpio"; }; qup_spi15_data_clk: qup-spi15-data-clk-state { pins = "gpio60", "gpio61", "gpio62"; function = "qup17"; }; qup_spi15_cs: qup-spi15-cs-state { pins = "gpio63"; function = "qup17"; }; qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { pins = "gpio63"; function = "gpio"; }; qup_uart0_cts: qup-uart0-cts-state { pins = "gpio0"; function = "qup00"; }; qup_uart0_rts: qup-uart0-rts-state { pins = "gpio1"; function = "qup00"; }; qup_uart0_tx: qup-uart0-tx-state { pins = "gpio2"; function = "qup00"; }; qup_uart0_rx: qup-uart0-rx-state { pins = "gpio3"; function = "qup00"; }; qup_uart1_cts: qup-uart1-cts-state { pins = "gpio4"; function = "qup01"; }; qup_uart1_rts: qup-uart1-rts-state { pins = "gpio5"; function = "qup01"; }; qup_uart1_tx: qup-uart1-tx-state { pins = "gpio6"; function = "qup01"; }; qup_uart1_rx: qup-uart1-rx-state { pins = "gpio7"; function = "qup01"; }; qup_uart2_cts: qup-uart2-cts-state { pins = "gpio8"; function = "qup02"; }; qup_uart2_rts: qup-uart2-rts-state { pins = "gpio9"; function = "qup02"; }; qup_uart2_tx: qup-uart2-tx-state { pins = "gpio10"; function = "qup02"; }; qup_uart2_rx: qup-uart2-rx-state { pins = "gpio11"; function = "qup02"; }; qup_uart3_cts: qup-uart3-cts-state { pins = "gpio12"; function = "qup03"; }; qup_uart3_rts: qup-uart3-rts-state { pins = "gpio13"; function = "qup03"; }; qup_uart3_tx: qup-uart3-tx-state { pins = "gpio14"; function = "qup03"; }; qup_uart3_rx: qup-uart3-rx-state { pins = "gpio15"; function = "qup03"; }; qup_uart4_cts: qup-uart4-cts-state { pins = "gpio16"; function = "qup04"; }; qup_uart4_rts: qup-uart4-rts-state { pins = "gpio17"; function = "qup04"; }; qup_uart4_tx: qup-uart4-tx-state { pins = "gpio18"; function = "qup04"; }; qup_uart4_rx: qup-uart4-rx-state { pins = "gpio19"; function = "qup04"; }; qup_uart5_cts: qup-uart5-cts-state { pins = "gpio20"; function = "qup05"; }; qup_uart5_rts: qup-uart5-rts-state { pins = "gpio21"; function = "qup05"; }; qup_uart5_tx: qup-uart5-tx-state { pins = "gpio22"; function = "qup05"; }; qup_uart5_rx: qup-uart5-rx-state { pins = "gpio23"; function = "qup05"; }; qup_uart6_cts: qup-uart6-cts-state { pins = "gpio24"; function = "qup06"; }; qup_uart6_rts: qup-uart6-rts-state { pins = "gpio25"; function = "qup06"; }; qup_uart6_tx: qup-uart6-tx-state { pins = "gpio26"; function = "qup06"; }; qup_uart6_rx: qup-uart6-rx-state { pins = "gpio27"; function = "qup06"; }; qup_uart7_cts: qup-uart7-cts-state { pins = "gpio28"; function = "qup07"; }; qup_uart7_rts: qup-uart7-rts-state { pins = "gpio29"; function = "qup07"; }; qup_uart7_tx: qup-uart7-tx-state { pins = "gpio30"; function = "qup07"; }; qup_uart7_rx: qup-uart7-rx-state { pins = "gpio31"; function = "qup07"; }; qup_uart8_cts: qup-uart8-cts-state { pins = "gpio32"; function = "qup10"; }; qup_uart8_rts: qup-uart8-rts-state { pins = "gpio33"; function = "qup10"; }; qup_uart8_tx: qup-uart8-tx-state { pins = "gpio34"; function = "qup10"; }; qup_uart8_rx: qup-uart8-rx-state { pins = "gpio35"; function = "qup10"; }; qup_uart9_cts: qup-uart9-cts-state { pins = "gpio36"; function = "qup11"; }; qup_uart9_rts: qup-uart9-rts-state { pins = "gpio37"; function = "qup11"; }; qup_uart9_tx: qup-uart9-tx-state { pins = "gpio38"; function = "qup11"; }; qup_uart9_rx: qup-uart9-rx-state { pins = "gpio39"; function = "qup11"; }; qup_uart10_cts: qup-uart10-cts-state { pins = "gpio40"; function = "qup12"; }; qup_uart10_rts: qup-uart10-rts-state { pins = "gpio41"; function = "qup12"; }; qup_uart10_tx: qup-uart10-tx-state { pins = "gpio42"; function = "qup12"; }; qup_uart10_rx: qup-uart10-rx-state { pins = "gpio43"; function = "qup12"; }; qup_uart11_cts: qup-uart11-cts-state { pins = "gpio44"; function = "qup13"; }; qup_uart11_rts: qup-uart11-rts-state { pins = "gpio45"; function = "qup13"; }; qup_uart11_tx: qup-uart11-tx-state { pins = "gpio46"; function = "qup13"; }; qup_uart11_rx: qup-uart11-rx-state { pins = "gpio47"; function = "qup13"; }; qup_uart12_cts: qup-uart12-cts-state { pins = "gpio48"; function = "qup14"; }; qup_uart12_rts: qup-uart12-rts-state { pins = "gpio49"; function = "qup14"; }; qup_uart12_tx: qup-uart12-tx-state { pins = "gpio50"; function = "qup14"; }; qup_uart12_rx: qup-uart12-rx-state { pins = "gpio51"; function = "qup14"; }; qup_uart13_cts: qup-uart13-cts-state { pins = "gpio52"; function = "qup15"; }; qup_uart13_rts: qup-uart13-rts-state { pins = "gpio53"; function = "qup15"; }; qup_uart13_tx: qup-uart13-tx-state { pins = "gpio54"; function = "qup15"; }; qup_uart13_rx: qup-uart13-rx-state { pins = "gpio55"; function = "qup15"; }; qup_uart14_cts: qup-uart14-cts-state { pins = "gpio56"; function = "qup16"; }; qup_uart14_rts: qup-uart14-rts-state { pins = "gpio57"; function = "qup16"; }; qup_uart14_tx: qup-uart14-tx-state { pins = "gpio58"; function = "qup16"; }; qup_uart14_rx: qup-uart14-rx-state { pins = "gpio59"; function = "qup16"; }; qup_uart15_cts: qup-uart15-cts-state { pins = "gpio60"; function = "qup17"; }; qup_uart15_rts: qup-uart15-rts-state { pins = "gpio61"; function = "qup17"; }; qup_uart15_tx: qup-uart15-tx-state { pins = "gpio62"; function = "qup17"; }; qup_uart15_rx: qup-uart15-rx-state { pins = "gpio63"; function = "qup17"; }; sdc1_clk: sdc1-clk-state { pins = "sdc1_clk"; }; sdc1_cmd: sdc1-cmd-state { pins = "sdc1_cmd"; }; sdc1_data: sdc1-data-state { pins = "sdc1_data"; }; sdc1_rclk: sdc1-rclk-state { pins = "sdc1_rclk"; }; sdc1_clk_sleep: sdc1-clk-sleep-state { pins = "sdc1_clk"; drive-strength = <2>; bias-bus-hold; }; sdc1_cmd_sleep: sdc1-cmd-sleep-state { pins = "sdc1_cmd"; drive-strength = <2>; bias-bus-hold; }; sdc1_data_sleep: sdc1-data-sleep-state { pins = "sdc1_data"; drive-strength = <2>; bias-bus-hold; }; sdc1_rclk_sleep: sdc1-rclk-sleep-state { pins = "sdc1_rclk"; drive-strength = <2>; bias-bus-hold; }; sdc2_clk: sdc2-clk-state { pins = "sdc2_clk"; }; sdc2_cmd: sdc2-cmd-state { pins = "sdc2_cmd"; }; sdc2_data: sdc2-data-state { pins = "sdc2_data"; }; sdc2_clk_sleep: sdc2-clk-sleep-state { pins = "sdc2_clk"; drive-strength = <2>; bias-bus-hold; }; sdc2_cmd_sleep: sdc2-cmd-sleep-state { pins = "sdc2_cmd"; drive-strength = <2>; bias-bus-hold; }; sdc2_data_sleep: sdc2-data-sleep-state { pins = "sdc2_data"; drive-strength = <2>; bias-bus-hold; }; }; sram@146a5000 { compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; reg = <0 0x146a5000 0 0x6000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x146a5000 0x6000>; pil-reloc@594c { compatible = "qcom,pil-reloc-info"; reg = <0x594c 0xc8>; }; }; apps_smmu: iommu@15000000 { compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; dma-coherent; interrupts = , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ; }; intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0 0x17a00000 0 0x10000>, /* GICD */ <0 0x17a60000 0 0x100000>; /* GICR * 8 */ interrupts = ; #interrupt-cells = <3>; interrupt-controller; #address-cells = <2>; #size-cells = <2>; ranges; msi-controller@17a40000 { compatible = "arm,gic-v3-its"; reg = <0 0x17a40000 0 0x20000>; msi-controller; #msi-cells = <1>; status = "disabled"; }; }; watchdog: watchdog@17c10000 { compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; reg = <0 0x17c10000 0 0x1000>; clocks = <&sleep_clk>; interrupts = ; status = "reserved"; /* Owned by Gunyah hyp */ }; timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0x20000000>; compatible = "arm,armv7-timer-mem"; reg = <0 0x17c20000 0 0x1000>; frame@17c21000 { frame-number = <0>; interrupts = , ; reg = <0x17c21000 0x1000>, <0x17c22000 0x1000>; }; frame@17c23000 { frame-number = <1>; interrupts = ; reg = <0x17c23000 0x1000>; status = "disabled"; }; frame@17c25000 { frame-number = <2>; interrupts = ; reg = <0x17c25000 0x1000>; status = "disabled"; }; frame@17c27000 { frame-number = <3>; interrupts = ; reg = <0x17c27000 0x1000>; status = "disabled"; }; frame@17c29000 { frame-number = <4>; interrupts = ; reg = <0x17c29000 0x1000>; status = "disabled"; }; frame@17c2b000 { frame-number = <5>; interrupts = ; reg = <0x17c2b000 0x1000>; status = "disabled"; }; frame@17c2d000 { frame-number = <6>; interrupts = ; reg = <0x17c2d000 0x1000>; status = "disabled"; }; }; apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; reg = <0 0x18200000 0 0x10000>, <0 0x18210000 0 0x10000>, <0 0x18220000 0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2"; interrupts = , , ; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , , , ; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; rpmhpd: power-controller { compatible = "qcom,sc7280-rpmhpd"; #power-domain-cells = <1>; operating-points-v2 = <&rpmhpd_opp_table>; rpmhpd_opp_table: opp-table { compatible = "operating-points-v2"; rpmhpd_opp_ret: opp1 { opp-level = ; }; rpmhpd_opp_low_svs: opp2 { opp-level = ; }; rpmhpd_opp_svs: opp3 { opp-level = ; }; rpmhpd_opp_svs_l1: opp4 { opp-level = ; }; rpmhpd_opp_svs_l2: opp5 { opp-level = ; }; rpmhpd_opp_nom: opp6 { opp-level = ; }; rpmhpd_opp_nom_l1: opp7 { opp-level = ; }; rpmhpd_opp_turbo: opp8 { opp-level = ; }; rpmhpd_opp_turbo_l1: opp9 { opp-level = ; }; }; }; rpmhcc: clock-controller { compatible = "qcom,sc7280-rpmh-clk"; clocks = <&xo_board>; clock-names = "xo"; #clock-cells = <1>; }; }; epss_l3: interconnect@18590000 { compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; reg = <0 0x18590000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #interconnect-cells = <1>; }; cpufreq_hw: cpufreq@18591000 { compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, <0 0x18592000 0 0x1000>, <0 0x18593000 0 0x1000>; interrupts = , , ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; #clock-cells = <1>; }; }; thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { cpu0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu0_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu0_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu0_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu1-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { cpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu1_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu1_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu1_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu2-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { cpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu2_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu2_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu2_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu3-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { cpu3_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu3_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu3_alert0>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu3_alert1>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu4-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { cpu4_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu4_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu4_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu4_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu5-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { cpu5_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu5_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu5_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu5_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu6-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { cpu6_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu6_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu6_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu6_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu7-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { cpu7_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu7_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu7_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu7_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu8-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { cpu8_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu8_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu8_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu8_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu8_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu9-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { cpu9_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu9_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu9_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu9_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu9_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu10-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { cpu10_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu10_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu10_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu10_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu10_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; cpu11-thermal { polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { cpu11_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "passive"; }; cpu11_alert1: trip-point1 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; cpu11_crit: cpu-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&cpu11_alert0>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; map1 { trip = <&cpu11_alert1>; cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; aoss0-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { aoss0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; aoss0_crit: aoss0-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; aoss1-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 0>; trips { aoss1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; aoss1_crit: aoss1-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; cpuss0-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { cpuss0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cpuss0_crit: cluster0-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; cpuss1-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { cpuss1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; cpuss1_crit: cluster0-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; gpuss0-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { gpuss0_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; gpuss0_crit: gpuss0-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&gpuss0_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; gpuss1-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { gpuss1_alert0: trip-point0 { temperature = <95000>; hysteresis = <2000>; type = "passive"; }; gpuss1_crit: gpuss1-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; cooling-maps { map0 { trip = <&gpuss1_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; nspss0-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 3>; trips { nspss0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; nspss0_crit: nspss0-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; nspss1-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 4>; trips { nspss1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; nspss1_crit: nspss1-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; video-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 5>; trips { video_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; video_crit: video-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; ddr-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 6>; trips { ddr_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; ddr_crit: ddr-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; mdmss0-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 7>; trips { mdmss0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; mdmss0_crit: mdmss0-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; mdmss1-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 8>; trips { mdmss1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; mdmss1_crit: mdmss1-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; mdmss2-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 9>; trips { mdmss2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; mdmss2_crit: mdmss2-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; mdmss3-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 10>; trips { mdmss3_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; mdmss3_crit: mdmss3-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; camera0-thermal { polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&tsens1 11>; trips { camera0_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; }; camera0_crit: camera0-crit { temperature = <110000>; hysteresis = <0>; type = "critical"; }; }; }; }; timer { compatible = "arm,armv8-timer"; interrupts = , , , ; }; };