1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7280.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 clock-frequency = <76800000>; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 clock-frequency = <32000>; 31 #clock-cells = <0>; 32 }; 33 }; 34 35 reserved-memory { 36 #address-cells = <2>; 37 #size-cells = <2>; 38 ranges; 39 40 aop_mem: memory@80800000 { 41 reg = <0x0 0x80800000 0x0 0x60000>; 42 no-map; 43 }; 44 45 aop_cmd_db_mem: memory@80860000 { 46 reg = <0x0 0x80860000 0x0 0x20000>; 47 compatible = "qcom,cmd-db"; 48 no-map; 49 }; 50 51 cpucp_mem: memory@80b00000 { 52 no-map; 53 reg = <0x0 0x80b00000 0x0 0x100000>; 54 }; 55 }; 56 57 cpus { 58 #address-cells = <2>; 59 #size-cells = <0>; 60 61 CPU0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,kryo"; 64 reg = <0x0 0x0>; 65 enable-method = "psci"; 66 next-level-cache = <&L2_0>; 67 L2_0: l2-cache { 68 compatible = "cache"; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 }; 73 }; 74 }; 75 76 CPU1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,kryo"; 79 reg = <0x0 0x100>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_100>; 82 L2_100: l2-cache { 83 compatible = "cache"; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU2: cpu@200 { 89 device_type = "cpu"; 90 compatible = "arm,kryo"; 91 reg = <0x0 0x200>; 92 enable-method = "psci"; 93 next-level-cache = <&L2_200>; 94 L2_200: l2-cache { 95 compatible = "cache"; 96 next-level-cache = <&L3_0>; 97 }; 98 }; 99 100 CPU3: cpu@300 { 101 device_type = "cpu"; 102 compatible = "arm,kryo"; 103 reg = <0x0 0x300>; 104 enable-method = "psci"; 105 next-level-cache = <&L2_300>; 106 L2_300: l2-cache { 107 compatible = "cache"; 108 next-level-cache = <&L3_0>; 109 }; 110 }; 111 112 CPU4: cpu@400 { 113 device_type = "cpu"; 114 compatible = "arm,kryo"; 115 reg = <0x0 0x400>; 116 enable-method = "psci"; 117 next-level-cache = <&L2_400>; 118 L2_400: l2-cache { 119 compatible = "cache"; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU5: cpu@500 { 125 device_type = "cpu"; 126 compatible = "arm,kryo"; 127 reg = <0x0 0x500>; 128 enable-method = "psci"; 129 next-level-cache = <&L2_500>; 130 L2_500: l2-cache { 131 compatible = "cache"; 132 next-level-cache = <&L3_0>; 133 }; 134 }; 135 136 CPU6: cpu@600 { 137 device_type = "cpu"; 138 compatible = "arm,kryo"; 139 reg = <0x0 0x600>; 140 enable-method = "psci"; 141 next-level-cache = <&L2_600>; 142 L2_600: l2-cache { 143 compatible = "cache"; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 148 CPU7: cpu@700 { 149 device_type = "cpu"; 150 compatible = "arm,kryo"; 151 reg = <0x0 0x700>; 152 enable-method = "psci"; 153 next-level-cache = <&L2_700>; 154 L2_700: l2-cache { 155 compatible = "cache"; 156 next-level-cache = <&L3_0>; 157 }; 158 }; 159 }; 160 161 memory@80000000 { 162 device_type = "memory"; 163 /* We expect the bootloader to fill in the size */ 164 reg = <0 0x80000000 0 0>; 165 }; 166 167 firmware { 168 scm { 169 compatible = "qcom,scm-sc7280", "qcom,scm"; 170 }; 171 }; 172 173 pmu { 174 compatible = "arm,armv8-pmuv3"; 175 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 }; 182 183 soc: soc@0 { 184 #address-cells = <2>; 185 #size-cells = <2>; 186 ranges = <0 0 0 0 0x10 0>; 187 dma-ranges = <0 0 0 0 0x10 0>; 188 compatible = "simple-bus"; 189 190 gcc: clock-controller@100000 { 191 compatible = "qcom,gcc-sc7280"; 192 reg = <0 0x00100000 0 0x1f0000>; 193 clocks = <&rpmhcc RPMH_CXO_CLK>, 194 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 195 <0>, <0>, <0>, <0>, <0>, <0>; 196 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 197 "pcie_0_pipe_clk", "pcie_1_pipe-clk", 198 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 199 "ufs_phy_tx_symbol_0_clk", 200 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 201 #clock-cells = <1>; 202 #reset-cells = <1>; 203 #power-domain-cells = <1>; 204 }; 205 206 qupv3_id_0: geniqup@9c0000 { 207 compatible = "qcom,geni-se-qup"; 208 reg = <0 0x009c0000 0 0x2000>; 209 clock-names = "m-ahb", "s-ahb"; 210 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 211 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 212 #address-cells = <2>; 213 #size-cells = <2>; 214 ranges; 215 status = "disabled"; 216 217 uart5: serial@994000 { 218 compatible = "qcom,geni-debug-uart"; 219 reg = <0 0x00994000 0 0x4000>; 220 clock-names = "se"; 221 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&qup_uart5_default>; 224 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 225 status = "disabled"; 226 }; 227 }; 228 229 pdc: interrupt-controller@b220000 { 230 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 231 reg = <0 0x0b220000 0 0x30000>; 232 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 233 <55 306 4>, <59 312 3>, <62 374 2>, 234 <64 434 2>, <66 438 3>, <69 86 1>, 235 <70 520 54>, <124 609 31>, <155 63 1>, 236 <156 716 12>; 237 #interrupt-cells = <2>; 238 interrupt-parent = <&intc>; 239 interrupt-controller; 240 }; 241 242 spmi_bus: spmi@c440000 { 243 compatible = "qcom,spmi-pmic-arb"; 244 reg = <0 0x0c440000 0 0x1100>, 245 <0 0x0c600000 0 0x2000000>, 246 <0 0x0e600000 0 0x100000>, 247 <0 0x0e700000 0 0xa0000>, 248 <0 0x0c40a000 0 0x26000>; 249 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 250 interrupt-names = "periph_irq"; 251 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 252 qcom,ee = <0>; 253 qcom,channel = <0>; 254 #address-cells = <1>; 255 #size-cells = <1>; 256 interrupt-controller; 257 #interrupt-cells = <4>; 258 }; 259 260 tlmm: pinctrl@f100000 { 261 compatible = "qcom,sc7280-pinctrl"; 262 reg = <0 0x0f100000 0 0x300000>; 263 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 264 gpio-controller; 265 #gpio-cells = <2>; 266 interrupt-controller; 267 #interrupt-cells = <2>; 268 gpio-ranges = <&tlmm 0 0 175>; 269 wakeup-parent = <&pdc>; 270 271 qup_uart5_default: qup-uart5-default { 272 pins = "gpio46", "gpio47"; 273 function = "qup13"; 274 }; 275 }; 276 277 apps_smmu: iommu@15000000 { 278 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 279 reg = <0 0x15000000 0 0x100000>; 280 #iommu-cells = <2>; 281 #global-interrupts = <1>; 282 dma-coherent; 283 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 364 }; 365 366 intc: interrupt-controller@17a00000 { 367 compatible = "arm,gic-v3"; 368 #address-cells = <2>; 369 #size-cells = <2>; 370 ranges; 371 #interrupt-cells = <3>; 372 interrupt-controller; 373 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 374 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 375 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 376 377 gic-its@17a40000 { 378 compatible = "arm,gic-v3-its"; 379 msi-controller; 380 #msi-cells = <1>; 381 reg = <0 0x17a40000 0 0x20000>; 382 status = "disabled"; 383 }; 384 }; 385 386 watchdog@17c10000 { 387 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 388 reg = <0 0x17c10000 0 0x1000>; 389 clocks = <&sleep_clk>; 390 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 391 }; 392 393 timer@17c20000 { 394 #address-cells = <2>; 395 #size-cells = <2>; 396 ranges; 397 compatible = "arm,armv7-timer-mem"; 398 reg = <0 0x17c20000 0 0x1000>; 399 400 frame@17c21000 { 401 frame-number = <0>; 402 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 404 reg = <0 0x17c21000 0 0x1000>, 405 <0 0x17c22000 0 0x1000>; 406 }; 407 408 frame@17c23000 { 409 frame-number = <1>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 reg = <0 0x17c23000 0 0x1000>; 412 status = "disabled"; 413 }; 414 415 frame@17c25000 { 416 frame-number = <2>; 417 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 418 reg = <0 0x17c25000 0 0x1000>; 419 status = "disabled"; 420 }; 421 422 frame@17c27000 { 423 frame-number = <3>; 424 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 425 reg = <0 0x17c27000 0 0x1000>; 426 status = "disabled"; 427 }; 428 429 frame@17c29000 { 430 frame-number = <4>; 431 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 432 reg = <0 0x17c29000 0 0x1000>; 433 status = "disabled"; 434 }; 435 436 frame@17c2b000 { 437 frame-number = <5>; 438 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 439 reg = <0 0x17c2b000 0 0x1000>; 440 status = "disabled"; 441 }; 442 443 frame@17c2d000 { 444 frame-number = <6>; 445 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 446 reg = <0 0x17c2d000 0 0x1000>; 447 status = "disabled"; 448 }; 449 }; 450 451 apps_rsc: rsc@18200000 { 452 compatible = "qcom,rpmh-rsc"; 453 reg = <0 0x18200000 0 0x10000>, 454 <0 0x18210000 0 0x10000>, 455 <0 0x18220000 0 0x10000>; 456 reg-names = "drv-0", "drv-1", "drv-2"; 457 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 460 qcom,tcs-offset = <0xd00>; 461 qcom,drv-id = <2>; 462 qcom,tcs-config = <ACTIVE_TCS 2>, 463 <SLEEP_TCS 3>, 464 <WAKE_TCS 3>, 465 <CONTROL_TCS 1>; 466 467 rpmhcc: clock-controller { 468 compatible = "qcom,sc7280-rpmh-clk"; 469 clocks = <&xo_board>; 470 clock-names = "xo"; 471 #clock-cells = <1>; 472 }; 473 }; 474 }; 475 476 timer { 477 compatible = "arm,armv8-timer"; 478 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 479 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 480 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 481 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 482 }; 483}; 484