Home
last modified time | relevance | path

Searched refs:sdhci_readl (Results 1 – 25 of 29) sorted by relevance

12

/openbmc/u-boot/drivers/mmc/
H A Dxenon_sdhci.c139 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
153 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_init()
166 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
179 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
215 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
221 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
237 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
246 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
250 var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
260 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
[all …]
H A Dkona_sdhci.c33 mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET; in init_kona_mmc_core()
46 (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) & in init_kona_mmc_core()
54 mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
61 mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET); in init_kona_mmc_core()
66 while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { in init_kona_mmc_core()
H A Dsdhci.c46 cmd->response[i] = sdhci_readl(host, in sdhci_cmd_done()
53 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); in sdhci_cmd_done()
64 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); in sdhci_transfer_pio()
86 stat = sdhci_readl(host, SDHCI_INT_STATUS); in sdhci_transfer_data()
93 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) in sdhci_transfer_data()
168 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
267 stat = sdhci_readl(host, SDHCI_INT_STATUS);
294 stat = sdhci_readl(host, SDHCI_INT_STATUS);
336 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
593 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
[all …]
H A Ds5p_sdhci.c41 val = sdhci_readl(host, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
69 ctrl = sdhci_readl(host, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c256 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
295 ret = read_poll_timeout(sdhci_readl, reg, in xenon_emmc_phy_init()
361 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
366 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
422 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); in xenon_emmc_phy_config_tuning()
432 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); in xenon_emmc_phy_config_tuning()
450 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe()
456 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); in xenon_emmc_phy_disable_strobe()
460 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); in xenon_emmc_phy_disable_strobe()
484 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj()
[all …]
H A Dsdhci-of-esdhc.c543 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); in esdhc_of_enable_dma()
595 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_clock_enable()
612 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) in esdhc_clock_enable()
628 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); in esdhc_flush_async_fifo()
637 if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) & in esdhc_flush_async_fifo()
719 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_of_set_clock()
733 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) in esdhc_of_set_clock()
746 temp = sdhci_readl(host, ESDHC_TBCTL); in esdhc_of_set_clock()
748 temp = sdhci_readl(host, ESDHC_SDCLKCTL); in esdhc_of_set_clock()
752 temp = sdhci_readl(host, ESDHC_DLLCFG0); in esdhc_of_set_clock()
[all …]
H A Dsdhci_f_sdh30.c45 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
57 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch()
62 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch()
83 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset()
89 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { in sdhci_f_sdh30_reset()
90 ctl = sdhci_readl(host, F_SDH30_TEST); in sdhci_f_sdh30_reset()
179 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
184 reg = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_f_sdh30_probe()
H A Dsdhci-xenon.c30 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
58 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle()
74 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_acg()
88 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_enable_sdhc()
106 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_disable_sdhc()
117 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran()
127 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
139 reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL); in xenon_retune_setup()
144 reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup()
147 reg = sdhci_readl(host, SDHCI_INT_ENABLE); in xenon_retune_setup()
[all …]
H A Dsdhci-bcm-kona.c56 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
60 while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) { in sdhci_bcm_kona_sd_reset()
68 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
88 val = sdhci_readl(host, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init()
93 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init()
127 val = sdhci_readl(host, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
H A Dsdhci-pci-dwc-mshc.c39 reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock()
47 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
63 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
H A Dsdhci-milbeaut.c65 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
75 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_milbeaut_soft_voltage_switch()
118 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
149 val = sdhci_readl(host, MLB_CR_SET); in sdhci_milbeaut_bridge_init()
181 ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
196 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_vendor_init()
H A Dsdhci-pci-gli.c235 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_on()
252 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_off()
276 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); in gli_set_9750()
277 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
278 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); in gli_set_9750()
279 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750()
280 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); in gli_set_9750()
281 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
364 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750_rx_inv()
436 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_disable_ssc_pll()
[all …]
H A Dsdhci-sprd.c124 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config()
198 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); in sdhci_sprd_set_dll_invert()
242 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
262 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
268 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
275 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
281 if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), in sdhci_sprd_enable_phy_dll()
286 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), in sdhci_sprd_enable_phy_dll()
287 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); in sdhci_sprd_enable_phy_dll()
646 dll_cfg = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_tuning()
H A Dsdhci-tegra.c352 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap()
379 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); in tegra_sdhci_reset()
380 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_reset()
411 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_reset()
430 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad()
448 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset()
493 reg = sdhci_readl(host, in tegra_sdhci_set_padctrl()
557 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
575 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
798 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); in tegra_sdhci_hs400_enhanced_strobe()
[all …]
H A Dsdhci.c59 sdhci_readl(host, SDHCI_DMA_ADDRESS), in sdhci_dumpregs()
65 sdhci_readl(host, SDHCI_ARGUMENT), in sdhci_dumpregs()
68 sdhci_readl(host, SDHCI_PRESENT_STATE), in sdhci_dumpregs()
78 sdhci_readl(host, SDHCI_INT_STATUS)); in sdhci_dumpregs()
80 sdhci_readl(host, SDHCI_INT_ENABLE), in sdhci_dumpregs()
81 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); in sdhci_dumpregs()
86 sdhci_readl(host, SDHCI_CAPABILITIES), in sdhci_dumpregs()
87 sdhci_readl(host, SDHCI_CAPABILITIES_1)); in sdhci_dumpregs()
90 sdhci_readl(host, SDHCI_MAX_CURRENT)); in sdhci_dumpregs()
92 sdhci_readl(host, SDHCI_RESPONSE), in sdhci_dumpregs()
[all …]
H A Dsdhci-pci-o2micro.c94 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_o2_wait_card_detect_stable()
116 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
150 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
164 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in sdhci_o2_get_cd()
183 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_pll_dll_wdt_control()
263 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
737 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_pci_o2_probe_slot()
757 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); in sdhci_pci_o2_probe_slot()
789 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
H A Dsdhci-brcmstb.c50 reg = sdhci_readl(host, SDHCI_VENDOR); in enable_clock_gating()
137 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
139 sdhci_readl(host, SDHCI_BUFFER); in sdhci_brcmstb_cqe_enable()
140 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
H A Dsdhci-of-arasan.c454 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe()
533 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
535 sdhci_readl(host, SDHCI_BUFFER); in sdhci_arasan_cqe_enable()
536 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
902 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
969 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
1018 regval = sdhci_readl(host, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sdcardclk_set_phase()
1051 regval = sdhci_readl(host, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sampleclk_set_phase()
1064 regval = sdhci_readl(host, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sampleclk_set_phase()
H A Dsdhci-of-sparx5.c233 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION)); in sdhci_sparx5_probe()
235 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE)); in sdhci_sparx5_probe()
H A Dsdhci-npcm.c55 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in npcm_sdhci_probe()
H A Dsdhci-of-dwcmshc.c204 vendor = sdhci_readl(host, reg); in dwcmshc_hs400_enhanced_strobe()
242 extra = sdhci_readl(host, reg); in dwcmshc_rk3568_set_clock()
521 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; in dwcmshc_probe()
H A Dsdhci-of-at91.c126 u32 calcr = sdhci_readl(host, SDMMC_CALCR); in sdhci_at91_reset()
131 if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN), in sdhci_at91_reset()
H A Dsdhci-acpi.c318 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && in intel_probe_slot()
319 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) in intel_probe_slot()
984 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); in sdhci_acpi_remove()
H A Dsdhci.h700 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
741 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
/openbmc/u-boot/include/
H A Dsdhci.h308 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
348 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function

12