352 	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);  in tegra_sdhci_set_tap()
379 	misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);  in tegra_sdhci_reset()
380 	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);  in tegra_sdhci_reset()
411 		pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);  in tegra_sdhci_reset()
430 	val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);  in tegra_sdhci_configure_cal_pad()
448 	reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);  in tegra_sdhci_set_pad_autocal_offset()
493 			reg = sdhci_readl(host,  in tegra_sdhci_set_padctrl()
557 	reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);  in tegra_sdhci_pad_autocalib()
575 		reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);  in tegra_sdhci_pad_autocalib()
798 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);  in tegra_sdhci_hs400_enhanced_strobe()
829 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);  in tegra_sdhci_set_dqs_trim()
840 	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);  in tegra_sdhci_hs400_dll_cal()
877 		val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);  in tegra_sdhci_tap_correction()
881 		tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0);  in tegra_sdhci_tap_correction()
948 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);  in tegra_sdhci_post_tuning()
971 		val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1);  in tegra_sdhci_post_tuning()
1041 	val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);  in tegra_sdhci_set_uhs_signaling()
1306 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);  in tegra_sdhci_set_timeout()