| /openbmc/openbmc/poky/meta/conf/machine/include/arm/ |
| H A D | feature-arm-idiv.inc | 1 TUNEVALID[idiv] = "ARM-state integer division instructions"
2 TUNE_CCARGS_MARCH_OPTS .= "${@bb.utils.contains('TUNE_FEATURES', 'idiv', '+idiv', '', d)}"
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| H A D | arch-armv7r.inc | 13 require conf/machine/include/arm/feature-arm-idiv.inc
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| /openbmc/linux/drivers/clk/axs10x/ |
| H A D | i2s_pll_clock.c | 26 unsigned int idiv; member
102 unsigned int idiv, fbdiv, odiv; in i2s_pll_recalc_rate() local
104 idiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_IDIV_REG)); in i2s_pll_recalc_rate()
108 return ((parent_rate / idiv) * fbdiv) / odiv; in i2s_pll_recalc_rate()
144 i2s_pll_write(clk, PLL_IDIV_REG, pll_cfg[i].idiv); in i2s_pll_set_rate()
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| H A D | pll_clock.c | 68 u32 idiv; member
139 u32 idiv, fbdiv, odiv; in axs10x_pll_recalc_rate() local
142 idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV)); in axs10x_pll_recalc_rate()
147 do_div(rate, idiv * odiv); in axs10x_pll_recalc_rate()
183 axs10x_encode_div(pll_cfg[i].idiv, 0)); in axs10x_pll_set_rate()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk-hsdk-cgu.c | 137 const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS]; member
157 const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS]; member
184 u32 idiv; member
349 val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT; in hsdk_pll_set_cfg()
373 u32 idiv, fbdiv, odiv; in pll_get() local
389 idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT); in pll_get()
396 do_div(rate, idiv * odiv); in pll_get()
562 clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft; in axi_clk_set()
563 hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]); in axi_clk_set()
600 clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft; in tun_clk_set()
[all …]
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| H A D | clk_pic32.c | 93 u32 iclk, idiv, odiv, mult; in pic32_get_pll_rate() local
98 idiv = ((v >> 8) & PLLIDIV_MASK) + 1; in pic32_get_pll_rate()
111 return ((plliclk / idiv) * mult) / odiv; in pic32_get_pll_rate()
282 u32 v, idiv, mul; in pic32_get_mpll_rate() local
287 idiv = v & MPLL_IDIV; in pic32_get_mpll_rate()
292 rate = (SYS_POSC_CLK_HZ / idiv) * mul; in pic32_get_mpll_rate()
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| /openbmc/linux/drivers/net/dsa/sja1105/ |
| H A D | sja1105_clocking.c | 46 u64 idiv; member
102 static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv, in sja1105_cgu_idiv_packing() argument
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
118 struct sja1105_cgu_idiv idiv; in sja1105_cgu_idiv_config() local
130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
131 idiv.autoblock = 1; /* Block clk automatically */ in sja1105_cgu_idiv_config()
132 idiv.idiv = factor - 1; /* Divide by 1 or 10 */ in sja1105_cgu_idiv_config()
[all …]
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-hsdk-pll.c | 48 u32 idiv; member
141 val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT; in hsdk_pll_set_cfg()
172 u32 idiv, fbdiv, odiv; in hsdk_pll_recalc_rate() local
188 idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT); in hsdk_pll_recalc_rate()
195 do_div(rate, idiv * odiv); in hsdk_pll_recalc_rate()
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| H A D | clk-versaclock3.c | 292 unsigned long idiv; in vc3_pfd_round_rate() local
302 idiv = DIV_ROUND_UP(*parent_rate, rate); in vc3_pfd_round_rate()
304 if (idiv > 63) in vc3_pfd_round_rate()
307 if (idiv > 31) in vc3_pfd_round_rate()
311 return *parent_rate / idiv; in vc3_pfd_round_rate()
319 unsigned long idiv; in vc3_pfd_set_rate() local
330 idiv = DIV_ROUND_UP(parent_rate, rate); in vc3_pfd_set_rate()
332 if (idiv == 2) { in vc3_pfd_set_rate()
338 div = VC3_PLL1_M_DIV(idiv); in vc3_pfd_set_rate()
340 div = VC3_PLL2_M_DIV(idiv); in vc3_pfd_set_rate()
[all …]
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| H A D | clk-versaclock5.c | 369 unsigned long idiv; in vc5_pfd_round_rate() local
379 idiv = DIV_ROUND_UP(*parent_rate, rate); in vc5_pfd_round_rate()
380 if (idiv > 127) in vc5_pfd_round_rate()
383 return *parent_rate / idiv; in vc5_pfd_round_rate()
391 unsigned long idiv; in vc5_pfd_set_rate() local
405 idiv = DIV_ROUND_UP(parent_rate, rate); in vc5_pfd_set_rate()
408 if (idiv == 2) in vc5_pfd_set_rate()
411 div = VC5_REF_DIVIDER_REF_DIV(idiv); in vc5_pfd_set_rate()
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| H A D | clk-si5351.c | 271 unsigned char idiv; in si5351_clkin_recalc_rate() local
275 idiv = SI5351_CLKIN_DIV_8; in si5351_clkin_recalc_rate()
278 idiv = SI5351_CLKIN_DIV_4; in si5351_clkin_recalc_rate()
281 idiv = SI5351_CLKIN_DIV_2; in si5351_clkin_recalc_rate()
284 idiv = SI5351_CLKIN_DIV_1; in si5351_clkin_recalc_rate()
288 SI5351_CLKIN_DIV_MASK, idiv); in si5351_clkin_recalc_rate()
291 __func__, (1 << (idiv >> 6)), rate); in si5351_clkin_recalc_rate()
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| /openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7r/ |
| H A D | tune-cortexr8.inc | 13 TUNE_FEATURES:tune-cortexr8 = "${TUNE_FEATURES:tune-armv7r-vfpv3d16} cortexr8 idiv"
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| H A D | tune-cortexr7.inc | 13 TUNE_FEATURES:tune-cortexr7 = "${TUNE_FEATURES:tune-armv7r-vfpv3d16} cortexr7 idiv"
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| H A D | tune-cortexr5.inc | 13 TUNE_FEATURES:tune-cortexr5 = "${TUNE_FEATURES:tune-armv7r-vfpv3d16} cortexr5 idiv"
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| /openbmc/linux/drivers/clk/microchip/ |
| H A D | clk-core.c | 585 u32 idiv; /* PLL iclk divider, treated fixed */ member
608 parent_rate /= pll->idiv; in spll_calc_mult_div()
660 pll_in_rate = parent_rate / pll->idiv; in spll_clk_recalc_rate()
749 spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK; in pic32_spll_clk_register()
750 spll->idiv += 1; in pic32_spll_clk_register()
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| /openbmc/qemu/target/microblaze/ |
| H A D | insns.decode | 165 idiv 010010 ..... ..... ..... 000 0000 0000 @typea
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| H A D | translate.c | 480 DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) in DO_TYPEA_CFG() argument
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| /openbmc/qemu/disas/ |
| H A D | microblaze.c | 103 idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, enumerator
310 …ST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x48000000, OPCODE_MASK_H4, idiv, div_inst },
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| /openbmc/linux/drivers/scsi/ |
| H A D | ncr53c8xx.c | 5360 u_char idiv; in ncr_setsync() local
5375 idiv = ((scntl3 >> 4) & 0x7); in ncr_setsync()
5376 if ((sxfer & 0x1f) && idiv) in ncr_setsync()
5377 tp->period = (((sxfer>>5)+4)*div_10M[idiv-1])/np->clock_khz; in ncr_setsync()
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| /openbmc/qemu/tests/tcg/i386/ |
| H A D | test-i386.c | 590 #define OP idiv
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| /openbmc/linux/arch/arm/ |
| H A D | Kconfig | 1225 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
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| /openbmc/linux/arch/x86/kvm/ |
| H A D | emulate.c | 1017 FASTOP1SRC2EX(idiv, idiv_ex);
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| /openbmc/linux/ |
| H A D | opengrok1.0.log | [all...] |