Searched refs:UCR1_TRDYEN (Results 1 – 4 of 4) sorted by relevance
67 #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */ macro
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ macro424 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); in imx_uart_stop_tx()554 ucr1 &= ~UCR1_TRDYEN; in imx_uart_transmit_buffer()746 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); in imx_uart_start_tx()755 ucr1 |= UCR1_TRDYEN; in imx_uart_start_tx()1017 if ((ucr1 & UCR1_TRDYEN) == 0) in imx_uart_int()1620 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | in imx_uart_shutdown()1908 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); in imx_uart_poll_init()2053 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); in imx_uart_console_write()2380 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN); in imx_uart_probe()
26 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ macro
529 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ macro