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Searched refs:writew (Results 1 – 25 of 433) sorted by relevance

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/openbmc/u-boot/board/renesas/sh7753evb/
H A Dsh7753evb.c28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0x0000, &gpio->pdcr); /* SPI0 */ in init_gpio()
32 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
33 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
34 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ in init_gpio()
35 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
36 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
37 writew(0x0000, &gpio->pjcr); /* SCIF4 */ in init_gpio()
[all …]
/openbmc/u-boot/board/renesas/sh7752evb/
H A Dsh7752evb.c28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
32 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
33 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
34 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
35 writew(0x0003, &gpio->pkcr); /* SerMux */ in init_gpio()
36 writew(0x0000, &gpio->plcr); /* SerMux */ in init_gpio()
37 writew(0x0000, &gpio->pmcr); /* RIIC */ in init_gpio()
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-wmt.c143 writew(0, i2c_dev->base + REG_CDR); in wmt_i2c_write()
145 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); in wmt_i2c_write()
151 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write()
155 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write()
167 writew(tcr_val, i2c_dev->base + REG_TCR); in wmt_i2c_write()
172 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write()
196 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write()
202 writew(CR_ENABLE, i2c_dev->base + REG_CR); in wmt_i2c_write()
204 writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base + in wmt_i2c_write()
206 writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR); in wmt_i2c_write()
[all …]
/openbmc/linux/sound/isa/msnd/
H A Dmsnd.c46 writew(PCTODSP_BASED(start), base + JQS_wStart); in snd_msnd_init_queue()
47 writew(PCTODSP_OFFSET(size) - 1, base + JQS_wSize); in snd_msnd_init_queue()
48 writew(0, base + JQS_wHead); in snd_msnd_init_queue()
49 writew(0, base + JQS_wTail); in snd_msnd_init_queue()
266 writew(PCTODSP_BASED(offset), pDAQ); in snd_msnd_DARQ()
269 writew(wTmp, chip->DARQ + JQS_wTail); in snd_msnd_DARQ()
318 writew(chip->play_period_bytes, DAQD + DAQDS_wSize); in snd_msnd_DAPQ()
327 writew(PCTODSP_BASED(offset), DAQD + DAQDS_wStart); in snd_msnd_DAPQ()
339 writew(DAPQ_tail, chip->DAPQ + JQS_wTail); in snd_msnd_DAPQ()
365 writew(PCTODSP_OFFSET(0 * DAQDS__size), chip->DAPQ + JQS_wHead); in snd_msnd_play_reset_queue()
[all …]
/openbmc/linux/arch/arm/mach-spear/
H A Dtime.c75 writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); in spear_clocksource_init()
81 writew(0xFFFF, gpt_base + LOAD(CLKSRC)); in spear_clocksource_init()
86 writew(val, gpt_base + CR(CLKSRC)); in spear_clocksource_init()
99 writew(val, gpt_base + CR(CLKEVT)); in spear_timer_shutdown()
118 writew(val, gpt_base + CR(CLKEVT)); in spear_set_oneshot()
133 writew(period, gpt_base + LOAD(CLKEVT)); in spear_set_periodic()
138 writew(val, gpt_base + CR(CLKEVT)); in spear_set_periodic()
160 writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT)); in clockevent_next_event()
162 writew(cycles, gpt_base + LOAD(CLKEVT)); in clockevent_next_event()
165 writew(val, gpt_base + CR(CLKEVT)); in clockevent_next_event()
[all …]
/openbmc/linux/arch/m68k/coldfire/
H A Dnettel.c109 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); in nettel_smc91x_setmac()
110 writew(macp[0], ioaddr + SMC91xx_BASEMAC); in nettel_smc91x_setmac()
111 writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2); in nettel_smc91x_setmac()
112 writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4); in nettel_smc91x_setmac()
125 writew(0x00ec, MCFSIM_PADDR); in nettel_smc91x_init()
127 writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT); in nettel_smc91x_init()
128 writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR); in nettel_smc91x_init()
132 writew(0x1180, MCFSIM_CSCR3); in nettel_smc91x_init()
/openbmc/linux/drivers/comedi/drivers/
H A Ddt3000.c231 writew(cmd, dev->mmio + DPR_CMD_MBX); in dt3k_send_cmd()
250 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_readsingle()
252 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_readsingle()
253 writew(gain, dev->mmio + DPR_PARAMS(1)); in dt3k_readsingle()
263 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_writesingle()
265 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_writesingle()
266 writew(0, dev->mmio + DPR_PARAMS(1)); in dt3k_writesingle()
267 writew(data, dev->mmio + DPR_PARAMS(2)); in dt3k_writesingle()
298 writew(rear, dev->mmio + DPR_AD_BUF_REAR); in dt3k_ai_empty_fifo()
304 writew(DPR_SUBSYS_AI, dev->mmio + DPR_SUBSYS); in dt3k_ai_cancel()
[all …]
H A Dicp_multi.c120 writew(adc_csr, dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_insn_read()
124 writew(adc_csr | ICP_MULTI_ADC_CSR_ST, in icp_multi_ai_insn_read()
166 writew(dac_csr, dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_insn_write()
177 writew(val, dev->mmio + ICP_MULTI_AO); in icp_multi_ao_insn_write()
180 writew(dac_csr | ICP_MULTI_DAC_CSR_ST, in icp_multi_ao_insn_write()
205 writew(s->state, dev->mmio + ICP_MULTI_DO); in icp_multi_do_insn_bits()
217 writew(0, dev->mmio + ICP_MULTI_INT_EN); in icp_multi_reset()
218 writew(ICP_MULTI_INT_MASK, dev->mmio + ICP_MULTI_INT_STAT); in icp_multi_reset()
225 writew(dac_csr, dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_reset()
228 writew(0, dev->mmio + ICP_MULTI_AO); in icp_multi_reset()
[all …]
H A Dme_daq.c176 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_dio_insn_config()
194 writew((s->state & 0xffff), mmio_porta); in me_dio_insn_bits()
196 writew(((s->state >> 16) & 0xffff), mmio_portb); in me_dio_insn_bits()
251 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
253 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */ in me_ai_insn_read()
257 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
265 writew(val, dev->mmio + ME_AI_FIFO_REG); in me_ai_insn_read()
269 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
289 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
307 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ao_insn_write()
[all …]
/openbmc/u-boot/arch/x86/cpu/queensbay/
H A Dtnc.c128 writew(PIRQE, &rcba->d02ir); in tnc_irq_init()
129 writew(PIRQF, &rcba->d03ir); in tnc_irq_init()
130 writew(PIRQG, &rcba->d27ir); in tnc_irq_init()
131 writew(PIRQH, &rcba->d31ir); in tnc_irq_init()
132 writew(PIRQA, &rcba->d23ir); in tnc_irq_init()
133 writew(PIRQB, &rcba->d24ir); in tnc_irq_init()
134 writew(PIRQC, &rcba->d25ir); in tnc_irq_init()
135 writew(PIRQD, &rcba->d26ir); in tnc_irq_init()
/openbmc/linux/drivers/scsi/arm/
H A Dcumana_1.c64 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
65 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
66 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
67 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
68 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
69 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
70 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
71 v=*laddr++; writew(L(v), dma); writew(H(v), dma); in cumanascsi_pwrite()
/openbmc/linux/drivers/watchdog/
H A Drza_wdt.c79 writew(WTCSR_MAGIC | 0, priv->base + WTCSR); in rza_wdt_start()
83 writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR); in rza_wdt_start()
87 writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR); in rza_wdt_start()
88 writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT); in rza_wdt_start()
89 writew(WTCSR_MAGIC | WTSCR_WT | WTSCR_TME | in rza_wdt_start()
99 writew(WTCSR_MAGIC | 0, priv->base + WTCSR); in rza_wdt_stop()
108 writew(WTCNT_MAGIC | priv->count, priv->base + WTCNT); in rza_wdt_ping()
128 writew(WTCSR_MAGIC | 0, priv->base + WTCSR); in rza_wdt_restart()
132 writew(WRCSR_CLEAR_WOVF, priv->base + WRCSR); in rza_wdt_restart()
138 writew(WRCSR_MAGIC | WRCSR_RSTE, priv->base + WRCSR); in rza_wdt_restart()
[all …]
/openbmc/u-boot/drivers/watchdog/
H A Dimx_watchdog.c22 writew(0x5555, &wdog->wsr); in hw_watchdog_reset()
23 writew(0xaaaa, &wdog->wsr); in hw_watchdog_reset()
42 writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr); in hw_watchdog_init()
44 writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | in hw_watchdog_init()
57 writew(0x5555, &wdog->wsr); in reset_cpu()
58 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ in reset_cpu()
/openbmc/linux/drivers/pwm/
H A Dpwm-ep93xx.c75 writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE); in ep93xx_pwm_apply()
89 writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_INVERT); in ep93xx_pwm_apply()
91 writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_INVERT); in ep93xx_pwm_apply()
98 writew(0x0, ep93xx_pwm->base + EP93XX_PWMx_ENABLE); in ep93xx_pwm_apply()
130 writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT); in ep93xx_pwm_apply()
131 writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE); in ep93xx_pwm_apply()
133 writew(duty_cycles, base + EP93XX_PWMx_DUTY_CYCLE); in ep93xx_pwm_apply()
134 writew(period_cycles, base + EP93XX_PWMx_TERM_COUNT); in ep93xx_pwm_apply()
152 writew(0x1, ep93xx_pwm->base + EP93XX_PWMx_ENABLE); in ep93xx_pwm_apply()
/openbmc/u-boot/board/renesas/sh7763rdp/
H A Dsh7763rdp.c39 writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); in board_init()
43 writew(((dat & ~0xff00) | 0x2400), PSEL1); in board_init()
44 writew(0, PFCR); in board_init()
45 writew(0, PGCR); in board_init()
46 writew(0, PHCR); in board_init()
/openbmc/u-boot/board/renesas/r7780mp/
H A Dr7780mp.c28 writew(0x0, PHCR); in board_init()
42 writew(0x432, FPGA_CFCTL); in ide_set_reset()
44 writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); in ide_set_reset()
46 writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); in ide_set_reset()
48 writew(0x01, FPGA_CFCDINTCLR); in ide_set_reset()
/openbmc/linux/drivers/rtc/
H A Drtc-msc313.c76 writew(reg, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_alarm_irq_enable()
86 writew((seconds & 0xFFFF), priv->rtc_base + REG_RTC_MATCH_VAL_L); in msc313_rtc_set_alarm()
87 writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_MATCH_VAL_H); in msc313_rtc_set_alarm()
105 writew(reg, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_set_enabled()
118 writew(reg | READ_EN_BIT, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_read_time()
139 writew(seconds & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_L); in msc313_rtc_set_time()
140 writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_H); in msc313_rtc_set_time()
144 writew(reg | LOAD_EN_BIT, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_set_time()
173 writew(reg, priv->rtc_base + REG_RTC_CTRL); in msc313_rtc_interrupt()
222 writew(rate & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_L); in msc313_rtc_probe()
[all …]
/openbmc/linux/drivers/input/keyboard/
H A Dimx_keypad.c96 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
100 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
106 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
115 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
137 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
261 writew(reg_val, keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
266 writew(reg_val, keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
279 writew(reg_val, keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
284 writew(reg_val, keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
299 writew(reg_val, keypad->mmio_base + KPSR); in imx_keypad_irq_handler()
[all …]
/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_core.c27 writew(0, &musbr->intrtxe); in musb_start()
28 writew(0, &musbr->intrrxe); in musb_start()
52 writew(fifoaddr >> 3, &musbr->dir##fifoadd); \
85 writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); in musb_configure_ep()
89 writew(csr | MUSB_TXCSR_FLUSHFIFO, in musb_configure_ep()
98 writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); in musb_configure_ep()
102 writew(csr | MUSB_RXCSR_FLUSHFIFO, in musb_configure_ep()
H A Dmusb_hcd.c49 writew(csr, &musbr->txcsr); in write_toggle()
52 writew(csr, &musbr->txcsr); in write_toggle()
54 writew(csr, &musbr->txcsr); in write_toggle()
63 writew(csr, &musbr->rxcsr); in write_toggle()
67 writew(csr, &musbr->rxcsr); in write_toggle()
69 writew(csr, &musbr->rxcsr); in write_toggle()
88 writew(csr, &musbr->txcsr); in check_stall()
96 writew(csr, &musbr->txcsr); in check_stall()
103 writew(csr, &musbr->rxcsr); in check_stall()
125 writew(csr, &musbr->txcsr); in wait_until_ep0_ready()
[all …]
/openbmc/linux/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_i2c.c73 writew(reg & ~TWI_IRQEN, &i2c->regs->twi_ctrl0_stat); in netup_i2c_interrupt()
96 writew(tmp & ~FIFO_IRQEN, &i2c->regs->rx_fifo.stat_ctrl); in netup_i2c_interrupt()
104 writew(tmp & ~FIFO_IRQEN, &i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_interrupt()
123 writew(TWI_SOFT_RESET, &i2c->regs->twi_addr_ctrl1); in netup_i2c_reset()
124 writew(TWI_CLKDIV, &i2c->regs->clkdiv); in netup_i2c_reset()
125 writew(FIFO_RESET, &i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_reset()
126 writew(FIFO_RESET, &i2c->regs->rx_fifo.stat_ctrl); in netup_i2c_reset()
127 writew(0x800, &i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_reset()
128 writew(0x800, &i2c->regs->rx_fifo.stat_ctrl); in netup_i2c_reset()
148 writew(readw(&i2c->regs->tx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_tx()
[all …]
/openbmc/u-boot/board/ronetix/pm9263/
H A Dpm9263.c180 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
181 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ in pm9263_lcd_hw_psram_init()
186 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
188 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
195 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
196 writew(0x5678, PHYS_PSRAM + 2); in pm9263_lcd_hw_psram_init()
206 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
208 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
211 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
212 writew(0x5678, PHYS_PSRAM+2); in pm9263_lcd_hw_psram_init()
/openbmc/linux/drivers/tty/
H A Dmoxa.c549 writew(arg, ofsAddr + FuncArg); in moxafunc()
550 writew(cmd, ofsAddr + FuncCode); in moxafunc()
560 writew(arg, ofsAddr + FuncArg); in moxafuncret()
561 writew(cmd, ofsAddr + FuncCode); in moxafuncret()
812 writew(len - 7168 - 2, baseAddr + C320bapi_len); in moxa_load_320b()
868 writew(len2, baseAddr + loadlen); in moxa_real_load_code()
869 writew(0, baseAddr + key); in moxa_real_load_code()
878 writew(0, baseAddr + loadlen); in moxa_real_load_code()
879 writew(usum, baseAddr + checksum); in moxa_real_load_code()
880 writew(0, baseAddr + key); in moxa_real_load_code()
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dheadc57d.c138 writew(r + ri * i, mem + 0); in headc57d_olut_load_8()
139 writew(g + gi * i, mem + 2); in headc57d_olut_load_8()
140 writew(b + bi * i, mem + 4); in headc57d_olut_load_8()
147 writew(readw(mem - 8), mem + 0); in headc57d_olut_load_8()
148 writew(readw(mem - 6), mem + 2); in headc57d_olut_load_8()
149 writew(readw(mem - 4), mem + 4); in headc57d_olut_load_8()
159 writew(drm_color_lut_extract(in-> red, 16), mem + 0); in headc57d_olut_load()
160 writew(drm_color_lut_extract(in->green, 16), mem + 2); in headc57d_olut_load()
161 writew(drm_color_lut_extract(in-> blue, 16), mem + 4); in headc57d_olut_load()
167 writew(readw(mem - 8), mem + 0); in headc57d_olut_load()
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dreset.c29 writew(0x0000, &regs->wcr); in reset_cpu()
32 writew(0x5555, &regs->wsr); in reset_cpu()
33 writew(0xAAAA, &regs->wsr); in reset_cpu()
36 writew(WCR_WDE, &regs->wcr); in reset_cpu()

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