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Searched refs:vecbase (Results 1 – 25 of 29) sorted by relevance

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/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_sr.S223 test_sr vecbase, 1
225 wsr a2, vecbase
/openbmc/qemu/target/arm/
H A Dcpu.c396 uint32_t vecbase; in arm_cpu_reset_hold() local
456 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80; in arm_cpu_reset_hold()
457 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80; in arm_cpu_reset_hold()
460 vecbase = env->v7m.vecbase[env->v7m.secure]; in arm_cpu_reset_hold()
461 rom = rom_ptr_for_as(cs->as, vecbase, 8); in arm_cpu_reset_hold()
474 initial_msp = ldl_phys(cs->as, vecbase); in arm_cpu_reset_hold()
475 initial_pc = ldl_phys(cs->as, vecbase + 4); in arm_cpu_reset_hold()
H A Dmachine.c518 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU),
708 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU),
H A Dcpu.h543 uint32_t vecbase[M_REG_NUM_BANKS]; member
/openbmc/qemu/target/xtensa/
H A Dcpu.c123 env->sregs[VECBASE] = env->config->vecbase; in xtensa_cpu_reset_hold()
H A Dexc_helper.c149 return vector - env->config->vecbase + env->sregs[VECBASE]; in relocated_vector()
H A Doverlay_tool.h329 .vecbase = XCHAL_VECBASE_RESET_VADDR, \
H A Dcpu.h436 uint32_t vecbase; member
/openbmc/qemu/target/xtensa/core-lx106/
H A Dgdb-config.c.inc64 XTREG( 41,164,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc6247 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
6250 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
6253 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/linux/arch/xtensa/kernel/
H A Dhead.S119 wsr a2, vecbase
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc100 XTREG( 76,304,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc9246 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
9249 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
9252 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc204 XTREG(91, 364, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase,
H A Dxtensa-modules.c.inc11405 { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */,
11408 { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */,
11411 { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */,
12428 return 219; /* xsr.vecbase */
12626 return 217; /* rsr.vecbase */
12763 return 218; /* wsr.vecbase */
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc117 XTREG(92, 368, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase, 0, 0, 0, 0, 0, 0)
H A Dxtensa-modules.c.inc12050 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
12053 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
12056 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc114 XTREG( 79,364,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
/openbmc/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc109 XTREG( 85,340,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc11419 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
11422 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
11425 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc146 XTREG(111,492,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc150 XTREG(111,508,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dgdb-config.c.inc284 XTREG(205,1940,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c1086 return cpu->env.v7m.vecbase[attrs.secure]; in nvic_readl()
1604 cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; in nvic_writel()
/openbmc/qemu/target/arm/tcg/
H A Dm_helper.c662 uint32_t addr = env->v7m.vecbase[targets_secure] + exc * 4; in arm_v7m_load_vector()

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