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Searched refs:v7m (Results 1 – 25 of 30) sorted by relevance

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/openbmc/qemu/target/arm/tcg/
H A Dm_helper.c64 uint32_t value = env->v7m.control[secure]; in arm_v7m_mrs_control()
68 value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; in arm_v7m_mrs_control()
198 !(env->v7m.control[secstate] & 1); in arm_v7m_mmu_idx_for_secstate()
232 env->v7m.sfsr |= R_V7M_SFSR_LSPERR_MASK; in v7m_stack_write()
237 env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK; in v7m_stack_write()
239 env->v7m.sfsr |= R_V7M_SFSR_SFARVALID_MASK; in v7m_stack_write()
240 env->v7m.sfar = addr; in v7m_stack_write()
247 env->v7m.cfsr[secure] |= R_V7M_CFSR_MLSPERR_MASK; in v7m_stack_write()
251 env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK; in v7m_stack_write()
264 env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_LSPERR_MASK; in v7m_stack_write()
[all …]
H A Dtranslate-m-nocp.c133 aspen = load_cpu_field(v7m.fpccr[M_REG_S]); in trans_VSCCLRM()
134 sfpa = load_cpu_field(v7m.control[M_REG_S]); in trans_VSCCLRM()
187 store_cpu_field(tcg_constant_i32(0), v7m.vpr); in trans_VSCCLRM()
296 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); in gen_branch_fpInactive()
297 fpca = load_cpu_field(v7m.control[M_REG_S]); in gen_branch_fpInactive()
389 control = load_cpu_field(v7m.control[M_REG_S]); in gen_M_fp_sysreg_write()
392 store_cpu_field(control, v7m.control[M_REG_S]); in gen_M_fp_sysreg_write()
405 store_cpu_field(tmp, v7m.vpr); in gen_M_fp_sysreg_write()
412 vpr = load_cpu_field(v7m.vpr); in gen_M_fp_sysreg_write()
415 store_cpu_field(vpr, v7m.vpr); in gen_M_fp_sysreg_write()
[all …]
H A Dmeson.build61 arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
62 arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
H A Dhflags.c101 uint32_t ccr = env->v7m.ccr[env->v7m.secure]; in rebuild_hflags_m32()
123 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { in rebuild_hflags_m32()
H A Dmve_helper.c79 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); in mve_element_mask()
81 if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { in mve_element_mask()
84 if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { in mve_element_mask()
88 if (env->v7m.ltpsize < 4 && in mve_element_mask()
89 env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { in mve_element_mask()
96 int masklen = env->regs[14] << env->v7m.ltpsize; in mve_element_mask()
113 uint32_t vpr = env->v7m.vpr; in mve_advance_vpt()
148 env->v7m.vpr = vpr; in mve_advance_vpt()
2617 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \ in DO_VIDUP_ALL()
2639 env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \
[all …]
H A Dtranslate-vfp.c161 tmp = load_cpu_field(v7m.fpccr[M_REG_S]); in gen_update_fp_context()
167 store_cpu_field(tmp, v7m.fpccr[M_REG_S]); in gen_update_fp_context()
180 fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); in gen_update_fp_context()
183 store_cpu_field(tcg_constant_i32(0), v7m.vpr); in gen_update_fp_context()
202 control = load_cpu_field(v7m.control[M_REG_S]); in gen_update_fp_context()
204 store_cpu_field(control, v7m.control[M_REG_S]); in gen_update_fp_context()
H A Dop_helper.c140 && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { in handle_possible_div0_trap()
H A Dtranslate.c6672 store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); in trans_DLS()
6737 store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); in trans_WLS()
6817 tmp = load_cpu_field(v7m.ltpsize); in trans_LE()
6845 TCGv_i32 ltpsize = load_cpu_field(v7m.ltpsize); in trans_LE()
6859 store_cpu_field(tcg_constant_i32(4), v7m.ltpsize); in trans_LE()
6883 store_cpu_field_constant(4, v7m.ltpsize); in trans_LCTP()
H A Dt32.decode395 # Note that the v7m insn overlaps both the normal and banked insn.
H A Dtranslate-mve.c1328 TCGv_i32 vpr = load_cpu_field(v7m.vpr); in gen_vpst()
1349 store_cpu_field(vpr, v7m.vpr); in gen_vpst()
/openbmc/qemu/target/arm/
H A Dmachine.c395 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU),
396 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU),
413 return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK in csselr_vmstate_validate()
414 && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; in csselr_vmstate_validate()
430 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS),
442 VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU),
453 VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
472 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS),
473 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS),
484 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS),
[all …]
H A Dgdbstub.c199 return gdb_get_reg32(buf, env->v7m.vpr); in mve_gdb_get_reg()
212 env->v7m.vpr = ldl_p(buf); in mve_gdb_set_reg()
352 ptr = &env->v7m.msplim[sec]; in m_sysreg_ptr()
355 ptr = &env->v7m.psplim[sec]; in m_sysreg_ptr()
358 ptr = &env->v7m.primask[sec]; in m_sysreg_ptr()
361 ptr = &env->v7m.basepri[sec]; in m_sysreg_ptr()
364 ptr = &env->v7m.faultmask[sec]; in m_sysreg_ptr()
367 ptr = &env->v7m.control[sec]; in m_sysreg_ptr()
396 return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure)); in arm_gdb_get_m_systemreg()
398 return m_sysreg_get(env, buf, reg, env->v7m.secure); in arm_gdb_get_m_systemreg()
H A Dcpu.c405 env->v7m.ltpsize = 4; in arm_cpu_reset_hold()
407 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold()
408 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; in arm_cpu_reset_hold()
412 env->v7m.secure = true; in arm_cpu_reset_hold()
419 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK; in arm_cpu_reset_hold()
427 env->v7m.nsacr = 0xcff; in arm_cpu_reset_hold()
434 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold()
435 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK; in arm_cpu_reset_hold()
438 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK; in arm_cpu_reset_hold()
439 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK; in arm_cpu_reset_hold()
[all …]
H A DKconfig6 # translate.c v7m helpers under ARM_V7M.
H A Dinternals.h1083 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; in v7m_using_psp()
1094 return env->v7m.psplim[env->v7m.secure]; in v7m_sp_limit()
1096 return env->v7m.msplim[env->v7m.secure]; in v7m_sp_limit()
1108 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { in v7m_cpacr_pass()
H A Dcpu.h571 } v7m; member
1553 | env->v7m.exception; in xpsr_read()
2690 return env->v7m.exception != 0; in arm_v7m_is_handler_mode()
2700 !(env->v7m.control[env->v7m.secure] & 1); in arm_current_el()
H A Dvfp_helper.c160 fpcr |= env->v7m.ltpsize << 16; in vfp_get_fpcr()
252 env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, in vfp_set_fpcr_masked()
H A Dhelper.c12462 if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { in fp_exception_el()
12466 if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { in fp_exception_el()
12467 if (!extract32(env->v7m.nsacr, 10, 1)) { in fp_exception_el()
12593 return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); in arm_mmu_idx_el()
12665 if (env->v7m.vpr) { in mve_no_pred()
12668 if (env->v7m.ltpsize < 4) { in mve_no_pred()
12692 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) in cpu_get_tb_cpu_state()
12693 != env->v7m.secure) { in cpu_get_tb_cpu_state()
12697 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && in cpu_get_tb_cpu_state()
12698 (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || in cpu_get_tb_cpu_state()
[all …]
H A Dptw.c236 switch (env->v7m.mpu_ctrl[is_secure] & in regime_translation_disabled()
2372 return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; in pmsav7_use_background_region()
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c188 return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); in exc_targets_secure()
218 (s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) { in exc_group_prio()
347 if (env->v7m.basepri[M_REG_NS] > 0) { in nvic_exec_prio()
348 running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS); in nvic_exec_prio()
351 if (env->v7m.basepri[M_REG_S] > 0) { in nvic_exec_prio()
352 int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S); in nvic_exec_prio()
358 if (env->v7m.primask[M_REG_NS]) { in nvic_exec_prio()
359 if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) { in nvic_exec_prio()
368 if (env->v7m.primask[M_REG_S]) { in nvic_exec_prio()
372 if (env->v7m.faultmask[M_REG_NS]) { in nvic_exec_prio()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,nvic.txt11 "arm,v7m-nvic"
30 compatible = "arm,v7m-nvic";
/openbmc/linux/arch/arm/kernel/
H A DMakefile37 obj-y += entry-v7m.o v7m.o
/openbmc/linux/arch/arm/mm/
H A DMakefile47 obj-$(CONFIG_CPU_CACHE_V7M) += cache-v7m.o
90 obj-$(CONFIG_CPU_V7M) += proc-v7m.o
H A Dproc-v7m.S172 define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
H A Dcache-v7m.S374 subne r3, r2, #1 @ restore r3, corrupted by v7m's dccimvac

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