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Searched refs:tras (Results 1 – 25 of 35) sorted by relevance

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/openbmc/u-boot/board/work-microwave/work_92105/
H A Dwork_92105_spl.c24 .tras = 20833333,
44 .tras = 22222222,
/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A Dddr2_v3s.c20 u8 tras = ns_to_t(45); in mctl_set_timing_params() local
55 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), in mctl_set_timing_params()
H A Dddr3_1333.c20 u8 tras = ns_to_t(38); in mctl_set_timing_params() local
58 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), in mctl_set_timing_params()
H A Dlpddr3_stock.c20 u8 tras = ns_to_t(42); in mctl_set_timing_params() local
54 DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), in mctl_set_timing_params()
/openbmc/u-boot/board/timll/devkit3250/
H A Ddevkit3250_spl.c31 .tras = 23809524,
/openbmc/u-boot/drivers/ram/
H A Dstm32_sdram.c122 u8 tras; member
200 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
210 | timing->tras << FMC_SDTR_TRAS_SHIFT in stm32_sdram_init()
/openbmc/u-boot/include/
H A Dspd.h45 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
H A Dddr_spd.h45 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
107 unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ member
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dddr.c1000 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1058 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1; in mx6_lpddr2_cfg()
1088 debug("tras=%d\n", tras); in mx6_lpddr2_cfg()
1142 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl; in mx6_lpddr2_cfg()
1231 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; in mx6_ddr3_cfg() local
1335 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1; in mx6_ddr3_cfg()
1364 debug("tras=%d\n", tras); in mx6_ddr3_cfg()
1435 (tras << 16) | (1 << 15) /* trpa */ | in mx6_ddr3_cfg()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a83t.c102 u8 tras = ns_to_t(38); in auto_set_timing_para() local
153 tras = ns_to_t(42); in auto_set_timing_para()
170 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
H A Ddram_sun8i_a33.c102 u8 tras = ns_to_t(38); in auto_set_timing_para() local
138 reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0); in auto_set_timing_para()
H A Ddram_sun50i_h6.c196 u8 tras = ns_to_t(42); in mctl_set_timing_lpddr3() local
244 writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras, in mctl_set_timing_lpddr3()
268 writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1), in mctl_set_timing_lpddr3()
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmem.h66 #define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal) \ argument
69 ACTIM_CTRLA_TRAS(tras) | \
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h56 u32 tras; member
H A Dsdram_rk3036.h53 u32 tras; member
250 u32 tras; member
H A Dsdram_rk322x.h89 u32 tras; member
215 u32 tras; member
H A Dddr_rk3368.h57 u32 tras; member
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c42 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Demc.h85 u32 tras; member
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32-fmc.txt21 tras
/openbmc/u-boot/drivers/ddr/fsl/
H A Dddr2_dimm_params.c307 pdimm->tras_ps = spd->tras * 1000; in ddr_compute_dimm_parameters()
H A Dddr1_dimm_params.c308 pdimm->tras_ps = spd->tras * 1000; in ddr_compute_dimm_parameters()
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-lmcx-defs.h1834 uint64_t tras:5; member
1836 uint64_t tras:5;
1858 uint64_t tras:5; member
1860 uint64_t tras:5;
2695 uint64_t tras:5; member
2699 uint64_t tras:5;
2725 uint64_t tras:5; member
2729 uint64_t tras:5;
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun6i.h80 u32 tras; /* 0xf0 */ member
/openbmc/linux/Documentation/translations/sp_SP/
H A Dindex.rst43 gramática, y una cultura tras ella, por lo tanto, la traducción de una

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