Searched refs:timing_reg (Results 1 – 5 of 5) sorted by relevance
285 retval = d->timing_reg; in pmac_ide_read()333 d->timing_reg = val; in pmac_ide_write()362 VMSTATE_UINT32(timing_reg, MACIOIDEState),
89 uint32_t timing_reg; member
507 u32 timing_reg; in aspeed_spi_timing_calibration() local521 timing_reg = readl(&priv->regs->timings + cs); in aspeed_spi_timing_calibration()522 if (timing_reg != 0) in aspeed_spi_timing_calibration()617 timing_reg = readl(&priv->regs->timings); in aspeed_spi_timing_calibration()618 if (timing_reg != 0) in aspeed_spi_timing_calibration()663 timing_reg &= ~(0xfu << hshift); in aspeed_spi_timing_calibration()664 timing_reg |= delay << hshift; in aspeed_spi_timing_calibration()668 debug("Read Timing Compensation set to 0x%08x\n", timing_reg); in aspeed_spi_timing_calibration()669 writel(timing_reg, &priv->regs->timings); in aspeed_spi_timing_calibration()
199 struct timing_reg { struct206 static const struct timing_reg timing_row_reg_fields[] = { argument215 static const struct timing_reg timing_data_reg_fields[] = {226 static const struct timing_reg timing_power_reg_fields[] = {1041 const struct timing_reg *reg; in create_timings_aligned()
303 u16 timing_reg; member590 mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING); in mtk_i2c_init_hw()906 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()929 i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt; in mtk_i2c_set_speed()