spi: aspeed: Use fixed SPI clock frequency at the beginning

The SPI clock frequency in the device tree is
adopted from probe SPI flash stage instead of
after timing calibration.

Signed-off-by: Chin

spi: aspeed: Use fixed SPI clock frequency at the beginning

The SPI clock frequency in the device tree is
adopted from probe SPI flash stage instead of
after timing calibration.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I076cf6476e9014e5fed121054764b8aab17318c4

show more ...

spi: aspeed: Fix bug for lower SPI clock frequency

When SPI clock frequency is lower than 12.5MHz, u-boot
will hang before access SPI flash.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.c

spi: aspeed: Fix bug for lower SPI clock frequency

When SPI clock frequency is lower than 12.5MHz, u-boot
will hang before access SPI flash.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Ifec96ff222e16a5b21541852cbf35cd46959d5fc

show more ...

spi: Add usage example for write protect APIs

Implement the demostration scenario for command filter
and write address filter APIs.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chang

spi: Add usage example for write protect APIs

Implement the demostration scenario for command filter
and write address filter APIs.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Ia1e67aa222925a711e98148ccbf37741d7ae7812

show more ...

spi: aspeed: Add flash write-protect by host ctrl APIs

Add APIs for command filter and address filter, by which
the access permission of the SPI flash regions can be
controller by configuring SPI co

spi: aspeed: Add flash write-protect by host ctrl APIs

Add APIs for command filter and address filter, by which
the access permission of the SPI flash regions can be
controller by configuring SPI controller registers.
Notice, this method cannot avoid physical flash access
from the external HW path.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I9516064ba677b99a6ff7de5b938ba57325049355

show more ...

spi: aspeed: Copy address info from data buf

When erase operation is executed, address information should
be copy from data buf to dedicated address field.

Signed-off-by: Chin-Ting Kuo <chin-ting_k

spi: aspeed: Copy address info from data buf

When erase operation is executed, address information should
be copy from data buf to dedicated address field.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I404fe41e0545894da26b39417453a3f02fcc0613

show more ...

Revert "spi: aspeed: Copy address info from data buf"

This reverts commit 1b244a42196bf2aa90dcc331502427fc78761eb6.

Reason for revert: There exists a bug for address calculation.

Change-Id: I6dfc8

Revert "spi: aspeed: Copy address info from data buf"

This reverts commit 1b244a42196bf2aa90dcc331502427fc78761eb6.

Reason for revert: There exists a bug for address calculation.

Change-Id: I6dfc8a581b5e616a07766ec0042847c3937ce2a0

show more ...

spi: aspeed: Copy address info from data buf

When erase operation is executed, address information should
be copy from data buf to dedicated address field.

Signed-off-by: Chin-Ting Kuo <chin-ting_k

spi: aspeed: Copy address info from data buf

When erase operation is executed, address information should
be copy from data buf to dedicated address field.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Ia8a9ad670236df5244b2c78b592d527348d6d7ea

show more ...

spi: aspeed: Add pure command mode support

When "aspeed-spi-command-mode" property is added in the
device tree, command mode is used to access flash.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@asp

spi: aspeed: Add pure command mode support

When "aspeed-spi-command-mode" property is added in the
device tree, command mode is used to access flash.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I4b844101dfd2bb0588554edd63afe33b8152b23b

show more ...

Merge branch pull request #14 into aspeed-dev-v2019.04

Change-Id: Ib8e72966367a58286d91adc0378072e0591ab571

spi: aspeed: Use "jedec,spi-nor" compatible to count devices

The SoC device trees use the "jedec,spi-nor" compatible property to
describe the flash devices and the board device trees override this
p

spi: aspeed: Use "jedec,spi-nor" compatible to count devices

The SoC device trees use the "jedec,spi-nor" compatible property to
describe the flash devices and the board device trees override this
property with "spi-flash", "sst,w25q256". This comes from the initial
driver which was first written when spi-nor support had not been
merged in U-boot yet.

"jedec,spi-nor" should be preferred since it is used by Linux and the
latest U-boot. Use it to count devices. We will clean up the board
device trees later.

Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220608061455.365123-1-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>

show more ...

spi: aspeed: Fix bug when using 2Gb flash

When the register value of address decoded register
is equal to zero, don't calculate its decoded size
and assign zero to the related array directly.

Signe

spi: aspeed: Fix bug when using 2Gb flash

When the register value of address decoded register
is equal to zero, don't calculate its decoded size
and assign zero to the related array directly.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Ibe781e2e6540e2e4055824c1abd437ee2ffdbb94

show more ...

spi-nor: Porting for S25HL series

Add Cypress S25HL series flash.
Sync code base from u-boot mainline.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I10a0d6d51f2500696b7c0a

spi-nor: Porting for S25HL series

Add Cypress S25HL series flash.
Sync code base from u-boot mainline.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I10a0d6d51f2500696b7c0abc41e935fda90321f0

show more ...

spi: aspeed: Fix resource size calculation method

resource size calculation method is (end - start + 1).

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Id1a667ef7ee5067e1076

spi: aspeed: Fix resource size calculation method

resource size calculation method is (end - start + 1).

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Id1a667ef7ee5067e10766c330266ab5ac4c38a7d

show more ...

spi: apseed: Update timing compensation calculation method

- Use frequency setting property in each flash device node
instead of parent controller itself.
- Find the most suitable timing delay poi

spi: apseed: Update timing compensation calculation method

- Use frequency setting property in each flash device node
instead of parent controller itself.
- Find the most suitable timing delay point which can
provide the most stable flash access operation.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Iac973933d2f95ede647348bdb589752b4f6e2efe

show more ...

spi_nor: aspeed: Update SPI driver

- Fix wrong decoded address configuration for AST2600.
- Always using user mode to read SFDP. Otherwise, wrong
data will be gotten.

Signed-off-by: Chin-Ting Kuo

spi_nor: aspeed: Update SPI driver

- Fix wrong decoded address configuration for AST2600.
- Always using user mode to read SFDP. Otherwise, wrong
data will be gotten.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I790e386d54a33671a59b4bc65121720b4f08f071

show more ...

pfr: Timing calibration disabled support

- Using default SPI clock frequency during early
booting up stage.
- Don't implement timing calibration when PFR is
AST1060 since the maximum SPI clock f

pfr: Timing calibration disabled support

- Using default SPI clock frequency during early
booting up stage.
- Don't implement timing calibration when PFR is
AST1060 since the maximum SPI clock frequency
supported by AST1060 is smaller than 50MHz.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Ifc8fb655152f167a05768ac0f2f632b3632d736d

show more ...

spi-nor: aspeed: Update SPI clock for write process

Using SPI clock frequency defined in dts to write flash.
Originally, the lowest speed, 12.5MHz, is adopted to
write flash.

Signed-off-by: Chin-Ti

spi-nor: aspeed: Update SPI clock for write process

Using SPI clock frequency defined in dts to write flash.
Originally, the lowest speed, 12.5MHz, is adopted to
write flash.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I5acd9a5f1938422b416e26829dfe0ff93fcc3139

show more ...

spi-nor: Add support for Cypress s25hl-t/s25hs-t

Only support 1-1-1 SPI write format.

spi-nor: Porting 2Gb flashes

- Enable SFDP parser on AST2600 defconfig.
- Don't support 1-4-4, 1-2-2 SPI format.

spi-nor: bugfix: Use current spi-nor struct info to access spi-flash

At the early stage of probe a spi-flash, some information of
spi-nor struct should be used to get flash info. For example,
when r

spi-nor: bugfix: Use current spi-nor struct info to access spi-flash

At the early stage of probe a spi-flash, some information of
spi-nor struct should be used to get flash info. For example,
when reading SFDP table, command and dummy cycle should be
known before, but at that time, flash name is still unknown.

show more ...

spi-nor: fixbug: Avoid using freed memory pointed by a spi-nor struct pointer

aspeed_spi_flash_init() is called during load env stage where
FMC0:0 is probed. Before leaving env_sf_load(), spi_flash

spi-nor: fixbug: Avoid using freed memory pointed by a spi-nor struct pointer

aspeed_spi_flash_init() is called during load env stage where
FMC0:0 is probed. Before leaving env_sf_load(), spi_flash
struct pointer is freed, but flash->spi always keep the original
freed memory since flash->init is set.

The solution is assigning flash->spi current spi-nor struct every time.

show more ...

Merge branch 'aspeed-dev-v2019.04' into aspeed-master-v2019.04

Merge branch 'ryan_port' into aspeed-dev-v2019.04

add for ast2400

Merge branch 'spi' into aspeed-dev-v2019.04