| /openbmc/qemu/target/rx/ |
| H A D | translate.c | 272 tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0); in psw_cond()
762 tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); in trans_SCCnd()
766 tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); in trans_SCCnd()
950 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); in rx_neg()
952 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0); in rx_neg()
1291 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); in trans_SHLL_irr()
1292 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); in trans_SHLL_irr()
1294 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); in trans_SHLL_irr()
1321 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); in trans_SHLL_rr()
1322 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); in trans_SHLL_rr()
[all …]
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| /openbmc/qemu/target/sh4/ |
| H A D | translate.c | 749 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_t, cmp1, 0); in _decode_opc()
955 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1173 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s); in _decode_opc()
1280 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1289 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1350 tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1353 tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1357 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1653 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0); in _decode_opc()
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| /openbmc/qemu/include/tcg/ |
| H A D | tcg-op.h | 320 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
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| H A D | tcg-op-common.h | 126 void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
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| /openbmc/qemu/target/ppc/ |
| H A D | translate.c | 1759 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); in gen_op_arith_divw()
1760 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_divw()
1762 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_divw()
1769 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); in gen_op_arith_divw()
1840 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); in gen_op_arith_modw()
1841 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); in gen_op_arith_modw()
1843 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); in gen_op_arith_modw()
4330 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); in gen_setb()
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| /openbmc/qemu/target/ppc/translate/ |
| H A D | vmx-impl.c.inc | 3348 tcg_gen_setcondi_i32(TCG_COND_EQ, t0, a, INT32_MIN); \
3349 tcg_gen_setcondi_i32(TCG_COND_EQ, t1, b, -1); \
3351 tcg_gen_setcondi_i32(TCG_COND_EQ, t1, b, 0); \
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | translate-a64.c | 2007 tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); in trans_XAFLAG()
2204 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); in gen_get_nzcv()
2226 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); in gen_set_nzcv()
8008 tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0); in disas_cc()
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| /openbmc/qemu/tcg/ |
| H A D | tcg-op.c | 543 void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, in tcg_gen_setcondi_i32() function
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| /openbmc/qemu/target/m68k/ |
| H A D | translate.c | 2609 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0); in DISAS_INSN()
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