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Searched refs:tcg_gen_sar_i32 (Results 1 – 12 of 12) sorted by relevance

/openbmc/qemu/include/tcg/
H A Dtcg-op.h315 #define tcg_gen_sar_tl tcg_gen_sar_i32
H A Dtcg-op-common.h178 void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
/openbmc/qemu/target/rx/
H A Dtranslate.c1319 tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); in trans_SHLL_rr()
1365 tcg_gen_shr_i32, tcg_gen_sar_i32, in shiftr_reg()
/openbmc/qemu/tcg/
H A Dtcg-op.c496 void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) in tcg_gen_sar_i32() function
507 tcg_gen_sar_i32(ret, arg1, tcg_constant_i32(arg2)); in tcg_gen_sari_i32()
H A Dtcg-op-gvec.c3309 .fni4 = tcg_gen_sar_i32, in tcg_gen_gvec_sars()
3512 tcg_gen_sar_i32(d, a, t); in tcg_gen_sar_mod_i32()
/openbmc/qemu/target/microblaze/
H A Dtranslate.c350 tcg_gen_sar_i32(out, ina, tmp); in DO_TYPEA()
/openbmc/qemu/target/ppc/translate/
H A Dspe-impl.c.inc184 tcg_gen_sar_i32(ret, arg1, t0);
/openbmc/qemu/target/sh4/
H A Dtranslate.c889 tcg_gen_sar_i32(t2, REG(B11_8), t0); in _decode_opc()
/openbmc/qemu/target/arm/tcg/
H A Dgengvec.c1147 tcg_gen_sar_i32(rval, src, rsh); in gen_sshl_i32()
H A Dtranslate.c560 tcg_gen_sar_i32(dest, t0, tmp1); in GEN_SHIFT()
/openbmc/qemu/target/m68k/
H A Dtranslate.c3937 tcg_gen_sar_i32(QREG_CC_N, tmp, shift); in DISAS_INSN()
/openbmc/qemu/target/xtensa/
H A Dtranslate.c2308 tcg_gen_sar_i32(arg[0].out, arg[1].in, cpu_SR[SAR]); in translate_sra()