/openbmc/qemu/tcg/ |
H A D | tcg-op.c | 764 tcg_gen_movcond_i32(TCG_COND_EQ, ret, arg1, z, arg2, t); in tcg_gen_ctz_i32() 1135 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, in tcg_gen_movcond_i32() function 1396 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); in tcg_gen_smin_i32() 1401 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); in tcg_gen_umin_i32() 1406 tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); in tcg_gen_smax_i32() 1411 tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); in tcg_gen_umax_i32() 3005 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, zero, in tcg_gen_movcond_i64() 3007 tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, zero, in tcg_gen_movcond_i64()
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H A D | tcg-op-ldst.c | 887 tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); in tcg_gen_nonatomic_cmpxchg_i32_int()
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H A D | tcg-op-gvec.c | 2268 tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d); in tcg_gen_usadd_i32() 2310 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d); in tcg_gen_ussub_i32()
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/openbmc/qemu/target/arm/tcg/ |
H A D | gengvec.c | 1030 tcg_gen_movcond_i32(TCG_COND_LTU, dst, lsh, max, lval, zero); in gen_ushl_i32() 1031 tcg_gen_movcond_i32(TCG_COND_LTU, dst, rsh, max, rval, dst); in gen_ushl_i32() 1148 tcg_gen_movcond_i32(TCG_COND_LEU, lval, lsh, max, lval, zero); in gen_sshl_i32() 1149 tcg_gen_movcond_i32(TCG_COND_LT, dst, lsh, zero, rval, lval); in gen_sshl_i32() 1650 tcg_gen_movcond_i32(TCG_COND_LT, d, a, b, d, t); in gen_sabd_i32() 1707 tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, d, t); in gen_uabd_i32()
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H A D | translate-vfp.c | 390 tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, frn, frm); in trans_VSEL() 393 tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, frn, frm); in trans_VSEL() 398 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, frn, frm); in trans_VSEL() 401 tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, frn, frm); in trans_VSEL() 404 tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, dest, frm); in trans_VSEL()
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H A D | translate-m-nocp.c | 541 tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), in gen_M_fp_sysreg_read()
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H A D | translate.c | 548 tcg_gen_movcond_i32(TCG_COND_NE, dest, tmp1, zero, zero, tmpd); \ 6071 tcg_gen_movcond_i32(TCG_COND_NE, qf, t2, t3, one, qf); in op_smlad() 6911 tcg_gen_movcond_i32(TCG_COND_LEU, masklen, in trans_VCTP() 7265 tcg_gen_movcond_i32(c.cond, rn, c.value, tcg_constant_i32(0), rn, rm); in trans_CSEL()
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H A D | translate-sve.c | 2438 tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last); in incr_last_active() 2452 tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last); in wrap_last_active()
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/openbmc/qemu/include/tcg/ |
H A D | tcg-op.h | 370 #define tcg_gen_movcond_tl tcg_gen_movcond_i32
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H A D | tcg-op-common.h | 132 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
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/openbmc/qemu/target/m68k/ |
H A D | translate.c | 3425 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, in shift_reg() 3431 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, in shift_reg() 3471 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V, in shift_reg() 3636 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx); in rotate_x() 3715 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X); in rotate32_x() 3716 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo); in rotate32_x() 3809 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, in DISAS_INSN() 3840 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, in DISAS_INSN() 3872 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, in DISAS_INSN()
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/openbmc/qemu/target/sh4/ |
H A D | translate.c | 777 tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, zero, REG(B7_4), t2); in _decode_opc() 894 tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2); in _decode_opc() 916 tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2); in _decode_opc()
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/openbmc/qemu/target/xtensa/ |
H A D | translate.c | 1835 tcg_gen_movcond_i32(par[0], arg[0].out, in translate_movcond() 1852 tcg_gen_movcond_i32(par[0], in translate_movp() 2217 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_exclusive_val, in translate_s32ex() 6295 tcg_gen_movcond_i32(TCG_COND_NE, in translate_compare_d() 6324 tcg_gen_movcond_i32(TCG_COND_NE, in translate_compare_s() 6507 tcg_gen_movcond_i32(par[0], arg[0].out, in translate_movcond_s() 6537 tcg_gen_movcond_i32(par[0], in translate_movp_s()
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/openbmc/qemu/target/rx/ |
H A D | translate.c | 733 tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, in stcond() 1816 tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], in trans_SAT()
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/openbmc/qemu/target/ppc/ |
H A D | translate.c | 1765 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); in gen_op_arith_divw() 1771 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); in gen_op_arith_divw() 1846 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); in gen_op_arith_modw() 1852 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); in gen_op_arith_modw() 4331 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); in gen_setb()
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/openbmc/qemu/target/microblaze/ |
H A D | translate.c | 1118 tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, in DO_BR()
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/openbmc/qemu/target/sparc/ |
H A D | translate.c | 810 tcg_gen_movcond_i32(TCG_COND_LT, d, v, z, t, r); in gen_op_fpadds32s() 828 tcg_gen_movcond_i32(TCG_COND_LT, d, v, z, t, r); in gen_op_fpsubs32s() 2392 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); in gen_fmovs()
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/openbmc/qemu/target/ppc/translate/ |
H A D | vmx-impl.c.inc | 3339 tcg_gen_movcond_i32(TCG_COND_EQ, b, b, zero, one, b); \ 3354 tcg_gen_movcond_i32(TCG_COND_NE, b, t0, t1, t0, b); \
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/openbmc/qemu/target/mips/tcg/ |
H A D | translate.c | 9216 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2); in gen_sel_s() 9220 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1); in gen_sel_s() 9224 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1); in gen_sel_s()
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/openbmc/qemu/target/i386/tcg/ |
H A D | emit.c.inc | 3797 tcg_gen_movcond_i32(TCG_COND_EQ, decode->cc_op_dynamic, count32, tcg_constant_i32(0),
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