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Searched refs:rs2 (Results 1 – 25 of 60) sorted by relevance

123

/openbmc/linux/arch/riscv/net/
H A Dbpf_jit.h229 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, in rv_r_insn() argument
232 return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_r_insn()
242 static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_s_insn() argument
246 return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_s_insn()
250 static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode) in rv_b_insn() argument
255 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) | in rv_b_insn()
274 static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1, in rv_amo_insn() argument
279 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); in rv_amo_insn()
284 static inline u16 rv_cr_insn(u8 funct4, u8 rd, u8 rs2, u8 op) in rv_cr_insn() argument
286 return (funct4 << 12) | (rd << 7) | (rs2 << 2) | op; in rv_cr_insn()
[all …]
H A Dbpf_jit_comp32.c572 const s8 *rs2 = bpf_get_reg64(src2, tmp2, ctx); in emit_branch_r64() local
587 emit(rv_bne(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
588 emit(rv_bne(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
591 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
592 emit(rv_bltu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
593 emit(rv_bleu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
596 emit(rv_bltu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
597 emit(rv_bgtu(hi(rs1), hi(rs2), NO_JUMP(1)), ctx); in emit_branch_r64()
598 emit(rv_bgeu(lo(rs1), lo(rs2), NO_JUMP(0)), ctx); in emit_branch_r64()
601 emit(rv_bgtu(hi(rs1), hi(rs2), JUMP(2)), ctx); in emit_branch_r64()
[all …]
/openbmc/linux/arch/sparc/kernel/
H A Dvisemul.c140 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
143 if (rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
296 unsigned long orig_rs1, rs1, orig_rs2, rs2, rd_val; in edge() local
301 orig_rs2 = rs2 = fetch_reg(RS2(insn), regs); in edge()
305 rs2 = rs2 & 0xffffffff; in edge()
312 right = edge8_tab[rs2 & 0x7].right; in edge()
317 right = edge8_tab_l[rs2 & 0x7].right; in edge()
323 right = edge16_tab[(rs2 >> 1) & 0x3].right; in edge()
329 right = edge16_tab_l[(rs2 >> 1) & 0x3].right; in edge()
335 right = edge32_tab[(rs2 >> 2) & 0x1].right; in edge()
[all …]
H A Dunaligned_32.c72 static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2, in maybe_flush_windows() argument
75 if(rs2 >= 16 || rs1 >= 16 || rd >= 16) { in maybe_flush_windows()
140 unsigned int rs2 = insn & 0x1f; in compute_effective_address() local
147 maybe_flush_windows(rs1, rs2, rd); in compute_effective_address()
148 return (fetch_reg(rs1, regs) + fetch_reg(rs2, regs)); in compute_effective_address()
156 unsigned int rs2 = insn & 0x1f; in safe_compute_effective_address() local
163 maybe_flush_windows(rs1, rs2, rd); in safe_compute_effective_address()
164 return (safe_fetch_reg(rs1, regs) + safe_fetch_reg(rs2, regs)); in safe_compute_effective_address()
/openbmc/qemu/target/riscv/
H A Dcrypto_helper.c31 target_ulong rs1, target_ulong rs2, in aes32_operation() argument
34 uint8_t si = rs2 >> shamt; in aes32_operation()
57 target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2, in HELPER()
60 return aes32_operation(shamt, rs1, rs2, true, true); in HELPER()
63 target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2, in HELPER()
66 return aes32_operation(shamt, rs1, rs2, true, false); in HELPER()
69 target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2, in HELPER()
72 return aes32_operation(shamt, rs1, rs2, false, true); in HELPER()
75 target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2, in HELPER()
78 return aes32_operation(shamt, rs1, rs2, false, false); in HELPER()
[all …]
H A Dfpu_helper.c121 static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_h() argument
125 float16 frs2 = check_nanbox_h(env, rs2); in do_fmadd_h()
131 static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, in do_fmadd_s() argument
135 float32 frs2 = check_nanbox_s(env, rs2); in do_fmadd_s()
218 uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fadd_s() argument
221 float32 frs2 = check_nanbox_s(env, rs2); in helper_fadd_s()
225 uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fsub_s() argument
228 float32 frs2 = check_nanbox_s(env, rs2); in helper_fsub_s()
232 uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) in helper_fmul_s() argument
235 float32 frs2 = check_nanbox_s(env, rs2); in helper_fmul_s()
[all …]
H A Dbitmanip_helper.c27 target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2) in HELPER()
32 if ((rs2 >> i) & 1) { in HELPER()
40 target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2) in HELPER()
45 if ((rs2 >> i) & 1) { in HELPER()
106 static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2, in do_xperm() argument
115 pos = ((rs2 >> i) & mask) << sz_log2; in do_xperm()
123 target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2) in HELPER()
125 return do_xperm(rs1, rs2, 2); in HELPER()
128 target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2) in HELPER()
130 return do_xperm(rs1, rs2, 3); in HELPER()
H A Dinsn16.decode56 &r rd rs1 rs2 !extern
58 &s imm rs1 rs2 !extern
60 &b imm rs2 rs1 !extern
64 &r2_s rs1 rs2 !extern
70 @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
75 @cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
76 @cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3
77 @cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
78 @cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
80 @cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
[all …]
H A Dinsn32.decode21 %rs2 20:5
46 &b imm rs2 rs1
49 &r rd rs1 rs2
51 &r2_s rs1 rs2
52 &s imm rs1 rs2
55 &atomic aq rl rs2 rs1 rd
56 &rmrr vm rd rs1 rs2
57 &rmr vm rd rs2
59 &rnfvm vm rd rs1 rs2 nf
60 &k_aes shamt rs2 rs1 rd
[all …]
H A Dxthead.decode18 %rs2 20:5
26 &r rd rs1 rs2 !extern
31 &th_memidx rd rs1 rs2 imm2
36 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
37 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
43 @th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %rs2 %imm2
53 # is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
H A DXVentanaCondOps.decode13 %rs2 20:5
18 &r rd rs1 rs2 !extern
21 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfh.c.inc82 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
94 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
111 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
128 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
145 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
162 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
178 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
194 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
210 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
242 if (a->rs1 == a->rs2) { /* FMOV */
[all …]
H A Dtrans_rvf.c.inc79 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
102 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
119 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
136 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
153 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
170 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
186 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
202 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
218 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
250 if (a->rs1 == a->rs2) { /* FMOV */
[all …]
H A Dtrans_rvd.c.inc90 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
110 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
114 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
128 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
132 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
146 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
150 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
164 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3);
168 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
182 REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2);
[all …]
H A Dtrans_rvzacas.c.inc68 * Encodings with odd numbered registers specified in rs2 and rd are
71 if ((a->rs2 | a->rd) & 1) {
77 TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2);
106 * Encodings with odd numbered registers specified in rs2 and rd are
109 if ((a->rs2 | a->rd) & 1) {
117 TCGv_i64 src2l = get_gpr(ctx, a->rs2, EXT_NONE);
118 TCGv_i64 src2h = get_gpr(ctx, a->rs2 == 0 ? 0 : a->rs2 + 1, EXT_NONE);
H A Dtrans_rvvk.c.inc28 return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \
48 return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
174 vreg_ofs(s, a->rs2), tcg_env, \
188 vext_check_ss(s, a->rd, a->rs2, a->vm);
196 vext_check_ss(s, a->rd, a->rs2, a->vm);
226 return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, \
267 tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
283 require_align(a->rs2, s->lmul) &&
296 return vaes_check_overlap(s, a->rd, a->rs2) &&
342 tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
[all …]
H A Dtrans_rvzfa.c.inc188 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
205 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
222 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
239 TCGv_i64 src2 = get_fpr_d(ctx, a->rs2);
256 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
273 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
426 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
441 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
456 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
471 TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2);
[all …]
/openbmc/qemu/target/sparc/
H A Dinsns.decode47 &r_r_r rd rs1 rs2
48 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r
49 @d_r_r .. ..... ...... rs1:5 . ........ rs2:5 \
52 &r_r_r rs1=%dfp_rs1 rs2=%dfp_rs2
54 &r_r_r rd=%dfp_rd rs2=%dfp_rs2
56 &r_r_r rd=%dfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2
58 &r_r_r rd=%qfp_rd rs1=%qfp_rs1 rs2=%qfp_rs2
60 &r_r_r rd=%qfp_rd rs1=%dfp_rs1 rs2=%dfp_rs2
62 @r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r
64 &r_r_r rd=%dfp_rd rs1=%dfp_rs2 rs2=%dfp_rs1
[all …]
/openbmc/qemu/tests/tcg/tricore/asm/
H A Dmacros.h115 #define TEST_D_DDD(insn, num, result, rs1, rs2, rs3) \ argument
118 LI(DREG_RS2, rs2); \
124 #define TEST_D_DD_PSW(insn, num, result, psw, rs1, rs2) \ argument
127 LI(DREG_RS2, rs2); \
132 #define TEST_D_DDD_PSW(insn, num, result, psw, rs1, rs2, rs3) \ argument
135 LI(DREG_RS2, rs2); \
141 #define TEST_D_DDI(insn, num, result, rs1, rs2, imm) \ argument
144 LI(DREG_RS2, rs2); \
149 #define TEST_D_DDI_PSW(insn, num, result, psw, rs1, rs2, imm) \ argument
152 LI(DREG_RS2, rs2); \
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h142 #define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \ argument
145 ((rs2) << 11))
150 #define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \ argument
153 ((rs2) << 11))
154 #define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \ argument
157 ((rs2) << 11))
162 #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ argument
166 ((rs2) << 11) + \
202 #define ASM_LSWX(rd, rs1, rs2) ASM_12(OP_LSWX, rd, rs1, rs2) argument
204 #define ASM_STSWX(rd, rs1, rs2) ASM_12(OP_STSWX, rd, rs1, rs2) argument
/openbmc/qemu/target/rx/
H A Dinsns.decode26 &rrr rd rs rs2
27 &rri rd imm rs2
30 &mr rs ld mi rs2
44 @b2_rds_li .... .... .... rd:4 &rri rs2=%b2_r_0 imm=%b2_li_8
45 @b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=%b2_r_0
46 @b2_rs2_uimm4 .... .... imm:4 rs2:4 &rri rd=0
47 @b2_rds_imm5 .... ... imm:5 rd:4 &rri rs2=%b2_r_0
48 @b2_rd_rs_li .... .... rs2:4 rd:4 &rri imm=%b2_li_8
64 &rri rs2=%b3_r_0 imm=%b3_li_10
68 @b3_rd_rs_rs2 .... .... .... rd:4 rs:4 rs2:4 &rrr
[all …]
/openbmc/linux/arch/sparc/math-emu/
H A Dmath_64.c359 argp rs1 = NULL, rs2 = NULL, rd = NULL; in do_mathemu() local
398 case 1: rs2 = (argp)&f->regs[freg]; in do_mathemu()
401 rs2 = (argp)&zero; in do_mathemu()
405 case 7: FP_UNPACK_QP (QB, rs2); break; in do_mathemu()
406 case 6: FP_UNPACK_DP (DB, rs2); break; in do_mathemu()
407 case 5: FP_UNPACK_SP (SB, rs2); break; in do_mathemu()
457 case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break; in do_mathemu()
458 case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break; in do_mathemu()
459 case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break; in do_mathemu()
468 case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break; in do_mathemu()
[all …]
H A Dmath_32.c284 argp rs1 = NULL, rs2 = NULL, rd = NULL; in do_one_mathemu() local
390 rs2 = (argp)&fregs[freg]; in do_one_mathemu()
392 case 7: FP_UNPACK_QP (QB, rs2); break; in do_one_mathemu()
393 case 6: FP_UNPACK_DP (DB, rs2); break; in do_one_mathemu()
394 case 5: FP_UNPACK_SP (SB, rs2); break; in do_one_mathemu()
452 case FMOVS: rd->s = rs2->s; break; in do_one_mathemu()
453 case FABSS: rd->s = rs2->s & 0x7fffffff; break; in do_one_mathemu()
454 case FNEGS: rd->s = rs2->s ^ 0x80000000; break; in do_one_mathemu()
460 case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break; in do_one_mathemu()
461 case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break; in do_one_mathemu()
[all …]
/openbmc/linux/arch/riscv/include/asm/
H A Dinsn-def.h25 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
26 .insn r \opcode, \func3, \func7, \rd, \rs1, \rs2
37 .macro insn_r, opcode, func3, func7, rd, rs1, rs2
43 (.L__gpr_num_\rs2 << INSN_R_RS2_SHIFT))
63 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \ argument
64 ".insn r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n"
101 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2) \ argument
103 "insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \
115 #define INSN_R(opcode, func3, func7, rd, rs1, rs2) \ argument
117 RV_##rd, RV_##rs1, RV_##rs2)
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/fvp-base/
H A D0001-arm64-dts-fvp-Enable-virtio-rng-support.patch12 arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 1 -
15 … a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherbo…
17 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
18 +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi

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