Home
last modified time | relevance | path

Searched refs:reset_val (Results 1 – 24 of 24) sorted by relevance

/openbmc/linux/arch/arm64/kvm/
H A Dsys_regs.c1982 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1983 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
2001 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
2014 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
2115 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2117 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2122 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2128 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2129 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
2189 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
[all …]
H A Dsys_regs.h145 static inline u64 reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) in reset_val() function
/openbmc/linux/drivers/power/supply/
H A Dmax17040_battery.c55 u16 reset_val; member
66 .reset_val = 0x0054,
75 .reset_val = 0x0054,
84 .reset_val = 0x0054,
93 .reset_val = 0x0054,
102 .reset_val = 0x5400,
111 .reset_val = 0x5400,
120 .reset_val = 0x5400,
129 .reset_val = 0x5400,
158 return regmap_write(chip->regmap, MAX17040_CMD, chip->data.reset_val); in max17040_reset()
H A Dcw2015_battery.c101 u8 reset_val; in cw_update_profile() local
108 reset_val = reg_val; in cw_update_profile()
131 reset_val &= ~CW2015_MODE_RESTART; in cw_update_profile()
132 reg_val = reset_val | CW2015_MODE_RESTART; in cw_update_profile()
141 ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val); in cw_update_profile()
230 unsigned char reset_val; in cw_power_on_reset() local
232 reset_val = CW2015_MODE_SLEEP; in cw_power_on_reset()
233 ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val); in cw_power_on_reset()
240 reset_val = CW2015_MODE_NORMAL; in cw_power_on_reset()
241 ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reset_val); in cw_power_on_reset()
/openbmc/u-boot/tools/
H A Drkmux.py28 self.bits, self.attr, self.reset_val, self.desc = (
34 self.reset_val = ''
38 self.bits, self.attr, self.reset_val = cols[0:3]
51 return '%s,%s,%s,%s' % (self.bits, self.attr, self.reset_val,
/openbmc/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c170 u32 reset_val; member
787 .reset_val = FMC2_BUSWIDTH_16,
834 .reset_val = FMC2_BXTR_ADDSET_MAX,
842 .reset_val = FMC2_BXTR_ADDHLD_MAX,
850 .reset_val = FMC2_BXTR_DATAST_MAX,
858 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
871 .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
885 .reset_val = FMC2_BXTR_ADDSET_MAX,
893 .reset_val = FMC2_BXTR_ADDHLD_MAX,
901 .reset_val = FMC2_BXTR_DATAST_MAX,
[all …]
/openbmc/linux/include/linux/qed/
H A Dqed_chain.h498 u32 reset_val = p_chain->page_cnt - 1; in qed_chain_reset() local
501 p_chain->pbl.c.u16.prod_page_idx = (u16)reset_val; in qed_chain_reset()
502 p_chain->pbl.c.u16.cons_page_idx = (u16)reset_val; in qed_chain_reset()
504 p_chain->pbl.c.u32.prod_page_idx = reset_val; in qed_chain_reset()
505 p_chain->pbl.c.u32.cons_page_idx = reset_val; in qed_chain_reset()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c55 uint32_t reset_val = reset ? 1 : 0; in enc314_reset_fifo() local
58 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); in enc314_reset_fifo()
62 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc314_reset_fifo()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c431 uint32_t reset_val = reset ? 1 : 0; in enc32_reset_fifo() local
434 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); in enc32_reset_fifo()
438 REG_WAIT(DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, reset_val, 10, 5000); in enc32_reset_fifo()
/openbmc/linux/drivers/net/ethernet/amd/
H A Dlance.c475 int i, reset_val, lance_version; in lance_probe1() local
508 reset_val = inw(ioaddr+LANCE_RESET); /* Reset the LANCE */ in lance_probe1()
513 outw(reset_val, ioaddr+LANCE_RESET); in lance_probe1()
604 short reset_val = inw(ioaddr+LANCE_RESET); in lance_probe1() local
605 dev->dma = dma_tbl[(reset_val >> 2) & 3]; in lance_probe1()
606 dev->irq = irq_tbl[(reset_val >> 4) & 7]; in lance_probe1()
/openbmc/qemu/include/hw/acpi/
H A Dacpi-defs.h68 uint8_t reset_val; /* RESET_VALUE */ member
/openbmc/linux/drivers/infiniband/hw/efa/
H A Defa_com.c1047 u32 reset_val = 0; in efa_com_dev_reset() local
1066 EFA_SET(&reset_val, EFA_REGS_DEV_CTL_DEV_RESET, 1); in efa_com_dev_reset()
1067 EFA_SET(&reset_val, EFA_REGS_DEV_CTL_RESET_REASON, reset_reason); in efa_com_dev_reset()
1068 writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF); in efa_com_dev_reset()
/openbmc/linux/drivers/scsi/hisi_sas/
H A Dhisi_sas_v2_hw.c1018 int i, reset_val; in reset_hw_v2_hw() local
1025 reset_val = 0x1fffff; in reset_hw_v2_hw()
1027 reset_val = 0x7ffff; in reset_hw_v2_hw()
1087 reset_val); in reset_hw_v2_hw()
1089 reset_val); in reset_hw_v2_hw()
1092 if (reset_val != (val & reset_val)) { in reset_hw_v2_hw()
1099 reset_val); in reset_hw_v2_hw()
1101 reset_val); in reset_hw_v2_hw()
1105 if (val & reset_val) { in reset_hw_v2_hw()
/openbmc/qemu/hw/i386/
H A Dacpi-microvm.c180 .reset_val = ACPI_GED_RESET_VALUE, in acpi_build_microvm()
H A Dacpi-build.c219 pm->fadt.reset_val = 0xf; in acpi_get_pm_info()
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.c207 u32 mask, reset_val; in a6xx_gmu_start() local
212 reset_val = 0xbabeface; in a6xx_gmu_start()
215 reset_val = 0x100; in a6xx_gmu_start()
228 (val & mask) == reset_val, 100, 10000); in a6xx_gmu_start()
/openbmc/qemu/hw/arm/
H A Domap1.c120 uint32_t reset_val; member
145 timer->val = timer->reset_val; /* Should skip this on clk enable */ in omap_timer_update()
248 s->reset_val = value; in omap_mpu_timer_write()
270 s->reset_val = 31337; in omap_mpu_timer_reset()
355 s->timer.reset_val = value & 0xffff; in omap_wd_timer_write()
399 s->timer.reset_val = 0xffff; in omap_wd_timer_reset()
444 return s->timer.reset_val; in omap_os_timer_read()
472 s->timer.reset_val = value & 0x00ffffff; in omap_os_timer_write()
506 s->timer.reset_val = 0x00ffffff; in omap_os_timer_reset()
/openbmc/linux/drivers/net/ethernet/amazon/ena/
H A Dena_com.c2057 u32 stat, timeout, cap, reset_val; in ena_com_dev_reset() local
2081 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; in ena_com_dev_reset()
2082 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & in ena_com_dev_reset()
2084 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); in ena_com_dev_reset()
/openbmc/qemu/hw/loongarch/
H A Dacpi-build.c77 .reset_val = ACPI_GED_RESET_VALUE, in init_common_fadt_data()
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dsamsung-dsim.c541 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; in samsung_dsim_reset() local
544 samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val); in samsung_dsim_reset()
/openbmc/linux/drivers/usb/cdns3/
H A Dcdns3-gadget.c715 u16 reset_val = EP_CMD_TDL_MAX + 1 - tdl; in cdns3_wa2_reset_tdl() local
717 writel(EP_CMD_TDL_SET(reset_val) | EP_CMD_STDL, in cdns3_wa2_reset_tdl()
/openbmc/linux/drivers/net/ethernet/sun/
H A Dniu.c932 u64 reset_val, val_rd; in serdes_init_1g_serdes() local
939 reset_val = ENET_SERDES_RESET_0; in serdes_init_1g_serdes()
945 reset_val = ENET_SERDES_RESET_1; in serdes_init_1g_serdes()
979 nw64(ENET_SERDES_RESET, reset_val); in serdes_init_1g_serdes()
982 val_rd &= ~reset_val; in serdes_init_1g_serdes()
/openbmc/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_debug.c286 u32 reset_val[MAX_CHIP_IDS]; member
1701 if (s_rbc_reset_defs[i].reset_val[dev_data->chip_id]) in qed_grc_unreset_blocks()
1706 s_rbc_reset_defs[i].reset_val[chip_id]); in qed_grc_unreset_blocks()
/openbmc/qemu/hw/acpi/
H A Daml-build.c2290 build_append_int_noprefix(tbl, f->reset_val, 1); /* RESET_VALUE */ in build_fadt()