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Searched refs:reg_shift (Results 1 – 25 of 85) sorted by relevance

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/openbmc/u-boot/drivers/i2c/
H A Dmxc_i2c.c175 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; in bus_i2c_set_bus_speed() local
181 writeb(idx, base + (IFDR << reg_shift)); in bus_i2c_set_bus_speed()
184 writeb(I2CR_IDIS, base + (I2CR << reg_shift)); in bus_i2c_set_bus_speed()
185 writeb(0, base + (I2SR << reg_shift)); in bus_i2c_set_bus_speed()
198 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; in wait_for_sr_state() local
202 sr = readb(base + (I2SR << reg_shift)); in wait_for_sr_state()
206 (I2SR << reg_shift)); in wait_for_sr_state()
209 (I2SR << reg_shift)); in wait_for_sr_state()
211 __func__, sr, readb(base + (I2CR << reg_shift)), in wait_for_sr_state()
223 sr, readb(base + (I2CR << reg_shift)), state); in wait_for_sr_state()
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dns16550.c32 static u32 reg_shift; variable
36 out_8(reg_base + (UART_FCR << reg_shift), 0x06); in ns16550_open()
42 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_THRE) == 0); in ns16550_putc()
48 while ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) == 0); in ns16550_getc()
54 return ((in_8(reg_base + (UART_LSR << reg_shift)) & UART_LSR_DR) != 0); in ns16550_tstc()
71 n = getprop(devp, "reg-shift", &reg_shift, sizeof(reg_shift)); in ns16550_console_init()
72 if (n != sizeof(reg_shift)) in ns16550_console_init()
73 reg_shift = 0; in ns16550_console_init()
75 reg_shift = be32_to_cpu(reg_shift); in ns16550_console_init()
/openbmc/linux/drivers/input/misc/
H A Diqs7222.c798 int reg_shift; member
812 .reg_shift = 8,
820 .reg_shift = 0,
828 .reg_shift = 6,
836 .reg_shift = 5,
843 .reg_shift = 4,
850 .reg_shift = 3,
857 .reg_shift = 0,
866 .reg_shift = 10,
873 .reg_shift = 4,
[all …]
/openbmc/linux/drivers/ata/
H A Dpata_falcon.c132 int irq = 0, io_offset = 1, reg_shift = 2; /* Falcon defaults */ in pata_falcon_init_one() local
178 reg_shift = 0; in pata_falcon_init_one()
186 ap->ioaddr.error_addr = base + io_offset + (1 << reg_shift); in pata_falcon_init_one()
187 ap->ioaddr.feature_addr = base + io_offset + (1 << reg_shift); in pata_falcon_init_one()
188 ap->ioaddr.nsect_addr = base + io_offset + (2 << reg_shift); in pata_falcon_init_one()
189 ap->ioaddr.lbal_addr = base + io_offset + (3 << reg_shift); in pata_falcon_init_one()
190 ap->ioaddr.lbam_addr = base + io_offset + (4 << reg_shift); in pata_falcon_init_one()
191 ap->ioaddr.lbah_addr = base + io_offset + (5 << reg_shift); in pata_falcon_init_one()
192 ap->ioaddr.device_addr = base + io_offset + (6 << reg_shift); in pata_falcon_init_one()
193 ap->ioaddr.status_addr = base + io_offset + (7 << reg_shift); in pata_falcon_init_one()
[all …]
H A Dpata_pxa.c236 (ATA_REG_DATA << pdata->reg_shift); in pxa_ata_probe()
238 (ATA_REG_ERR << pdata->reg_shift); in pxa_ata_probe()
240 (ATA_REG_FEATURE << pdata->reg_shift); in pxa_ata_probe()
242 (ATA_REG_NSECT << pdata->reg_shift); in pxa_ata_probe()
244 (ATA_REG_LBAL << pdata->reg_shift); in pxa_ata_probe()
246 (ATA_REG_LBAM << pdata->reg_shift); in pxa_ata_probe()
248 (ATA_REG_LBAH << pdata->reg_shift); in pxa_ata_probe()
250 (ATA_REG_DEVICE << pdata->reg_shift); in pxa_ata_probe()
252 (ATA_REG_STATUS << pdata->reg_shift); in pxa_ata_probe()
254 (ATA_REG_CMD << pdata->reg_shift); in pxa_ata_probe()
H A Dpata_of_platform.c29 unsigned int reg_shift = 0; in pata_of_platform_probe() local
59 of_property_read_u32(dn, "reg-shift", &reg_shift); in pata_of_platform_probe()
76 reg_shift, pio_mask, &pata_platform_sht, in pata_of_platform_probe()
/openbmc/linux/drivers/gpio/
H A Dgpio-adnp.c15 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
16 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
17 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
18 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
19 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
24 unsigned int reg_shift; member
69 unsigned int reg = offset >> adnp->reg_shift; in adnp_gpio_get()
83 unsigned int reg = offset >> adnp->reg_shift; in __adnp_gpio_set()
112 unsigned int reg = offset >> adnp->reg_shift; in adnp_gpio_direction_input()
149 unsigned int reg = offset >> adnp->reg_shift; in adnp_gpio_direction_output()
[all …]
H A Dgpio-creg-snps.c34 u32 reg, reg_shift, value; in creg_gpio_set() local
40 reg_shift = layout->shift[offset]; in creg_gpio_set()
42 reg_shift += layout->bit_per_gpio[i] + layout->shift[i]; in creg_gpio_set()
46 reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift); in creg_gpio_set()
47 reg |= (value << reg_shift); in creg_gpio_set()
H A Dgpio-htc-egpio.c37 int reg_shift; /* bit shift */ member
123 return bit >> ei->reg_shift; in egpio_pos()
128 return 1 << (bit & ((1 << ei->reg_shift)-1)); in egpio_bit()
189 shift = pos << ei->reg_shift; in egpio_set()
241 shift += (1<<ei->reg_shift)) { in egpio_write_cache()
298 ei->reg_shift = fls(pdata->reg_width - 1); in egpio_probe()
299 pr_debug("reg_shift = %d\n", ei->reg_shift); in egpio_probe()
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-socfpga.c51 u32 reg_shift; member
107 u32 reg_offset, reg_shift; in socfpga_dwmac_parse_data() local
128 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift); in socfpga_dwmac_parse_data()
222 dwmac->reg_shift = reg_shift; in socfpga_dwmac_parse_data()
277 u32 reg_shift = dwmac->reg_shift; in socfpga_gen5_set_phy_mode() local
297 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); in socfpga_gen5_set_phy_mode()
298 ctrl |= val << reg_shift; in socfpga_gen5_set_phy_mode()
306 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); in socfpga_gen5_set_phy_mode()
312 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); in socfpga_gen5_set_phy_mode()
315 (reg_shift / 2)); in socfpga_gen5_set_phy_mode()
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-ocores.c36 u32 reg_shift; member
91 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_8()
96 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16()
101 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32()
106 iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16be()
111 iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32be()
116 return ioread8(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_8()
121 return ioread16(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_16()
126 return ioread32(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_32()
131 return ioread16be(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_16be()
[all …]
/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-pltfm.c27 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ argument
28 ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
74 u32 clk_phase[2] = {0}, reg_offset, reg_shift; in dw_mci_socfpga_priv_init() local
88 of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift); in dw_mci_socfpga_priv_init()
93 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); in dw_mci_socfpga_priv_init()
/openbmc/u-boot/drivers/net/
H A Ddwmac_socfpga.c23 u32 reg_shift; member
60 pdata->reg_shift = args.args[1]; in dwmac_socfpga_ofdata_to_platdata()
98 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; in dwmac_socfpga_probe()
100 modereg << pdata->reg_shift); in dwmac_socfpga_probe()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddevices.c47 { .base = UART3_BASE, .reg_shift = 2,
49 { .base = UART4_BASE, .reg_shift = 2,
51 { .base = UART5_BASE, .reg_shift = 2,
53 { .base = UART6_BASE, .reg_shift = 2,
/openbmc/qemu/target/arm/tcg/
H A Dneon-dp.decode189 &2reg_shift vm vd q shift size
198 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
200 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
202 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
204 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
207 &2reg_shift vm=%vm_dp vd=%vd_dp size=3
209 &2reg_shift vm=%vm_dp vd=%vd_dp size=2
211 &2reg_shift vm=%vm_dp vd=%vd_dp size=1
213 &2reg_shift vm=%vm_dp vd=%vd_dp size=0
217 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
[all …]
/openbmc/linux/drivers/input/touchscreen/
H A Diqs7211.c480 int reg_shift; member
506 .reg_shift = 9,
527 .reg_shift = 5,
548 .reg_shift = 0,
566 .reg_shift = 0,
578 .reg_shift = 8,
620 .reg_shift = 8,
630 .reg_shift = 0,
726 .reg_shift = 8,
785 .reg_shift = 15,
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dboard.c66 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
69 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
72 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
74 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
76 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
78 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_vbif.c159 u32 reg_lvl, reg_val, reg_val_lvl, mask, reg_high, reg_shift; in dpu_hw_set_qos_remap() local
168 reg_shift = (xin_id & 0x7) * 4; in dpu_hw_set_qos_remap()
173 mask = 0x7 << reg_shift; in dpu_hw_set_qos_remap()
176 reg_val |= (remap_level << reg_shift) & mask; in dpu_hw_set_qos_remap()
179 reg_val_lvl |= (remap_level << reg_shift) & mask; in dpu_hw_set_qos_remap()
/openbmc/linux/drivers/thermal/broadcom/
H A Dbrcmstb_thermal.c75 int reg_shift; member
85 .reg_shift = AVS_TMON_INT_THRESH_low_shift,
93 .reg_shift = AVS_TMON_INT_THRESH_high_shift,
101 .reg_shift = AVS_TMON_RESET_THRESH_shift,
198 val >>= trip->reg_shift; in avs_tmon_get_trip_temp()
216 val <<= trip->reg_shift; in avs_tmon_set_trip_temp()
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-mcp23s08_i2c.c26 mcp->reg_shift = 0; in mcp230xx_probe()
33 mcp->reg_shift = 1; in mcp230xx_probe()
40 mcp->reg_shift = 1; in mcp230xx_probe()
/openbmc/linux/arch/mips/include/asm/
H A Dsetup.h13 unsigned int reg_shift, unsigned int timeout);
16 unsigned int reg_shift, unsigned int timeout) {} in setup_8250_early_printk_port() argument
/openbmc/linux/arch/mips/kernel/
H A Dearly_printk_8250.c16 void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift, in setup_8250_early_printk_port() argument
20 serial8250_reg_shift = reg_shift; in setup_8250_early_printk_port()
/openbmc/u-boot/drivers/serial/
H A Dns16550.c100 offset *= 1 << plat->reg_shift; in ns16550_writeb()
107 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); in ns16550_writeb()
115 offset *= 1 << plat->reg_shift; in ns16550_readb()
118 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); in ns16550_readb()
405 info->reg_shift = plat->reg_shift; in ns16550_serial_getinfo()
483 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); in ns16550_serial_ofdata_to_platdata()
H A Dserial_rockchip.c34 plat->plat.reg_shift = plat->dtplat.reg_shift; in rockchip_serial_probe()
/openbmc/u-boot/drivers/gpio/
H A Dhsdk-creg-gpio.c32 u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift; in hsdk_creg_gpio_set_value() local
35 reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift); in hsdk_creg_gpio_set_value()
36 reg |= ((val ? hcg->deactivate : hcg->activate) << reg_shift); in hsdk_creg_gpio_set_value()

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