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Searched refs:reg_set (Results 1 – 25 of 37) sorted by relevance

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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_cp110.c114 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in comphy_pcie_power_up()
118 reg_set(comphy_base + COMMON_PHY_SD_CTRL1, in comphy_pcie_power_up()
130 reg_set((void __iomem *)DFX_DEV_GEN_CTRL12, in comphy_pcie_power_up()
147 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
154 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
172 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_pcie_power_up()
182 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in comphy_pcie_power_up()
198 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in comphy_pcie_power_up()
200 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG, in comphy_pcie_power_up()
204 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG, in comphy_pcie_power_up()
[all …]
H A Dcomphy_a3700.c205 reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF); in comphy_pcie_power_up()
265 reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF); in reg_set_indirect()
266 reg_set(rh_vsreg_data, data, mask); in reg_set_indirect()
314 reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF); in comphy_sata_power_up()
315 reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll); in comphy_sata_power_up()
321 reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF); in comphy_sata_power_up()
370 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0); in comphy_usb3_power_up()
376 reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns); in comphy_usb3_power_up()
486 reg_set(rh_vsreg_addr, in comphy_usb3_power_up()
516 reg_set(USB32_CTRL_BASE, in comphy_usb3_power_up()
[all …]
H A Dcomphy_mux.c106 reg_set(selector_base, value, mask); in comphy_mux_reg_write()
/openbmc/qemu/hw/intc/
H A Dexynos4210_combiner.c71 VMSTATE_UINT32_ARRAY(reg_set, Exynos4210CombinerState,
125 val = s->reg_set[offset >> 2]; in exynos4210_combiner_read()
201 s->reg_set[offset >> 2] = val; in exynos4210_combiner_write()
290 memset(&s->reg_set, 0, sizeof(s->reg_set)); in exynos4210_combiner_reset()
292 s->reg_set[0xC0 >> 2] = 0x01010101; in exynos4210_combiner_reset()
293 s->reg_set[0xC4 >> 2] = 0x01010101; in exynos4210_combiner_reset()
294 s->reg_set[0xD0 >> 2] = 0x01010101; in exynos4210_combiner_reset()
295 s->reg_set[0xD4 >> 2] = 0x01010101; in exynos4210_combiner_reset()
/openbmc/linux/drivers/scsi/mvsas/
H A Dmv_sas.h64 #define SATA_RECEIVED_FIS_LIST(reg_set) \ argument
65 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
66 #define SATA_RECEIVED_SDB_FIS(reg_set) \ argument
67 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
68 #define SATA_RECEIVED_D2H_FIS(reg_set) \ argument
69 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
70 #define SATA_RECEIVED_PIO_FIS(reg_set) \ argument
71 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
72 #define SATA_RECEIVED_DMA_FIS(reg_set) \ argument
73 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
[all …]
H A Dmv_94xx.c667 mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) in mvs_94xx_clear_srs_irq() argument
684 if (reg_set > 31) in mvs_94xx_clear_srs_irq()
689 if (tmp & (1 << (reg_set % 32))) { in mvs_94xx_clear_srs_irq()
690 mv_dprintk("register set 0x%x was stopped.\n", reg_set); in mvs_94xx_clear_srs_irq()
691 if (reg_set > 31) in mvs_94xx_clear_srs_irq()
692 mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32)); in mvs_94xx_clear_srs_irq()
694 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); in mvs_94xx_clear_srs_irq()
744 u8 reg_set = *tfs; in mvs_94xx_free_reg_set() local
749 mvi->sata_reg_set &= ~bit(reg_set); in mvs_94xx_free_reg_set()
750 if (reg_set < 32) in mvs_94xx_free_reg_set()
[all …]
H A Dmv_64xx.c124 mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) in mvs_64xx_clear_srs_irq() argument
136 if (tmp & (1 << (reg_set % 32))) { in mvs_64xx_clear_srs_irq()
138 reg_set); in mvs_64xx_clear_srs_irq()
139 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); in mvs_64xx_clear_srs_irq()
/openbmc/linux/drivers/media/i2c/
H A Drj54n1cb0c.c464 static int reg_set(struct i2c_client *client, const u16 reg, in reg_set() function
506 return reg_set(client, RJ54N1_STILL_CONTROL, (!enable) << 7, 0x80); in rj54n1_s_stream()
895 ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1); in rj54n1_set_clock()
1035 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_set_fmt()
1040 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_set_fmt()
1045 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_set_fmt()
1050 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_set_fmt()
1055 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_set_fmt()
1062 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8); in rj54n1_set_fmt()
1069 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8); in rj54n1_set_fmt()
[all …]
H A Dak881x.c46 static int reg_set(struct i2c_client *client, const u8 reg, in reg_set() function
172 reg_set(client, AK881X_VIDEO_PROCESS1, vp1, 0xf); in ak881x_s_std_output()
H A Dmt9m111.c140 #define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val)) macro
440 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_reset()
442 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); in mt9m111_reset()
834 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN); in mt9m111_set_autoexposure()
843 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN); in mt9m111_set_autowhitebalance()
923 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_suspend()
925 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC | in mt9m111_suspend()
/openbmc/linux/drivers/gpio/
H A Dgpio-mmio.c140 return !!(gc->read_reg(gc->reg_set) & pinmask); in bgpio_get_set()
162 *bits |= gc->read_reg(gc->reg_set) & set_mask; in bgpio_get_set_multiple()
243 gc->write_reg(gc->reg_set, mask); in bgpio_set_with_clear()
260 gc->write_reg(gc->reg_set, gc->bgpio_data); in bgpio_set_set()
312 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); in bgpio_set_multiple_set()
324 gc->write_reg(gc->reg_set, set_mask); in bgpio_set_multiple_with_clear()
502 gc->reg_set = set; in bgpio_setup_io()
507 gc->reg_set = set; in bgpio_setup_io()
641 gc->bgpio_data = gc->read_reg(gc->reg_set); in bgpio_init()
/openbmc/linux/drivers/leds/
H A Dleds-tca6507.c157 int reg_set; /* One bit per register where member
272 tca->reg_set |= (1 << bit); in set_select()
293 tca->reg_set |= 1 << reg; in set_code()
354 set = tca->reg_set; in tca6507_work()
356 tca->reg_set = 0; in tca6507_work()
540 if (tca->reg_set) in led_assign()
608 if (tca->reg_set) in tca6507_gpio_set_value()
780 tca->reg_set = 0x7f; in tca6507_probe()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Diomux.c62 writel(1 << bp, &mxs_reg->reg_set); in mxs_iomux_setup_pad()
74 writel(1 << bp, &mxs_reg->reg_set); in mxs_iomux_setup_pad()
/openbmc/linux/drivers/scsi/megaraid/
H A Dmegaraid_sas_base.c230 struct megasas_register_set __iomem *reg_set);
308 cmd->frame_phys_addr, 0, instance->reg_set); in megasas_issue_dcmd()
463 regs = instance->reg_set; in megasas_enable_intr_xscale()
480 regs = instance->reg_set; in megasas_disable_intr_xscale()
493 return readl(&instance->reg_set->outbound_msg_0); in megasas_read_fw_status_reg_xscale()
505 regs = instance->reg_set; in megasas_clear_intr_xscale()
643 regs = instance->reg_set; in megasas_enable_intr_ppc()
662 regs = instance->reg_set; in megasas_disable_intr_ppc()
675 return readl(&instance->reg_set->outbound_scratch_pad_0); in megasas_read_fw_status_reg_ppc()
687 regs = instance->reg_set; in megasas_clear_intr_ppc()
[all …]
H A Dmegaraid_sas_fusion.c107 (instance, instance->reg_set)) in megasas_adp_reset_wait_for_ready()
168 regs = instance->reg_set; in megasas_enable_intr_fusion()
191 regs = instance->reg_set; in megasas_disable_intr_fusion()
205 regs = instance->reg_set; in megasas_clear_intr_fusion()
299 writeq(req_data, &instance->reg_set->inbound_low_queue_port); in megasas_write_64bit_req_desc()
304 &instance->reg_set->inbound_low_queue_port); in megasas_write_64bit_req_desc()
306 &instance->reg_set->inbound_high_queue_port); in megasas_write_64bit_req_desc()
325 &instance->reg_set->inbound_single_queue_port); in megasas_fire_cmd_fusion()
351 &instance->reg_set->outbound_scratch_pad_2) & 0x00FFFF; in megasas_fusion_update_can_queue()
1107 (instance, &instance->reg_set->outbound_scratch_pad_1); in megasas_ioc_init_fusion()
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dmxs_gpio.c72 writel(1 << PAD_PIN(gpio), &reg->reg_set); in gpio_set_value()
98 writel(1 << PAD_PIN(gpio), &reg->reg_set); in gpio_direction_output()
/openbmc/u-boot/drivers/pinctrl/aspeed/
H A Dpinctrl_ast2500.c199 clrbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); in ast2500_pinctrl_group_set()
201 setbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); in ast2500_pinctrl_group_set()
H A Dpinctrl_ast2400.c204 clrbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); in ast2400_pinctrl_group_set()
206 setbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); in ast2400_pinctrl_group_set()
H A Dpinctrl-aspeed.h3 u32 reg_set; member
H A Dpinctrl_ast2600.c517 descs->reg_set); in ast2600_pinctrl_group_set()
520 descs->reg_set); in ast2600_pinctrl_group_set()
/openbmc/u-boot/drivers/usb/host/
H A Dehci-mxs.c65 pll_offset = offsetof(struct mxs_register_32, reg_set); in ehci_mxs_toggle_clock()
71 dig_offset = offsetof(struct mxs_register_32, reg_set); in ehci_mxs_toggle_clock()
/openbmc/qemu/include/hw/intc/
H A Dexynos4210_combiner.h50 uint32_t reg_set[IIC_REGSET_SIZE]; member
/openbmc/linux/drivers/gpu/drm/i2c/
H A Dtda998x_drv.c689 reg_set(struct tda998x_priv *priv, u16 reg, u8 val) in reg_set() function
718 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); in tda998x_reset()
845 reg_set(priv, REG_DIP_IF_FLAGS, bit); in tda998x_write_if()
996 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); in tda998x_audio_mute()
998 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); in tda998x_audio_mute()
1043 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); in tda998x_configure_audio()
1303 reg_set(priv, REG_TX4, TX4_PD_RAM); in tda998x_connector_get_modes()
1547 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); in tda998x_bridge_mode_set()
1557 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT); in tda998x_bridge_mode_set()
1590 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); in tda998x_bridge_mode_set()
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.c244 unsigned int reg_pupd, reg_set, reg_rst; in mtk_pctrl_spec_pull_set_samereg() local
263 reg_set = spec_pupd_pin->offset + devdata->port_align; in mtk_pctrl_spec_pull_set_samereg()
269 reg_pupd = reg_set; in mtk_pctrl_spec_pull_set_samereg()
283 regmap_write(regmap, reg_set, bit_r0); in mtk_pctrl_spec_pull_set_samereg()
288 regmap_write(regmap, reg_set, bit_r1); in mtk_pctrl_spec_pull_set_samereg()
291 regmap_write(regmap, reg_set, bit_r0); in mtk_pctrl_spec_pull_set_samereg()
292 regmap_write(regmap, reg_set, bit_r1); in mtk_pctrl_spec_pull_set_samereg()
/openbmc/u-boot/arch/arm/mach-imx/
H A Dmisc.c56 writel(MXS_BLOCK_SFTRST, &reg->reg_set); in mxs_reset_block()

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