183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2552a848eSStefano Babic /*
3552a848eSStefano Babic * Copyright 2013 Stefan Roese <sr@denx.de>
4552a848eSStefano Babic */
5552a848eSStefano Babic
6552a848eSStefano Babic #include <common.h>
7552a848eSStefano Babic #include <asm/arch/sys_proto.h>
8552a848eSStefano Babic #include <linux/errno.h>
9552a848eSStefano Babic #include <asm/io.h>
10552a848eSStefano Babic #include <asm/mach-imx/regs-common.h>
11552a848eSStefano Babic
12*528915c7SYe Li DECLARE_GLOBAL_DATA_PTR;
13*528915c7SYe Li
14552a848eSStefano Babic /* 1 second delay should be plenty of time for block reset. */
15552a848eSStefano Babic #define RESET_MAX_TIMEOUT 1000000
16552a848eSStefano Babic
17552a848eSStefano Babic #define MXS_BLOCK_SFTRST (1 << 31)
18552a848eSStefano Babic #define MXS_BLOCK_CLKGATE (1 << 30)
19552a848eSStefano Babic
mxs_wait_mask_set(struct mxs_register_32 * reg,uint32_t mask,unsigned int timeout)20552a848eSStefano Babic int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
21552a848eSStefano Babic int timeout)
22552a848eSStefano Babic {
23552a848eSStefano Babic while (--timeout) {
24552a848eSStefano Babic if ((readl(®->reg) & mask) == mask)
25552a848eSStefano Babic break;
26552a848eSStefano Babic udelay(1);
27552a848eSStefano Babic }
28552a848eSStefano Babic
29552a848eSStefano Babic return !timeout;
30552a848eSStefano Babic }
31552a848eSStefano Babic
mxs_wait_mask_clr(struct mxs_register_32 * reg,uint32_t mask,unsigned int timeout)32552a848eSStefano Babic int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
33552a848eSStefano Babic int timeout)
34552a848eSStefano Babic {
35552a848eSStefano Babic while (--timeout) {
36552a848eSStefano Babic if ((readl(®->reg) & mask) == 0)
37552a848eSStefano Babic break;
38552a848eSStefano Babic udelay(1);
39552a848eSStefano Babic }
40552a848eSStefano Babic
41552a848eSStefano Babic return !timeout;
42552a848eSStefano Babic }
43552a848eSStefano Babic
mxs_reset_block(struct mxs_register_32 * reg)44552a848eSStefano Babic int mxs_reset_block(struct mxs_register_32 *reg)
45552a848eSStefano Babic {
46552a848eSStefano Babic /* Clear SFTRST */
47552a848eSStefano Babic writel(MXS_BLOCK_SFTRST, ®->reg_clr);
48552a848eSStefano Babic
49552a848eSStefano Babic if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
50552a848eSStefano Babic return 1;
51552a848eSStefano Babic
52552a848eSStefano Babic /* Clear CLKGATE */
53552a848eSStefano Babic writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
54552a848eSStefano Babic
55552a848eSStefano Babic /* Set SFTRST */
56552a848eSStefano Babic writel(MXS_BLOCK_SFTRST, ®->reg_set);
57552a848eSStefano Babic
58552a848eSStefano Babic /* Wait for CLKGATE being set */
59552a848eSStefano Babic if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
60552a848eSStefano Babic return 1;
61552a848eSStefano Babic
62552a848eSStefano Babic /* Clear SFTRST */
63552a848eSStefano Babic writel(MXS_BLOCK_SFTRST, ®->reg_clr);
64552a848eSStefano Babic
65552a848eSStefano Babic if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
66552a848eSStefano Babic return 1;
67552a848eSStefano Babic
68552a848eSStefano Babic /* Clear CLKGATE */
69552a848eSStefano Babic writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
70552a848eSStefano Babic
71552a848eSStefano Babic if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
72552a848eSStefano Babic return 1;
73552a848eSStefano Babic
74552a848eSStefano Babic return 0;
75552a848eSStefano Babic }
76*528915c7SYe Li
get_sp(void)77*528915c7SYe Li static ulong get_sp(void)
78*528915c7SYe Li {
79*528915c7SYe Li ulong ret;
80*528915c7SYe Li
81*528915c7SYe Li asm("mov %0, sp" : "=r"(ret) : );
82*528915c7SYe Li return ret;
83*528915c7SYe Li }
84*528915c7SYe Li
board_lmb_reserve(struct lmb * lmb)85*528915c7SYe Li void board_lmb_reserve(struct lmb *lmb)
86*528915c7SYe Li {
87*528915c7SYe Li ulong sp, bank_end;
88*528915c7SYe Li int bank;
89*528915c7SYe Li
90*528915c7SYe Li sp = get_sp();
91*528915c7SYe Li debug("## Current stack ends at 0x%08lx ", sp);
92*528915c7SYe Li
93*528915c7SYe Li /* adjust sp by 16K to be safe */
94*528915c7SYe Li sp -= 4096 << 2;
95*528915c7SYe Li for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
96*528915c7SYe Li if (sp < gd->bd->bi_dram[bank].start)
97*528915c7SYe Li continue;
98*528915c7SYe Li bank_end = gd->bd->bi_dram[bank].start +
99*528915c7SYe Li gd->bd->bi_dram[bank].size;
100*528915c7SYe Li if (sp >= bank_end)
101*528915c7SYe Li continue;
102*528915c7SYe Li lmb_reserve(lmb, sp, bank_end - sp);
103*528915c7SYe Li break;
104*528915c7SYe Li }
105*528915c7SYe Li }
106