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Searched refs:qtest_writel (Results 1 – 25 of 39) sorted by relevance

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/openbmc/qemu/tests/qtest/
H A Dmicrobit-test.c34 qtest_writel(qts, event_addr, 0x00); in uart_wait_for_event()
68 qtest_writel(qts, NRF51_UART_BASE + A_UART_TXD, in[i]); in uart_w_to_txd()
83 qtest_writel(qts, NRF51_UART_BASE + A_UART_ENABLE, 0x04); in test_nrf51_uart()
84 qtest_writel(qts, NRF51_UART_BASE + A_UART_STARTRX, 0x01); in test_nrf51_uart()
87 qtest_writel(qts, NRF51_UART_BASE + A_UART_RXDRDY, 0x00); in test_nrf51_uart()
90 qtest_writel(qts, NRF51_UART_BASE + A_UART_INTENSET, 0x04); in test_nrf51_uart()
92 qtest_writel(qts, NRF51_UART_BASE + A_UART_INTENCLR, 0x04); in test_nrf51_uart()
98 qtest_writel(qts, NRF51_UART_BASE + A_UART_STARTTX, 0x01); in test_nrf51_uart()
103 qtest_writel(qts, NRF51_UART_BASE + A_UART_SUSPEND, 0x01); in test_nrf51_uart()
104 qtest_writel(qts, NRF51_UART_BASE + A_UART_TXD, 'h'); in test_nrf51_uart()
[all …]
H A Dxlnx-can-test.c105 qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK); in read_data()
114 qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]); in send_data()
115 qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]); in send_data()
116 qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]); in send_data()
117 qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]); in send_data()
125 qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK); in send_data()
147 qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); in test_can_bus()
148 qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); in test_can_bus()
149 qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); in test_can_bus()
150 qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); in test_can_bus()
[all …]
H A Dsifive-e-aon-watchdog-test.c51 qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); in test_init()
52 qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0); in test_init()
54 qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); in test_init()
55 qtest_writel(qts, WDOG_BASE + WDOGCFG, 0); in test_init()
57 qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); in test_init()
58 qtest_writel(qts, WDOG_BASE + WDOGCMP0, 0xBEEF); in test_init()
69 qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0xBEEF); in test_wdogcount()
72 qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); in test_wdogcount()
73 qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0xBEEF); in test_wdogcount()
76 qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY); in test_wdogcount()
[all …]
H A Ddm163-test.c36 qtest_writel(qts, 0x48000400, 0xFFFFFEB7); in rise_gpio_pin_dck()
38 qtest_writel(qts, 0x48000414, 0x00000002); in rise_gpio_pin_dck()
44 qtest_writel(qts, 0x48000400, 0xFFFFFEB7); in lower_gpio_pin_dck()
46 qtest_writel(qts, 0x48000414, 0x00000000); in lower_gpio_pin_dck()
52 qtest_writel(qts, 0x48000800, 0xFFFFF7FF); in rise_gpio_pin_selbk()
54 qtest_writel(qts, 0x48000814, 0x00000020); in rise_gpio_pin_selbk()
60 qtest_writel(qts, 0x48000800, 0xFFFFF7FF); in lower_gpio_pin_selbk()
62 qtest_writel(qts, 0x48000814, 0x00000000); in lower_gpio_pin_selbk()
68 qtest_writel(qts, 0x48000800, 0xFFFFFDFF); in rise_gpio_pin_lat_b()
70 qtest_writel(qts, 0x48000814, 0x00000010); in rise_gpio_pin_lat_b()
[all …]
H A Dstm32l4x5_usart-test.c66 qtest_writel(qts, NVIC_ICPR1, (1 << n)); in clear_nvic_pending()
107 qtest_writel(qts, USART1_BASE_ADDR + A_TDR, in[i]); in usart_send_string()
119 qtest_writel(qts, (RCC_BASE_ADDR + A_CR), R_CR_MSION_MASK); in init_clocks()
122 qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0); in init_clocks()
132 qtest_writel(qts, (RCC_BASE_ADDR + A_PLLCFGR), R_PLLCFGR_PLLREN_MASK | in init_clocks()
139 qtest_writel(qts, (RCC_BASE_ADDR + A_CR), value | R_CR_PLLON_MASK); in init_clocks()
142 qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0); in init_clocks()
145 qtest_writel(qts, (RCC_BASE_ADDR + A_CCIPR), 0); in init_clocks()
149 qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), (value & ~R_CFGR_SW_MASK) | in init_clocks()
153 qtest_writel(qts, (RCC_BASE_ADDR + A_APB2ENR), R_APB2ENR_SYSCFGEN_MASK); in init_clocks()
[all …]
H A Dxlnx-canfd-test.c119 qtest_writel(qts, CANFD0_BASE_ADDR + R_AFMR_REGISTER0 + 8 * i, in enable_filters()
121 qtest_writel(qts, CANFD0_BASE_ADDR + R_AFIR_REGISTER0 + 8 * i, in enable_filters()
125 qtest_writel(qts, CANFD1_BASE_ADDR + R_AFMR_REGISTER0 + 8 * i, in enable_filters()
127 qtest_writel(qts, CANFD1_BASE_ADDR + R_AFIR_REGISTER0 + 8 * i, in enable_filters()
132 qtest_writel(qts, CANFD0_BASE_ADDR + R_FILTER_CONTROL_REGISTER, in enable_filters()
134 qtest_writel(qts, CANFD1_BASE_ADDR + R_FILTER_CONTROL_REGISTER, in enable_filters()
143 qtest_writel(qts, CANFD0_BASE_ADDR + R_SRR_OFFSET, SRR_CONFIG_MODE); in configure_canfd()
144 qtest_writel(qts, CANFD1_BASE_ADDR + R_SRR_OFFSET, SRR_CONFIG_MODE); in configure_canfd()
147 qtest_writel(qts, CANFD0_BASE_ADDR + R_MSR_OFFSET, mode); in configure_canfd()
148 qtest_writel(qts, CANFD1_BASE_ADDR + R_MSR_OFFSET, mode); in configure_canfd()
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H A Dqtest_aspeed.c26 qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, 0); in aspeed_i2c_startup()
28 qtest_writel(s, baseaddr + A_I2CC_FUN_CTRL, v); in aspeed_i2c_startup()
33 qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, slave_addr << 1); in aspeed_i2c_startup()
34 qtest_writel(s, baseaddr + A_I2CD_CMD, in aspeed_i2c_startup()
38 qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, reg); in aspeed_i2c_startup()
39 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD); in aspeed_i2c_startup()
53 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_RX_CMD); in aspeed_i2c_read_n()
58 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_STOP_CMD); in aspeed_i2c_read_n()
90 qtest_writel(s, baseaddr + A_I2CD_BYTE_BUF, v & 0xff); in aspeed_i2c_write_n()
92 qtest_writel(s, baseaddr + A_I2CD_CMD, A_I2CD_M_TX_CMD); in aspeed_i2c_write_n()
[all …]
H A Dfuzz-e1000e-test.c30 qtest_writel(s, 0xe1020030, 0x190002e1); in test_lp1879531_eth_get_rss_ex_dst_addr()
32 qtest_writel(s, 0xe1020048, 0x12077cdd); in test_lp1879531_eth_get_rss_ex_dst_addr()
33 qtest_writel(s, 0xe1020400, 0xba077cdd); in test_lp1879531_eth_get_rss_ex_dst_addr()
34 qtest_writel(s, 0xe1020420, 0x190002e1); in test_lp1879531_eth_get_rss_ex_dst_addr()
35 qtest_writel(s, 0xe1020428, 0x3509d807); in test_lp1879531_eth_get_rss_ex_dst_addr()
H A Daspeed_hace-test.c154 qtest_writel(s, base + HACE_HASH_SRC, src); in write_regs()
155 qtest_writel(s, base + HACE_HASH_DIGEST, out); in write_regs()
156 qtest_writel(s, base + HACE_HASH_DATA_LEN, length); in write_regs()
157 qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); in write_regs()
181 qtest_writel(s, base + HACE_STS, 0x00000200); in test_md5()
214 qtest_writel(s, base + HACE_STS, 0x00000200); in test_sha256()
247 qtest_writel(s, base + HACE_STS, 0x00000200); in test_sha512()
298 qtest_writel(s, base + HACE_STS, 0x00000200); in test_sha256_sg()
349 qtest_writel(s, base + HACE_STS, 0x00000200); in test_sha512_sg()
390 qtest_writel(s, base + HACE_STS, 0x00000200); in test_sha256_accum()
[all …]
H A Dfuzz-lsi53c895a-test.c31 qtest_writel(s, 0xff000000, 0xc0000024); in test_lsi_dma_reentrancy()
32 qtest_writel(s, 0xff000114, 0x00000080); in test_lsi_dma_reentrancy()
33 qtest_writel(s, 0xff00012c, 0xff000000); in test_lsi_dma_reentrancy()
34 qtest_writel(s, 0xff000004, 0xff000114); in test_lsi_dma_reentrancy()
35 qtest_writel(s, 0xff000008, 0xff100014); in test_lsi_dma_reentrancy()
36 qtest_writel(s, 0xff10002f, 0x000000ff); in test_lsi_dma_reentrancy()
H A Dast2700-gpio-test.c29 qtest_writel(s, offset, 0x00000003); in test_output_pins()
34 qtest_writel(s, offset, 0x00000002); in test_output_pins()
57 qtest_writel(s, offset, 0); in test_input_pins()
H A Daspeed_gpio-test.c60 qtest_writel(s, AST2600_GPIO_BASE + GPIO_ABCD_DIRECTION, 0x00000000); in test_set_input_pins()
70 qtest_writel(s, AST2600_GPIO_BASE + GPIO_ABCD_DATA_VALUE, 0x00000000); in test_set_input_pins()
H A Dlibqtest-single.h201 qtest_writel(global_qtest, addr, value); in writel()
H A Daspeed_fsi-test.c51 qtest_writel(s, aspeed_fsi_base_addr + reg, val); in aspeed_fsi_writel()
H A Dtpm-util.c36 qtest_writel(s, TPM_CRB_ADDR_BASE + A_CRB_CTRL_START, start); in tpm_util_crb_transfer()
H A Dpnv-xive2-common.c83 return qtest_writel(qts, addr + offset, cpu_to_be32(val)); in set_esb()
H A Daspeed-smc-utils.c44 qtest_writel(data->s, data->spi_base + offset, value); in spi_writel()
61 qtest_writel(data->s, data->flash_base + offset, value); in flash_writel()
H A Dlibqtest.h496 void qtest_writel(QTestState *s, uint64_t addr, uint32_t value);
/openbmc/qemu/tests/qtest/libqos/
H A Dvirtio-mmio.c49 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES_SEL, 0); in qvirtio_mmio_get_features()
53 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_HOST_FEATURES_SEL, 1); in qvirtio_mmio_get_features()
64 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES_SEL, 0); in qvirtio_mmio_set_features()
65 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES, features); in qvirtio_mmio_set_features()
68 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES_SEL, 1); in qvirtio_mmio_set_features()
69 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_GUEST_FEATURES, in qvirtio_mmio_set_features()
89 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_DEVICE_STATUS, (uint32_t)status); in qvirtio_mmio_set_status()
99 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_ACK, 1); in qvirtio_mmio_get_queue_isr_status()
113 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_INTERRUPT_ACK, 2); in qvirtio_mmio_get_config_isr_status()
135 qtest_writel(dev->qts, dev->addr + QVIRTIO_MMIO_QUEUE_SEL, (uint32_t)index); in qvirtio_mmio_queue_select()
[all …]
H A Dsdhci-cmd.c63 qtest_writel(qts, reg, msg_frag); in write_fifo()
70 qtest_writel(qts, reg, 0); in fill_block()
80 qtest_writel(qts, base_addr + SDHC_ARGUMENT, argument); in sdhci_cmd_regs()
H A Drtas.c16 qtest_writel(qts, target_args + i * sizeof(uint32_t), args[i]); in qrtas_copy_args()
H A Dvirtio-pci.c136 qtest_writel(dev->pdev->bus->qts, vqpci->msix_addr, 0); in qvirtio_pci_get_queue_isr_status()
160 qtest_writel(dev->pdev->bus->qts, dev->config_msix_addr, 0); in qvirtio_pci_get_config_isr_status()
H A Dgeneric-pcihost.c81 qtest_writel(bus->qts, s->gpex_pio_base + addr, val); in qpci_generic_pio_writel()
/openbmc/qemu/tests/qtest/fuzz/
H A Dmeson.build29 '-Wl,-wrap,qtest_writel',
H A Dqtest_wrappers.c38 WRAP(void , qtest_writel(QTestState *s, uint64_t addr, uint32_t value)) in WRAP()

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