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Searched refs:post_div (Results 1 – 25 of 49) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pll.c85 unsigned int den, unsigned int post_div, in amdgpu_pll_get_fb_ref_div() argument
92 ref_div_max = min(100 / post_div, ref_div_max); in amdgpu_pll_get_fb_ref_div()
94 ref_div_max = min(128 / post_div, ref_div_max); in amdgpu_pll_get_fb_ref_div()
97 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in amdgpu_pll_get_fb_ref_div()
98 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
135 unsigned post_div_min, post_div_max, post_div; in amdgpu_pll_compute() local
163 post_div_min = pll->post_div; in amdgpu_pll_compute()
164 post_div_max = pll->post_div; in amdgpu_pll_compute()
208 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in amdgpu_pll_compute()
210 amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max, in amdgpu_pll_compute()
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H A Datombios_crtc.c584 u32 post_div, in amdgpu_atombios_crtc_program_pll() argument
611 args.v1.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
621 args.v2.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
631 args.v3.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
648 args.v5.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
678 args.v6.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
825 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
851 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll()
854 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
861 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
H A Damdgpu_atombios.h28 u32 post_div; member
68 u32 post_div; member
H A Datombios_crtc.h51 u32 post_div,
H A Dsi.c1676 unsigned post_div = vco_freq / target_freq; in si_uvd_calc_upll_post_div() local
1679 if (post_div < pd_min) in si_uvd_calc_upll_post_div()
1680 post_div = pd_min; in si_uvd_calc_upll_post_div()
1683 if ((vco_freq / post_div) > target_freq) in si_uvd_calc_upll_post_div()
1684 post_div += 1; in si_uvd_calc_upll_post_div()
1687 if (post_div > pd_even && post_div % 2) in si_uvd_calc_upll_post_div()
1688 post_div += 1; in si_uvd_calc_upll_post_div()
1690 return post_div; in si_uvd_calc_upll_post_div()
/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2500.c49 unsigned int post_div; member
70 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) in ast2500_get_mpll_rate() local
73 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); in ast2500_get_mpll_rate()
89 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) in ast2500_get_hpll_rate() local
92 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); in ast2500_get_hpll_rate()
107 const ulong post_div = (dpll_reg >> 13) & 0x3f; in ast2500_get_dpll_rate() local
109 return (((clkin * ((num + 1) / (denum + 1))) / (post_div + 1))/ (od_div + 1)); in ast2500_get_dpll_rate()
124 const ulong post_div = (d2pll_reg >> 13) & 0x3f; in ast2500_get_d2pll_rate() local
127 return (((clkin * ((num + 1) / (denum + 1))) / (post_div + 1))/ (od_div + 1)); in ast2500_get_d2pll_rate()
249 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
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H A Dclk_ast2400.c32 unsigned int post_div; member
275 { 24000000, 250000000, { .num = 124, .denum = 1, .post_div = 5 } },
328 for (it.post_div = 0; it.post_div <= max_vals.post_div; in ast2400_calc_clock_config()
329 ++it.post_div) { in ast2400_calc_clock_config()
330 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) in ast2400_calc_clock_config()
337 / (it.post_div + 1); in ast2400_calc_clock_config()
362 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), in ast2400_configure_ddr()
370 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) in ast2400_configure_ddr()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
59 if (post_div == 2) in radeon_legacy_get_engine_clock()
61 else if (post_div == 3) in radeon_legacy_get_engine_clock()
63 else if (post_div == 4) in radeon_legacy_get_engine_clock()
73 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
89 if (post_div == 2) in radeon_legacy_get_memory_clock()
91 else if (post_div == 3) in radeon_legacy_get_memory_clock()
93 else if (post_div == 4) in radeon_legacy_get_memory_clock()
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H A Dradeon_display.c924 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in avivo_get_fb_ref_div() argument
929 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); in avivo_get_fb_ref_div()
932 *ref_div = min(max(den/post_div, 1u), ref_div_max); in avivo_get_fb_ref_div()
933 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
968 unsigned post_div_min, post_div_max, post_div; in radeon_compute_pll_avivo() local
999 post_div_min = pll->post_div; in radeon_compute_pll_avivo()
1000 post_div_max = pll->post_div; in radeon_compute_pll_avivo()
1044 for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { in radeon_compute_pll_avivo()
1046 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, in radeon_compute_pll_avivo()
1049 (ref_div * post_div)); in radeon_compute_pll_avivo()
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H A Dradeon_legacy_tv.c857 int post_div; in get_post_div() local
859 case 1: post_div = 0; break; in get_post_div()
860 case 2: post_div = 1; break; in get_post_div()
861 case 3: post_div = 4; break; in get_post_div()
862 case 4: post_div = 2; break; in get_post_div()
863 case 6: post_div = 6; break; in get_post_div()
864 case 8: post_div = 3; break; in get_post_div()
865 case 12: post_div = 7; break; in get_post_div()
867 default: post_div = 5; break; in get_post_div()
869 return post_div; in get_post_div()
H A Drv730_dpm.c62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
63 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
140 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
141 (dividers.post_div & 0xf) + 2; in rv730_populate_mclk_value()
153 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_mclk_value()
154 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_mclk_value()
H A Drv740_dpm.c142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
159 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
216 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
233 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
246 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
H A Dradeon_uvd.c912 unsigned post_div = vco_freq / target_freq; in radeon_uvd_calc_upll_post_div() local
915 if (post_div < pd_min) in radeon_uvd_calc_upll_post_div()
916 post_div = pd_min; in radeon_uvd_calc_upll_post_div()
919 if ((vco_freq / post_div) > target_freq) in radeon_uvd_calc_upll_post_div()
920 post_div += 1; in radeon_uvd_calc_upll_post_div()
923 if (post_div > pd_even && post_div % 2) in radeon_uvd_calc_upll_post_div()
924 post_div += 1; in radeon_uvd_calc_upll_post_div()
926 return post_div; in radeon_uvd_calc_upll_post_div()
H A Dradeon_legacy_crtc.c756 } *post_div, post_divs[] = { in radeon_set_pll() local
822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll()
823 if (post_div->divider == post_divider) in radeon_set_pll()
827 if (!post_div->divider) in radeon_set_pll()
828 post_div = &post_divs[0]; in radeon_set_pll()
843 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); in radeon_set_pll()
H A Drs780_dpm.c89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
454 (min_dividers.post_div != max_dividers.post_div) || in rs780_set_engine_clock_scaling()
456 (max_dividers.post_div != current_max_dividers.post_div)) in rs780_set_engine_clock_scaling()
989 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_debugfs_print_current_performance_level() local
992 (post_div * ref_div); in rs780_dpm_debugfs_print_current_performance_level()
1011 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_get_current_sclk() local
1014 (post_div * ref_div); in rs780_dpm_get_current_sclk()
H A Datombios_crtc.c824 u32 post_div, in atombios_crtc_program_pll() argument
851 args.v1.ucPostDiv = post_div; in atombios_crtc_program_pll()
861 args.v2.ucPostDiv = post_div; in atombios_crtc_program_pll()
871 args.v3.ucPostDiv = post_div; in atombios_crtc_program_pll()
888 args.v5.ucPostDiv = post_div; in atombios_crtc_program_pll()
917 args.v6.ucPostDiv = post_div; in atombios_crtc_program_pll()
1062 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1089 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1094 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1097 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
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/openbmc/u-boot/drivers/spi/
H A Dmxc_spi.c135 u32 pre_div = 0, post_div = 0; in spi_cfg_mxc() local
153 post_div = fls(pre_div); in spi_cfg_mxc()
154 if (post_div > 4) { in spi_cfg_mxc()
155 post_div -= 4; in spi_cfg_mxc()
156 if (post_div >= 16) { in spi_cfg_mxc()
161 pre_div >>= post_div; in spi_cfg_mxc()
163 post_div = 0; in spi_cfg_mxc()
167 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); in spi_cfg_mxc()
173 MXC_CSPICTRL_POSTDIV(post_div); in spi_cfg_mxc()
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dcpu.c58 int post_div; in clk_get() local
88 post_div = (readl(pll_base + PLLC_POSTDIV) & in clk_get()
91 pll_out /= post_div; in clk_get()
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c552 u32 post_div) in enable_pll_video() argument
568 switch (post_div) { in enable_pll_video()
626 u32 pll_div, pll_num, pll_denom, post_div = 1; in mxs_set_lcdclk() local
663 for (post_div = 2; post_div <= 4; post_div <<= 1) { in mxs_set_lcdclk()
664 if ((temp * post_div) > min) { in mxs_set_lcdclk()
665 freq *= post_div; in mxs_set_lcdclk()
670 if (post_div > 4) { in mxs_set_lcdclk()
710 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
747 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c474 enum root_post_div post_div; in get_ddrc_clk() local
484 post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK; in get_ddrc_clk()
486 return freq / (post_div + 1) / 2; in get_ddrc_clk()
776 u32 post_div) in enable_pll_video() argument
794 switch (post_div) { in enable_pll_video()
898 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local
909 post_div = i; in mxs_set_lcdclk()
946 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
H A Dclock_slice.c672 enum root_post_div post_div, enum clk_root_src clock_src) in clock_root_cfg() argument
698 if (post_div > CLK_ROOT_POST_DIV7) { in clock_root_cfg()
705 if (post_div != CLK_ROOT_POST_DIV1) { in clock_root_cfg()
716 post_div << CLK_ROOT_POST_DIV_SHIFT | in clock_root_cfg()
/openbmc/linux/drivers/clk/
H A Dclk-stm32f4.c1761 const struct stm32f4_pll_post_div_data *post_div; in stm32f4_rcc_init() local
1764 post_div = &post_div_data[n]; in stm32f4_rcc_init()
1766 hw = clk_register_pll_div(post_div->name, in stm32f4_rcc_init()
1767 post_div->parent, in stm32f4_rcc_init()
1768 post_div->flag, in stm32f4_rcc_init()
1769 base + post_div->offset, in stm32f4_rcc_init()
1770 post_div->shift, in stm32f4_rcc_init()
1771 post_div->width, in stm32f4_rcc_init()
1772 post_div->flag_div, in stm32f4_rcc_init()
1773 post_div->div_table, in stm32f4_rcc_init()
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c55 u32 post_div = 0; in read_pll() local
61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll()
64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll()
74 clock = clock / post_div; in read_pll()
/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c1527 } *post_div, in radeon_calc_pll_regs() local
1596 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_calc_pll_regs()
1597 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1601 if (uses_dvo && (post_div->divider & 1)) in radeon_calc_pll_regs()
1610 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1611 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1612 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1620 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1621 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1622 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
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/openbmc/u-boot/board/gdsys/common/
H A Dosd.c80 unsigned int *post_div, unsigned int *feedback_div) in mpc92469ac_calc_parameters() argument
82 unsigned int n = *post_div; in mpc92469ac_calc_parameters()
100 *post_div = n; in mpc92469ac_calc_parameters()

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