Home
last modified time | relevance | path

Searched refs:pmucru (Results 1 – 25 of 29) sorted by relevance

12

/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3399.c1248 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) in rk3399_i2c_get_pmuclk() argument
1254 con = readl(&pmucru->pmucru_clksel[2]); in rk3399_i2c_get_pmuclk()
1258 con = readl(&pmucru->pmucru_clksel[3]); in rk3399_i2c_get_pmuclk()
1262 con = readl(&pmucru->pmucru_clksel[2]); in rk3399_i2c_get_pmuclk()
1273 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, in rk3399_i2c_set_pmuclk() argument
1283 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), in rk3399_i2c_set_pmuclk()
1287 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), in rk3399_i2c_set_pmuclk()
1291 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), in rk3399_i2c_set_pmuclk()
1302 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) in rk3399_pwm_get_clk() argument
1307 con = readl(&pmucru->pmucru_clksel[0]); in rk3399_pwm_get_clk()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3399-dmc.txt5 - rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x.dtsi411 pmucru: clock-controller@fdd00000 { label
412 compatible = "rockchip,rk3568-pmucru";
425 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
427 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
435 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
448 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
461 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
472 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
483 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
494 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
[all …]
H A Drk3566-anbernic-rg353x.dtsi19 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
20 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3568.dtsi54 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
219 clocks = <&pmucru CLK_PCIEPHY0_REF>,
223 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
H A Drk3399.dtsi1248 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1261 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1274 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1276 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1289 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1291 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1304 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1306 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1322 clocks = <&pmucru PCLK_RKPWM_PMU>;
1332 clocks = <&pmucru PCLK_RKPWM_PMU>;
[all …]
H A Drk3566-anbernic-rg503.dts108 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
109 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-box-demo.dts73 clocks = <&pmucru CLK_RTC_32K>;
451 clocks = <&pmucru CLK_RTC_32K>;
469 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Dpx30.dtsi378 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
833 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
850 pmucru: clock-controller@ff2bc000 { label
851 compatible = "rockchip,px30-pmucru";
860 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
861 <&pmucru SCLK_WIFI_PMU>;
877 clocks = <&pmucru SCLK_USBPHY_REF>;
907 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
1398 clocks = <&pmucru PCLK_GPIO0_PMU>;
H A Drk3566-radxa-cm3-io.dts267 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-fastrhino-r66s.dtsi454 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-nanopi-r5s.dtsi574 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-lubancat-1.dts578 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-roc-pc.dts637 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-evb1-v10.dts676 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-odroid-m1.dts728 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-lubancat-2.dts678 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-soquartz.dtsi672 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-roc-pc.dts686 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-anbernic-rgxx3.dtsi775 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi225 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
239 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
250 pmucru: clock-controller@ff480000 { label
251 compatible = "rockchip,rv1126-pmucru";
527 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
/openbmc/u-boot/arch/arm/dts/
H A Drk3399.dtsi1094 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1107 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1120 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1122 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1135 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1137 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1150 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1152 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1168 clocks = <&pmucru PCLK_RKPWM_PMU>;
1179 clocks = <&pmucru PCLK_RKPWM_PMU>;
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/rk3399/
H A Dclk_rk3399.c52 return priv->pmucru; in rockchip_get_pmucru()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h17 struct rk3399_pmucru *pmucru; member
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3399.c37 struct rk3399_pmucru *pmucru; member
987 &dram->pmucru->pmucru_rstnhold_con[1]); in dram_all_config()
1146 priv->pmucru = rockchip_get_pmucru(); in rk3399_dmc_init()
1163 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); in rk3399_dmc_init()

12