| /openbmc/qemu/hw/intc/ |
| H A D | sifive_plic.c | 65 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level) in sifive_plic_set_pending() argument
67 atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level); in sifive_plic_set_pending()
70 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level) in sifive_plic_set_claimed() argument
72 atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level); in sifive_plic_set_claimed()
75 static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid) in sifive_plic_claimed() argument
78 uint32_t max_prio = plic->target_priority[addrid]; in sifive_plic_claimed()
82 for (i = 0; i < plic->bitfield_words; i++) { in sifive_plic_claimed()
84 (plic->pending[i] & ~plic->claimed[i]) & in sifive_plic_claimed()
85 plic->enable[addrid * plic->bitfield_words + i]; in sifive_plic_claimed()
91 if (i == (plic->bitfield_words - 1)) { in sifive_plic_claimed()
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| /openbmc/qemu/hw/riscv/ |
| H A D | opentitan.c | 130 object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC); in lowrisc_ibex_soc_init()
178 qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); in lowrisc_ibex_soc_realize()
179 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); in lowrisc_ibex_soc_realize()
180 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); in lowrisc_ibex_soc_realize()
181 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); in lowrisc_ibex_soc_realize()
182 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); in lowrisc_ibex_soc_realize()
183 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); in lowrisc_ibex_soc_realize()
184 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); in lowrisc_ibex_soc_realize()
185 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); in lowrisc_ibex_soc_realize()
186 qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); in lowrisc_ibex_soc_realize()
[all …]
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| H A D | microchip_pfsoc.c | 281 s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, in microchip_pfsoc_soc_realize()
300 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
309 qdev_get_gpio_in(DEVICE(s->plic), in microchip_pfsoc_soc_realize()
342 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); in microchip_pfsoc_soc_realize()
347 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), in microchip_pfsoc_soc_realize()
351 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), in microchip_pfsoc_soc_realize()
355 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), in microchip_pfsoc_soc_realize()
359 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), in microchip_pfsoc_soc_realize()
363 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), in microchip_pfsoc_soc_realize()
422 qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); in microchip_pfsoc_soc_realize()
[all …]
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| H A D | sifive_e.c | 210 s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, in sifive_e_soc_realize()
254 qdev_get_gpio_in(DEVICE(s->plic), in sifive_e_soc_realize()
258 qdev_get_gpio_in(DEVICE(s->plic), in sifive_e_soc_realize()
262 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); in sifive_e_soc_realize()
268 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); in sifive_e_soc_realize()
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| H A D | sifive_u.c | 830 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, in sifive_u_soc_realize()
843 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); in sifive_u_soc_realize()
845 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); in sifive_u_soc_realize()
871 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
882 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
900 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); in sifive_u_soc_realize()
913 qdev_get_gpio_in(DEVICE(s->plic), in sifive_u_soc_realize()
931 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); in sifive_u_soc_realize()
936 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); in sifive_u_soc_realize()
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| H A D | shakti_c.c | 111 sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base, in type_init()
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| /openbmc/linux/arch/riscv/boot/dts/microchip/ |
| H A D | mpfs.dtsi | 195 interrupt-parent = <&plic>;
209 plic: interrupt-controller@c000000 { label
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
226 interrupt-parent = <&plic>;
277 interrupt-parent = <&plic>;
289 interrupt-parent = <&plic>;
301 interrupt-parent = <&plic>;
313 interrupt-parent = <&plic>;
325 interrupt-parent = <&plic>;
336 interrupt-parent = <&plic>;
[all …]
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| H A D | mpfs-icicle-kit-fabric.dtsi | 23 interrupt-parent = <&plic>;
38 interrupt-parent = <&plic>;
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| H A D | mpfs-polarberry-fabric.dtsi | 26 interrupt-parent = <&plic>;
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| H A D | mpfs-m100pfs-fabric.dtsi | 26 interrupt-parent = <&plic>;
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| /openbmc/linux/arch/riscv/boot/dts/allwinner/ |
| H A D | sun20i-d1s.dtsi | 53 interrupt-parent = <&plic>;
63 plic: interrupt-controller@10000000 { label
64 compatible = "allwinner,sun20i-d1-plic",
65 "thead,c900-plic";
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| /openbmc/linux/arch/riscv/boot/dts/renesas/ |
| H A D | r9a07g043f.dtsi | 45 interrupt-parent = <&plic>;
47 plic: interrupt-controller@12c00000 { label
48 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
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| /openbmc/linux/arch/riscv/boot/dts/starfive/ |
| H A D | jh7100.dtsi | 138 interrupt-parent = <&plic>;
150 plic: interrupt-controller@c000000 { label
151 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
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| H A D | jh7110.dtsi | 334 interrupt-parent = <&plic>;
360 plic: interrupt-controller@c000000 { label
361 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
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| /openbmc/linux/arch/riscv/boot/dts/thead/ |
| H A D | th1520.dtsi | 139 interrupt-parent = <&plic>;
145 plic: interrupt-controller@ffd8000000 { label
146 compatible = "thead,th1520-plic", "thead,c900-plic";
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| /openbmc/qemu/include/hw/riscv/ |
| H A D | shakti_c.h | 36 DeviceState *plic; member
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| H A D | sifive_e.h | 38 DeviceState *plic; member
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| H A D | opentitan.h | 45 SiFivePLICState plic; member
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| H A D | sifive_u.h | 47 DeviceState *plic; member
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| H A D | microchip_pfsoc.h | 45 DeviceState *plic; member
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| /openbmc/linux/arch/riscv/boot/dts/sifive/ |
| H A D | fu540-c000.dtsi | 167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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| H A D | fu740-c000.dtsi | 170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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| /openbmc/linux/arch/riscv/boot/dts/canaan/ |
| H A D | k210.dtsi | 127 compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
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| /openbmc/linux/drivers/irqchip/ |
| H A D | Makefile | 98 obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
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| /openbmc/u-boot/doc/ |
| H A D | README.sifive-fu540 | 197 [ 0.000000] plic: mapped 53 interrupts to 4 (out of 9) handlers.
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