xref: /openbmc/qemu/include/hw/riscv/opentitan.h (revision 7efd65423ab22e6f5890ca08ae40c84d6660242f)
1fe0fe473SAlistair Francis /*
2fe0fe473SAlistair Francis  * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3fe0fe473SAlistair Francis  *
4fe0fe473SAlistair Francis  * Copyright (c) 2020 Western Digital
5fe0fe473SAlistair Francis  *
6fe0fe473SAlistair Francis  * This program is free software; you can redistribute it and/or modify it
7fe0fe473SAlistair Francis  * under the terms and conditions of the GNU General Public License,
8fe0fe473SAlistair Francis  * version 2 or later, as published by the Free Software Foundation.
9fe0fe473SAlistair Francis  *
10fe0fe473SAlistair Francis  * This program is distributed in the hope it will be useful, but WITHOUT
11fe0fe473SAlistair Francis  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12fe0fe473SAlistair Francis  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13fe0fe473SAlistair Francis  * more details.
14fe0fe473SAlistair Francis  *
15fe0fe473SAlistair Francis  * You should have received a copy of the GNU General Public License along with
16fe0fe473SAlistair Francis  * this program.  If not, see <http://www.gnu.org/licenses/>.
17fe0fe473SAlistair Francis  */
18fe0fe473SAlistair Francis 
19fe0fe473SAlistair Francis #ifndef HW_OPENTITAN_H
20fe0fe473SAlistair Francis #define HW_OPENTITAN_H
21fe0fe473SAlistair Francis 
22fe0fe473SAlistair Francis #include "hw/riscv/riscv_hart.h"
23ef631006SAlistair Francis #include "hw/intc/sifive_plic.h"
24cc411260SAlistair Francis #include "hw/char/ibex_uart.h"
253ef64344SAlistair Francis #include "hw/timer/ibex_timer.h"
269972479fSWilfred Mallawa #include "hw/ssi/ibex_spi_host.h"
278696b74aSPhilippe Mathieu-Daudé #include "hw/boards.h"
28db1015e9SEduardo Habkost #include "qom/object.h"
29fe0fe473SAlistair Francis 
30fe0fe473SAlistair Francis #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
318063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
32fe0fe473SAlistair Francis 
339972479fSWilfred Mallawa enum {
349972479fSWilfred Mallawa     OPENTITAN_SPI_HOST0,
359972479fSWilfred Mallawa     OPENTITAN_SPI_HOST1,
369972479fSWilfred Mallawa     OPENTITAN_NUM_SPI_HOSTS,
379972479fSWilfred Mallawa };
389972479fSWilfred Mallawa 
39db1015e9SEduardo Habkost struct LowRISCIbexSoCState {
40fe0fe473SAlistair Francis     /*< private >*/
41fe0fe473SAlistair Francis     SysBusDevice parent_obj;
42fe0fe473SAlistair Francis 
43fe0fe473SAlistair Francis     /*< public >*/
44fe0fe473SAlistair Francis     RISCVHartArrayState cpus;
45ef631006SAlistair Francis     SiFivePLICState plic;
46cc411260SAlistair Francis     IbexUartState uart;
473ef64344SAlistair Francis     IbexTimerState timer;
489972479fSWilfred Mallawa     IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
49b9fc5135SAlistair Francis 
50a06fded8SAlistair Francis     uint32_t resetvec;
51a06fded8SAlistair Francis 
52fe0fe473SAlistair Francis     MemoryRegion flash_mem;
53fe0fe473SAlistair Francis     MemoryRegion rom;
54bb7e0cdeSAlistair Francis     MemoryRegion flash_alias;
55db1015e9SEduardo Habkost };
56fe0fe473SAlistair Francis 
578696b74aSPhilippe Mathieu-Daudé #define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan")
58*a828ba9dSPhilippe Mathieu-Daudé OBJECT_DECLARE_SIMPLE_TYPE(OpenTitanState, OPENTITAN_MACHINE)
59264495f9SPhilippe Mathieu-Daudé 
60fe0fe473SAlistair Francis typedef struct OpenTitanState {
61fe0fe473SAlistair Francis     /*< private >*/
62*a828ba9dSPhilippe Mathieu-Daudé     MachineState parent_obj;
63fe0fe473SAlistair Francis 
64fe0fe473SAlistair Francis     /*< public >*/
65fe0fe473SAlistair Francis     LowRISCIbexSoCState soc;
66fe0fe473SAlistair Francis } OpenTitanState;
67fe0fe473SAlistair Francis 
68fe0fe473SAlistair Francis enum {
6930c717cbSEduardo Habkost     IBEX_DEV_ROM,
7030c717cbSEduardo Habkost     IBEX_DEV_RAM,
7130c717cbSEduardo Habkost     IBEX_DEV_FLASH,
72bb7e0cdeSAlistair Francis     IBEX_DEV_FLASH_VIRTUAL,
7330c717cbSEduardo Habkost     IBEX_DEV_UART,
74aecabd50SWilfred Mallawa     IBEX_DEV_SPI_DEVICE,
75aecabd50SWilfred Mallawa     IBEX_DEV_SPI_HOST0,
76aecabd50SWilfred Mallawa     IBEX_DEV_SPI_HOST1,
7730c717cbSEduardo Habkost     IBEX_DEV_GPIO,
78d31e970aSAlistair Francis     IBEX_DEV_I2C,
79d31e970aSAlistair Francis     IBEX_DEV_PATTGEN,
803ef64344SAlistair Francis     IBEX_DEV_TIMER,
81d31e970aSAlistair Francis     IBEX_DEV_SENSOR_CTRL,
82d31e970aSAlistair Francis     IBEX_DEV_OTP_CTRL,
83bf8803c6SWilfred Mallawa     IBEX_DEV_LC_CTRL,
8430c717cbSEduardo Habkost     IBEX_DEV_PWRMGR,
8530c717cbSEduardo Habkost     IBEX_DEV_RSTMGR,
8630c717cbSEduardo Habkost     IBEX_DEV_CLKMGR,
8730c717cbSEduardo Habkost     IBEX_DEV_PINMUX,
88aefd1108SWilfred Mallawa     IBEX_DEV_AON_TIMER,
89d31e970aSAlistair Francis     IBEX_DEV_USBDEV,
90d31e970aSAlistair Francis     IBEX_DEV_FLASH_CTRL,
91d31e970aSAlistair Francis     IBEX_DEV_PLIC,
92d31e970aSAlistair Francis     IBEX_DEV_AES,
93d31e970aSAlistair Francis     IBEX_DEV_HMAC,
94d31e970aSAlistair Francis     IBEX_DEV_KMAC,
95d31e970aSAlistair Francis     IBEX_DEV_KEYMGR,
96d31e970aSAlistair Francis     IBEX_DEV_CSRNG,
97d31e970aSAlistair Francis     IBEX_DEV_ENTROPY,
98d31e970aSAlistair Francis     IBEX_DEV_EDNO,
99d31e970aSAlistair Francis     IBEX_DEV_EDN1,
10030c717cbSEduardo Habkost     IBEX_DEV_ALERT_HANDLER,
1017ae71462SWilfred Mallawa     IBEX_DEV_SRAM_CTRL,
102d31e970aSAlistair Francis     IBEX_DEV_OTBN,
1037ae71462SWilfred Mallawa     IBEX_DEV_IBEX_CFG,
104fe0fe473SAlistair Francis };
105fe0fe473SAlistair Francis 
106cc411260SAlistair Francis enum {
107d4cad544SAlistair Francis     IBEX_UART0_TX_WATERMARK_IRQ   = 1,
1089972479fSWilfred Mallawa     IBEX_UART0_RX_WATERMARK_IRQ   = 2,
1099972479fSWilfred Mallawa     IBEX_UART0_TX_EMPTY_IRQ       = 3,
1109972479fSWilfred Mallawa     IBEX_UART0_RX_OVERFLOW_IRQ    = 4,
1119972479fSWilfred Mallawa     IBEX_UART0_RX_FRAME_ERR_IRQ   = 5,
1129972479fSWilfred Mallawa     IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
1139972479fSWilfred Mallawa     IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
1149972479fSWilfred Mallawa     IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
1157ae71462SWilfred Mallawa     IBEX_TIMER_TIMEREXPIRED0_0    = 124,
1167ae71462SWilfred Mallawa     IBEX_SPI_HOST0_ERR_IRQ        = 131,
1177ae71462SWilfred Mallawa     IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 132,
1187ae71462SWilfred Mallawa     IBEX_SPI_HOST1_ERR_IRQ        = 133,
1197ae71462SWilfred Mallawa     IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 134,
120cc411260SAlistair Francis };
121cc411260SAlistair Francis 
122fe0fe473SAlistair Francis #endif
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