Home
last modified time | relevance | path

Searched refs:pixel_clk (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8195.c213 u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; in mtk_hdmi_pll_calc() local
218 pixel_clk = rate; in mtk_hdmi_pll_calc()
219 tmds_clk = pixel_clk; in mtk_hdmi_pll_calc()
291 digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); in mtk_hdmi_pll_calc()
307 u32 pixel_clk = hdmi_phy->pll_rate; in mtk_hdmi_pll_drv_setting() local
309 tmds_clk = pixel_clk; in mtk_hdmi_pll_drv_setting()
327 } else if (((u64)pixel_clk * 1000) >= 74175 * MEGA && pixel_clk <= 300 * MEGA) { in mtk_hdmi_pll_drv_setting()
332 } else if (pixel_clk >= 27 * MEGA && ((u64)pixel_clk * 1000) < 74175 * MEGA) { in mtk_hdmi_pll_drv_setting()
/openbmc/linux/drivers/media/platform/cadence/
H A Dcdns-csi2rx.c77 struct clk *pixel_clk[CSI2RX_STREAMS_MAX]; member
196 ret = clk_prepare_enable(csi2rx->pixel_clk[i]); in csi2rx_start()
232 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); in csi2rx_start()
257 clk_disable_unprepare(csi2rx->pixel_clk[i]); in csi2rx_stop()
425 csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name); in csi2rx_get_resources()
426 if (IS_ERR(csi2rx->pixel_clk[i])) { in csi2rx_get_resources()
428 return PTR_ERR(csi2rx->pixel_clk[i]); in csi2rx_get_resources()
H A Dcdns-csi2tx.c108 struct clk *pixel_clk[CSI2TX_STREAMS_MAX]; member
486 csi2tx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name); in csi2tx_get_resources()
487 if (IS_ERR(csi2tx->pixel_clk[i])) { in csi2tx_get_resources()
490 return PTR_ERR(csi2tx->pixel_clk[i]); in csi2tx_get_resources()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_audio.c426 unsigned int h_active, h_total, hblank_delta, pixel_clk; in calc_hblank_early_prog() local
433 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; in calc_hblank_early_prog()
445 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk)) in calc_hblank_early_prog()
448 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; in calc_hblank_early_prog()
449 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); in calc_hblank_early_prog()
454 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), in calc_hblank_early_prog()
457 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000), in calc_hblank_early_prog()
460 mul_u32_u32(64 * pixel_clk, 1000000)); in calc_hblank_early_prog()
463 …hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_… in calc_hblank_early_prog()
470 unsigned int h_active, h_total, pixel_clk; in calc_samples_room() local
[all …]
/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dpi.c72 struct clk *pixel_clk; member
473 clk_disable_unprepare(dpi->pixel_clk); in mtk_dpi_power_off()
490 ret = clk_prepare_enable(dpi->pixel_clk); in mtk_dpi_power_on()
539 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); in mtk_dpi_set_display_mode()
541 clk_set_rate(dpi->pixel_clk, vm.pixelclock); in mtk_dpi_set_display_mode()
544 vm.pixelclock = clk_get_rate(dpi->pixel_clk); in mtk_dpi_set_display_mode()
1035 dpi->pixel_clk = devm_clk_get(dev, "pixel"); in mtk_dpi_probe()
1036 if (IS_ERR(dpi->pixel_clk)) in mtk_dpi_probe()
1037 return dev_err_probe(dev, PTR_ERR(dpi->pixel_clk), in mtk_dpi_probe()
/openbmc/linux/drivers/gpu/drm/stm/
H A Dltdc.c842 result = clk_round_rate(ldev->pixel_clk, target); in ltdc_crtc_mode_valid()
878 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { in ltdc_crtc_mode_fixup()
883 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; in ltdc_crtc_mode_fixup()
1878 clk_disable_unprepare(ldev->pixel_clk); in ltdc_suspend()
1888 ret = clk_prepare_enable(ldev->pixel_clk); in ltdc_resume()
1918 ldev->pixel_clk = devm_clk_get(dev, "lcd"); in ltdc_load()
1919 if (IS_ERR(ldev->pixel_clk)) { in ltdc_load()
1920 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) in ltdc_load()
1922 return PTR_ERR(ldev->pixel_clk); in ltdc_load()
1925 if (clk_prepare_enable(ldev->pixel_clk)) { in ltdc_load()
[all …]
H A Dltdc.h46 struct clk *pixel_clk; /* lcd pixel clock */ member
/openbmc/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.c564 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) in hdmi_compute_n() argument
576 if (pixel_clk == 25175000) in hdmi_compute_n()
578 else if (pixel_clk == 27027000) in hdmi_compute_n()
580 else if (pixel_clk == 74176000 || pixel_clk == 148352000) in hdmi_compute_n()
582 else if (pixel_clk == 297000000) in hdmi_compute_n()
590 if (pixel_clk == 25175000) in hdmi_compute_n()
592 else if (pixel_clk == 74176000) in hdmi_compute_n()
594 else if (pixel_clk == 148352000) in hdmi_compute_n()
596 else if (pixel_clk == 297000000) in hdmi_compute_n()
604 if (pixel_clk == 25175000) in hdmi_compute_n()
[all …]
/openbmc/u-boot/drivers/video/
H A Ddw_hdmi.c145 static int hdmi_lookup_n_cts(u32 pixel_clk) in hdmi_lookup_n_cts() argument
150 if (pixel_clk <= n_cts_table[i].tmds) in hdmi_lookup_n_cts()
159 static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 pixel_clk) in hdmi_audio_set_samplerate() argument
164 index = hdmi_lookup_n_cts(pixel_clk); in hdmi_audio_set_samplerate()
166 debug("audio not supported for pixel clk %d\n", pixel_clk); in hdmi_audio_set_samplerate()
H A Dipu_disp.c827 int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, in ipu_init_sync_panel() argument
857 debug("pixel clk = %dHz\n", pixel_clk); in ipu_init_sync_panel()
870 pixel_clk); in ipu_init_sync_panel()
890 rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); in ipu_init_sync_panel()
H A Dipu.h229 uint32_t pixel_clk,
H A Dipu_common.c403 static struct clk pixel_clk[] = { variable
483 g_pixel_clk[0] = &pixel_clk[0]; in ipu_probe()
484 g_pixel_clk[1] = &pixel_clk[1]; in ipu_probe()
/openbmc/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c120 struct clk *pixel_clk; member
313 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); in dsi_clk_init()
314 if (IS_ERR(msm_host->pixel_clk)) { in dsi_clk_init()
315 ret = PTR_ERR(msm_host->pixel_clk); in dsi_clk_init()
318 msm_host->pixel_clk = NULL; in dsi_clk_init()
379 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_6g()
414 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
430 clk_disable_unprepare(msm_host->pixel_clk); in dsi_link_clk_enable_6g()
465 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); in dsi_link_clk_set_rate_v2()
496 ret = clk_prepare_enable(msm_host->pixel_clk); in dsi_link_clk_enable_v2()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h179 unsigned int pixel_clk,
/openbmc/linux/drivers/gpu/drm/aspeed/
H A Daspeed_gfx_crtc.c93 clk_set_rate(priv->pixel_clk, m->crtc_clock * 1000); in aspeed_gfx_crtc_mode_set_nofb()
/openbmc/linux/drivers/gpu/ipu-v3/
H A Dipu-csi.c192 static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk, in ipu_csi_set_testgen_mclk() argument
198 div_ratio = (ipu_clk / pixel_clk) - 1; in ipu_csi_set_testgen_mclk()
/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h128 uint32_t pixel_clk; /* in KHz */ member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table.c1542 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v2() local
1546 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v2()
1592 uint64_t pixel_clk = (uint64_t)bp_params->pixel_clock; in adjust_display_pll_v3() local
1596 div_u64(pixel_clk * pixel_clk_10_khz_out, in adjust_display_pll_v3()
H A Dbios_parser.c1248 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_2()
1366 info->lcd_timing.pixel_clk = in get_embedded_panel_info_v1_3()
H A Dbios_parser2.c1453 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10; in get_embedded_panel_info_v2_1()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c1193 unsigned int pixel_clk, in dcn20_override_dp_pix_clk() argument
1199 REG_WRITE(PHASE[inst], pixel_clk); in dcn20_override_dp_pix_clk()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c678 u64 pixel_clk = 0; in vgpu_update_refresh_rate() local
683 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); in vgpu_update_refresh_rate()
684 pixel_clk *= MSEC_PER_SEC; in vgpu_update_refresh_rate()
687 …new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal… in vgpu_update_refresh_rate()