1ec17f034SBenjamin Gaignard /* SPDX-License-Identifier: GPL-2.0 */ 2b759012cSYannick Fertre /* 3b759012cSYannick Fertre * Copyright (C) STMicroelectronics SA 2017 4b759012cSYannick Fertre * 5b759012cSYannick Fertre * Authors: Philippe Cornu <philippe.cornu@st.com> 6b759012cSYannick Fertre * Yannick Fertre <yannick.fertre@st.com> 7b759012cSYannick Fertre * Fabien Dessenne <fabien.dessenne@st.com> 8b759012cSYannick Fertre * Mickael Reulier <mickael.reulier@st.com> 9b759012cSYannick Fertre */ 10b759012cSYannick Fertre 11b759012cSYannick Fertre #ifndef _LTDC_H_ 12b759012cSYannick Fertre #define _LTDC_H_ 13b759012cSYannick Fertre 14b759012cSYannick Fertre struct ltdc_caps { 15b759012cSYannick Fertre u32 hw_version; /* hardware version */ 16b759012cSYannick Fertre u32 nb_layers; /* number of supported layers */ 171726cee3SYannick Fertre u32 layer_ofs; /* layer offset for applicable regs */ 181726cee3SYannick Fertre const u32 *layer_regs; /* layer register offset */ 19b759012cSYannick Fertre u32 bus_width; /* bus width (32 or 64 bits) */ 208f2b5f6dSYannick Fertre const u32 *pix_fmt_hw; /* supported hw pixel formats */ 218f2b5f6dSYannick Fertre const u32 *pix_fmt_drm; /* supported drm pixel formats */ 228f2b5f6dSYannick Fertre int pix_fmt_nb; /* number of pixel format */ 238f2b5f6dSYannick Fertre bool pix_fmt_flex; /* pixel format flexibility supported */ 249569002aSPhilippe CORNU bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */ 257868e507SYannick Fertre int pad_max_freq_hz; /* max frequency supported by pad */ 26544aa6ceSYannick Fertre int nb_irq; /* number of hardware interrupts */ 27484e72d3SYannick Fertre bool ycbcr_input; /* ycbcr input converter supported */ 28fb998edfSYannick Fertre bool ycbcr_output; /* ycbcr output converter supported */ 29a55d08e0SYannick Fertre bool plane_reg_shadow; /* plane shadow registers ability */ 3079b44684SRaphael Gallais-Pou bool crc; /* cyclic redundancy check supported */ 3162467fccSYannick Fertre bool dynamic_zorder; /* dynamic z-order */ 32c6193dc5SYannick Fertre bool plane_rotation; /* plane rotation */ 33*7d008eecSYannick Fertre bool fifo_threshold; /* fifo underrun threshold supported */ 34b759012cSYannick Fertre }; 35b759012cSYannick Fertre 3625bb1a9dSPhilippe CORNU #define LTDC_MAX_LAYER 4 3725bb1a9dSPhilippe CORNU 3825bb1a9dSPhilippe CORNU struct fps_info { 3925bb1a9dSPhilippe CORNU unsigned int counter; 4025bb1a9dSPhilippe CORNU ktime_t last_timestamp; 4125bb1a9dSPhilippe CORNU }; 4225bb1a9dSPhilippe CORNU 43b759012cSYannick Fertre struct ltdc_device { 44b759012cSYannick Fertre void __iomem *regs; 45734c2645SYannick Fertre struct regmap *regmap; 46b759012cSYannick Fertre struct clk *pixel_clk; /* lcd pixel clock */ 47b759012cSYannick Fertre struct mutex err_lock; /* protecting error_status */ 48b759012cSYannick Fertre struct ltdc_caps caps; 49b759012cSYannick Fertre u32 irq_status; 50*7d008eecSYannick Fertre u32 fifo_err; /* fifo underrun error counter */ 51*7d008eecSYannick Fertre u32 fifo_warn; /* fifo underrun warning counter */ 52*7d008eecSYannick Fertre u32 fifo_threshold; /* fifo underrun threshold */ 53*7d008eecSYannick Fertre u32 transfer_err; /* transfer error counter */ 5425bb1a9dSPhilippe CORNU struct fps_info plane_fpsi[LTDC_MAX_LAYER]; 55df61c776SYannick Fertré struct drm_atomic_state *suspend_state; 5679b44684SRaphael Gallais-Pou int crc_skip_count; 5779b44684SRaphael Gallais-Pou bool crc_active; 58b759012cSYannick Fertre }; 59b759012cSYannick Fertre 60b759012cSYannick Fertre int ltdc_load(struct drm_device *ddev); 61b759012cSYannick Fertre void ltdc_unload(struct drm_device *ddev); 62df61c776SYannick Fertré void ltdc_suspend(struct drm_device *ddev); 63df61c776SYannick Fertré int ltdc_resume(struct drm_device *ddev); 64b759012cSYannick Fertre 65b759012cSYannick Fertre #endif 66