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Searched refs:pir (Results 1 – 25 of 72) sorted by relevance

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/openbmc/linux/drivers/net/ethernet/mscc/
H A Docelot_police.c27 u32 cir = 0, cbs = 0, pir = 0, pbs = 0; in qos_policer_conf_set() local
33 pir = conf->pir; in qos_policer_conf_set()
60 pir += conf->cir; in qos_policer_conf_set()
63 if (pir == 0 && pbs == 0) { in qos_policer_conf_set()
67 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
68 pir *= 3; /* 33 1/3 kbps */ in qos_policer_conf_set()
75 if (pir >= 100) { in qos_policer_conf_set()
77 pir = DIV_ROUND_UP(pir, 100); in qos_policer_conf_set()
78 pir *= 3; /* 33 1/3 fps */ in qos_policer_conf_set()
84 if (pir == 0 && pbs == 0) { in qos_policer_conf_set()
[all …]
H A Docelot_police.h29 u32 pir; /* PIR in kbps/fps */ member
/openbmc/qemu/include/hw/ppc/
H A Dpnv_chip.h106 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) argument
107 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) argument
140 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) argument
141 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) argument
142 #define PNV10_PIR2THREAD(pir) (((pir) & 0x7f)) argument
161 uint32_t *pir, uint32_t *tir);
H A Dpnv_core.h61 uint32_t pir; member
/openbmc/qemu/tests/qtest/
H A Dpnv-xive2-test.c64 static void set_tima8(QTestState *qts, uint32_t pir, uint32_t offset, in set_tima8() argument
69 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in set_tima8()
73 static void set_tima32(QTestState *qts, uint32_t pir, uint32_t offset, in set_tima32() argument
78 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in set_tima32()
82 static uint8_t get_tima8(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima8() argument
86 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in get_tima8()
90 static uint16_t get_tima16(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima16() argument
94 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in get_tima16()
98 static uint32_t get_tima32(QTestState *qts, uint32_t pir, uint32_t offset) in get_tima32() argument
102 ic_addr = XIVE_IC_TM_INDIRECT + (pir << XIVE_PAGE_SHIFT); in get_tima32()
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr.c266 void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) in stm32mp1_ddrphy_init() argument
268 pir |= DDRPHYC_PIR_INIT; in stm32mp1_ddrphy_init()
269 writel(pir, &phy->pir); in stm32mp1_ddrphy_init()
271 (u32)&phy->pir, pir, readl(&phy->pir)); in stm32mp1_ddrphy_init()
367 u32 pir; in stm32mp1_ddr_init() local
448 pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL | in stm32mp1_ddr_init()
452 pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */ in stm32mp1_ddr_init()
454 stm32mp1_ddrphy_init(priv->phy, pir); in stm32mp1_ddr_init()
/openbmc/linux/arch/x86/include/asm/
H A Dposted_intr.h12 u32 pir[8]; /* Posted interrupt requested */ member
50 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); in pi_test_and_set_pir()
55 return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS); in pi_is_pir_empty()
/openbmc/qemu/hw/ppc/
H A Dpnv.c146 uint32_t pir, tir; in pnv_dt_core() local
157 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); in pnv_dt_core()
162 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); in pnv_dt_core()
169 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); in pnv_dt_core()
170 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); in pnv_dt_core()
244 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
245 servers_prop[i * 2] = cpu_to_be32(pir); in pnv_dt_core()
247 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); in pnv_dt_core()
248 servers_prop[i * 2 + 1] = cpu_to_be32(pir); in pnv_dt_core()
256 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); in pnv_dt_core()
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H A Dppce500_spin.c46 uint32_t pir; member
68 stl_p(&info->pir, i); in spin_reset()
82 stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]); in spin_kick()
/openbmc/linux/arch/powerpc/platforms/powernv/
H A Didle.c81 uint64_t pir = get_hard_smp_processor_id(cpu); in pnv_save_sprs_for_deep_states() local
84 rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); in pnv_save_sprs_for_deep_states()
88 rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); in pnv_save_sprs_for_deep_states()
93 rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); in pnv_save_sprs_for_deep_states()
97 rc = opal_slw_set_reg(pir, in pnv_save_sprs_for_deep_states()
107 rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); in pnv_save_sprs_for_deep_states()
111 rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); in pnv_save_sprs_for_deep_states()
121 rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); in pnv_save_sprs_for_deep_states()
125 rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); in pnv_save_sprs_for_deep_states()
129 rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); in pnv_save_sprs_for_deep_states()
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H A Dopal-core.c111 static void __init fill_prstatus(struct elf_prstatus *prstatus, int pir, in fill_prstatus() argument
122 prstatus->common.pr_pid = cpu_to_be32(100 + pir); in fill_prstatus()
129 if (pir == oc_conf->crashing_cpu) { in fill_prstatus()
260 thread_pir = be32_to_cpu(thdr->pir); in opalcore_append_cpu_notes()
/openbmc/qemu/hw/intc/
H A Dpnv_xive2.c411 int pir = pnv_xive2_get_current_pir(xive); in pnv_xive2_inject_notify() local
412 int thread_nr = PNV10_PIR2THREAD(pir); in pnv_xive2_inject_notify()
413 int thread_topo_id = PNV10_PIR2CHIP(pir); in pnv_xive2_inject_notify()
618 int pir = ppc_cpu_pir(cpu); in pnv_xive2_is_cpu_enabled() local
619 uint32_t fc = PNV10_PIR2FUSEDCORE(pir); in pnv_xive2_is_cpu_enabled()
621 uint32_t bit = pir & 0x3f; in pnv_xive2_is_cpu_enabled()
708 int pir = ppc_cpu_pir(cpu); in pnv_xive2_tm_get_xive() local
713 xive2_error(xive, "IC: CPU %x is not enabled", pir); in pnv_xive2_tm_get_xive()
2045 static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir) in pnv_xive2_get_indirect_tctx() argument
2050 cpu = pnv_chip_find_cpu(chip, pir); in pnv_xive2_get_indirect_tctx()
[all …]
H A Dpnv_xive.c466 int pir = ppc_cpu_pir(cpu); in pnv_xive_is_cpu_enabled() local
467 uint32_t fc = PNV9_PIR2FUSEDCORE(pir); in pnv_xive_is_cpu_enabled()
469 uint32_t bit = pir & 0x3f; in pnv_xive_is_cpu_enabled()
548 int pir = ppc_cpu_pir(cpu); in pnv_xive_tm_get_xive() local
553 xive_error(xive, "IC: CPU %x is not enabled", pir); in pnv_xive_tm_get_xive()
1578 int pir; in pnv_xive_get_indirect_tctx() local
1585 pir = (chip->chip_id << 8) | GETFIELD(PC_TCTXT_INDIR_THRDID, tctxt_indir); in pnv_xive_get_indirect_tctx()
1586 cpu = pnv_chip_find_cpu(chip, pir); in pnv_xive_get_indirect_tctx()
1588 xive_error(xive, "IC: invalid PIR %x for indirect access", pir); in pnv_xive_get_indirect_tctx()
1594 xive_error(xive, "IC: CPU %x is not enabled", pir); in pnv_xive_get_indirect_tctx()
H A Dxive2.c278 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_save_ctx() local
307 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { in xive2_tctx_save_ctx()
310 nvp_blk, nvp_idx, pir); in xive2_tctx_save_ctx()
345 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_hw_cam_line() local
351 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); in xive2_tctx_hw_cam_line()
516 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_restore_os_ctx() local
534 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); in xive2_tctx_restore_os_ctx()
/openbmc/linux/drivers/net/ethernet/freescale/enetc/
H A Denetc_cbdr.c28 cbdr->pir = hw->reg + ENETC_SICBDRPIR; in enetc_setup_cbdr()
40 enetc_wr_reg(cbdr->pir, cbdr->next_to_clean); in enetc_setup_cbdr()
113 enetc_wr_reg(ring->pir, i); in enetc_send_cmd()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmp.c48 out_be32(&pic->pir, 1 << nr); in cpu_reset()
50 (void)in_be32(&pic->pir); in cpu_reset()
51 out_be32(&pic->pir, 0x0); in cpu_reset()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun6i.c159 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
160 writel(MCTL_PIR_STEP1, &mctl_phy->pir); in mctl_channel_init()
190 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
191 writel(MCTL_PIR_STEP2, &mctl_phy->pir); in mctl_channel_init()
H A Ddram_sun8i_a23.c231 writel(0x00000003, &mctl_phy->pir); in mctl_init()
239 writel(0x000005f3, &mctl_phy->pir); in mctl_init()
247 writel(0x5f3, &mctl_phy->pir); in mctl_init()
H A Ddram_sunxi_dw.c23 writel(val | PIR_INIT, &mctl_ctl->pir); in mctl_phy_init()
286 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
313 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
319 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
/openbmc/linux/arch/x86/kvm/vmx/
H A Dposted_intr.h21 vec = find_last_bit((unsigned long *)pi_desc->pir, 256); in pi_find_highest_vector()
/openbmc/linux/arch/powerpc/kvm/
H A De500_emulate.c67 int pir = param & PPC_DBELL_PIR_MASK; in kvmppc_e500_emul_msgsnd() local
75 int cpir = cvcpu->arch.shared->pir; in kvmppc_e500_emul_msgsnd()
76 if ((param & PPC_DBELL_MSG_BRDCAST) || (cpir == pir)) { in kvmppc_e500_emul_msgsnd()
/openbmc/linux/arch/powerpc/include/uapi/asm/
H A Dkvm_para.h59 __u32 pir; member
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c159 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
168 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
300 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
328 setbits_le32(&publ->pir, in memory_init()
436 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
439 setbits_le32(&publ->pir, in data_training()
H A Dsdram_rk3288.c158 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
167 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
358 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
386 setbits_le32(&publ->pir, in memory_init()
494 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
497 setbits_le32(&publ->pir, in data_training()
/openbmc/linux/arch/powerpc/platforms/85xx/
H A Dsmp.c40 u32 pir; member
250 out_be32(&spin_table->pir, hw_cpu); in smp_85xx_start_cpu()

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